1 /* Instruction printing code for the ARC.
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
27 #include "opcode/arc.h"
31 /* Structure used to iterate over, and extract the values for, operands of
34 struct arc_operand_iterator
38 OPERAND_ITERATOR_STANDARD,
42 /* The array of 32-bit values that make up this instruction. All
43 required values have been pre-loaded into this array during the
51 /* The opcode this iterator is operating on. */
52 const struct arc_opcode *opcode;
54 /* The index into the opcodes operand index list. */
55 const unsigned char *opidx;
60 /* The long instruction opcode this iterator is operating on. */
61 const struct arc_long_opcode *long_opcode;
63 /* Two indexes into the opcodes operand index lists. */
64 const unsigned char *opidx_base, *opidx_limm;
69 /* Globals variables. */
71 static const char * const regnames[64] =
73 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
74 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
75 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
76 "r24", "r25", "gp", "fp", "sp", "ilink", "r30", "blink",
78 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
79 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
80 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
81 "r56", "r57", "ACCL", "ACCH", "lp_count", "rezerved", "LIMM", "pcl"
87 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
89 # define pr_debug(fmt, args...)
92 #define ARRANGE_ENDIAN(info, buf) \
93 (info->endian == BFD_ENDIAN_LITTLE ? bfd_getm32 (bfd_getl32 (buf)) \
96 #define BITS(word,s,e) (((word) << (sizeof (word) * 8 - 1 - e)) >> \
97 (s + (sizeof (word) * 8 - 1 - e)))
98 #define OPCODE(word) (BITS ((word), 27, 31))
100 #define OPCODE_AC(word) (BITS ((word), 11, 15))
102 /* Functions implementation. */
105 bfd_getm32 (unsigned int data)
109 value = ((data & 0xff00) | (data & 0xff)) << 16;
110 value |= ((data & 0xff0000) | (data & 0xff000000)) >> 16;
115 special_flag_p (const char *opname,
118 const struct arc_flag_special *flg_spec;
119 unsigned i, j, flgidx;
121 for (i = 0; i < arc_num_flag_special; i++)
123 flg_spec = &arc_flag_special_cases[i];
125 if (strcmp (opname, flg_spec->name))
128 /* Found potential special case instruction. */
131 flgidx = flg_spec->flags[j];
133 break; /* End of the array. */
135 if (strcmp (flgname, arc_flag_operands[flgidx].name) == 0)
142 /* Find opcode from ARC_TABLE given the instruction described by INSN and
143 INSNLEN. The ISA_MASK restricts the possible matches in ARC_TABLE. */
145 static const struct arc_opcode *
146 find_format_from_table (const struct arc_opcode *arc_table,
147 unsigned *insn, unsigned int insn_len,
148 unsigned isa_mask, bfd_boolean *has_limm)
151 const struct arc_opcode *opcode = NULL;
152 const unsigned char *opidx;
153 const unsigned char *flgidx;
156 bfd_boolean invalid = FALSE;
158 opcode = &arc_table[i++];
160 if (ARC_SHORT (opcode->mask) && (insn_len == 2))
162 if (OPCODE_AC (opcode->opcode) != OPCODE_AC (insn[0]))
165 else if (!ARC_SHORT (opcode->mask) && (insn_len == 4))
167 if (OPCODE (opcode->opcode) != OPCODE (insn[0]))
173 if ((insn[0] ^ opcode->opcode) & opcode->mask)
176 if (!(opcode->cpu & isa_mask))
181 /* Possible candidate, check the operands. */
182 for (opidx = opcode->operands; *opidx; opidx++)
185 const struct arc_operand *operand = &arc_operands[*opidx];
187 if (operand->flags & ARC_OPERAND_FAKE)
190 if (operand->extract)
191 value = (*operand->extract) (insn[0], &invalid);
193 value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
195 /* Check for LIMM indicator. If it is there, then make sure
196 we pick the right format. */
197 if (operand->flags & ARC_OPERAND_IR
198 && !(operand->flags & ARC_OPERAND_LIMM))
200 if ((value == 0x3E && insn_len == 4)
201 || (value == 0x1E && insn_len == 2))
208 if (operand->flags & ARC_OPERAND_LIMM
209 && !(operand->flags & ARC_OPERAND_DUPLICATE))
213 /* Check the flags. */
214 for (flgidx = opcode->flags; *flgidx; flgidx++)
216 /* Get a valid flag class. */
217 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
218 const unsigned *flgopridx;
219 int foundA = 0, foundB = 0;
222 /* Check first the extensions. */
223 if (cl_flags->flag_class & F_CLASS_EXTEND)
225 value = (insn[0] & 0x1F);
226 if (arcExtMap_condCodeName (value))
229 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
231 const struct arc_flag_operand *flg_operand =
232 &arc_flag_operands[*flgopridx];
234 value = (insn[0] >> flg_operand->shift)
235 & ((1 << flg_operand->bits) - 1);
236 if (value == flg_operand->code)
241 if (!foundA && foundB)
251 /* The instruction is valid. */
253 } while (opcode->mask);
258 /* Find long instructions matching values in INSN array. */
260 static const struct arc_long_opcode *
261 find_format_long_instructions (unsigned *insn,
262 unsigned int *insn_len,
265 struct disassemble_info *info)
269 bfd_boolean limm_loaded = FALSE;
271 for (i = 0; i < arc_num_long_opcodes; ++i)
275 const struct arc_opcode *opcode;
277 opcode = &arc_long_opcodes[i].base_opcode;
279 if (ARC_SHORT (opcode->mask) && (*insn_len == 2))
281 if (OPCODE_AC (opcode->opcode) != OPCODE_AC (insn[0]))
284 else if (!ARC_SHORT (opcode->mask) && (*insn_len == 4))
286 if (OPCODE (opcode->opcode) != OPCODE (insn[0]))
292 if ((insn[0] ^ opcode->opcode) & opcode->mask)
295 if (!(opcode->cpu & isa_mask))
300 status = (*info->read_memory_func) (memaddr + *insn_len, buffer,
305 limm = ARRANGE_ENDIAN (info, buffer);
309 /* Check the second word using the mask and template. */
310 if ((limm & arc_long_opcodes[i].limm_mask)
311 != arc_long_opcodes[i].limm_template)
316 return &arc_long_opcodes[i];
322 /* Find opcode for INSN, trying various different sources. The instruction
323 length in INSN_LEN will be updated if the instruction requires a LIMM
324 extension, and the additional values loaded into the INSN array (which
327 A pointer to the opcode is placed into OPCODE_RESULT, and ITER is
328 initialised, ready to iterate over the operands of the found opcode.
330 This function returns TRUE in almost all cases, FALSE is reserved to
331 indicate an error (failing to find an opcode is not an error) a
332 returned result of FALSE would indicate that the disassembler can't
335 If no matching opcode is found then the returned result will be TRUE,
336 the value placed into OPCODE_RESULT will be NULL, ITER will be
337 undefined, and INSN_LEN will be unchanged.
339 If a matching opcode is found, then the returned result will be TRUE,
340 the opcode pointer is placed into OPCODE_RESULT, INSN_LEN will be
341 increased by 4 if the instruction requires a LIMM, and the LIMM value
342 will have been loaded into the INSN[1]. Finally, ITER will have been
343 initialised so that calls to OPERAND_ITERATOR_NEXT will iterate over
344 the opcode's operands. */
347 find_format (bfd_vma memaddr, unsigned *insn, unsigned int *insn_len,
348 unsigned isa_mask, struct disassemble_info *info,
349 const struct arc_opcode **opcode_result,
350 struct arc_operand_iterator *iter)
352 const struct arc_opcode *opcode;
353 bfd_boolean needs_limm;
355 /* Find the first match in the opcode table. */
356 opcode = find_format_from_table (arc_opcodes, insn, *insn_len,
357 isa_mask, &needs_limm);
361 const extInstruction_t *einsn;
363 /* No instruction found. Try the extensions. */
364 einsn = arcExtMap_insn (OPCODE (insn[0]), insn[0]);
367 const char *errmsg = NULL;
368 opcode = arcExtMap_genOpcode (einsn, isa_mask, &errmsg);
371 (*info->fprintf_func) (info->stream,
372 "An error occured while "
373 "generating the extension instruction "
375 *opcode_result = NULL;
379 opcode = find_format_from_table (opcode, insn, *insn_len,
380 isa_mask, &needs_limm);
381 assert (opcode != NULL);
385 if (needs_limm && opcode != NULL)
390 status = (*info->read_memory_func) (memaddr + *insn_len, buffer,
398 insn[1] = ARRANGE_ENDIAN (info, buffer);
405 const struct arc_long_opcode *long_opcode;
407 /* No instruction found yet, try the long instructions. */
409 find_format_long_instructions (insn, insn_len, isa_mask,
412 if (long_opcode != NULL)
414 iter->mode = OPERAND_ITERATOR_LONG;
416 iter->state.long_insn.long_opcode = long_opcode;
417 iter->state.long_insn.opidx_base =
418 long_opcode->base_opcode.operands;
419 iter->state.long_insn.opidx_limm =
420 long_opcode->operands;
421 opcode = &long_opcode->base_opcode;
426 iter->mode = OPERAND_ITERATOR_STANDARD;
428 iter->state.standard.opcode = opcode;
429 iter->state.standard.opidx = opcode->operands;
432 *opcode_result = opcode;
437 print_flags (const struct arc_opcode *opcode,
439 struct disassemble_info *info)
441 const unsigned char *flgidx;
444 /* Now extract and print the flags. */
445 for (flgidx = opcode->flags; *flgidx; flgidx++)
447 /* Get a valid flag class. */
448 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
449 const unsigned *flgopridx;
451 /* Check first the extensions. */
452 if (cl_flags->flag_class & F_CLASS_EXTEND)
455 value = (insn[0] & 0x1F);
457 name = arcExtMap_condCodeName (value);
460 (*info->fprintf_func) (info->stream, ".%s", name);
465 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
467 const struct arc_flag_operand *flg_operand =
468 &arc_flag_operands[*flgopridx];
470 if (!flg_operand->favail)
473 value = (insn[0] >> flg_operand->shift)
474 & ((1 << flg_operand->bits) - 1);
475 if (value == flg_operand->code)
477 /* FIXME!: print correctly nt/t flag. */
478 if (!special_flag_p (opcode->name, flg_operand->name))
479 (*info->fprintf_func) (info->stream, ".");
480 else if (info->insn_type == dis_dref)
482 switch (flg_operand->name[0])
496 if (flg_operand->name[0] == 'd'
497 && flg_operand->name[1] == 0)
498 info->branch_delay_insns = 1;
500 /* Check if it is a conditional flag. */
501 if (cl_flags->flag_class & F_CLASS_COND)
503 if (info->insn_type == dis_jsr)
504 info->insn_type = dis_condjsr;
505 else if (info->insn_type == dis_branch)
506 info->insn_type = dis_condbranch;
509 (*info->fprintf_func) (info->stream, "%s", flg_operand->name);
516 get_auxreg (const struct arc_opcode *opcode,
522 const struct arc_aux_reg *auxr = &arc_aux_regs[0];
524 if (opcode->insn_class != AUXREG)
527 name = arcExtMap_auxRegName (value);
531 for (i = 0; i < arc_num_aux_regs; i++, auxr++)
533 if (!(auxr->cpu & isa_mask))
536 if (auxr->subclass != NONE)
539 if (auxr->address == value)
545 /* Calculate the instruction length for an instruction starting with MSB
546 and LSB, the most and least significant byte. The ISA_MASK is used to
547 filter the instructions considered to only those that are part of the
548 current architecture.
550 The instruction lengths are calculated from the ARC_OPCODE table, and
551 cached for later use. */
554 arc_insn_length (bfd_byte msb, bfd_byte lsb, struct disassemble_info *info)
556 bfd_byte major_opcode = msb >> 3;
560 case bfd_mach_arc_arc700:
561 /* The nps400 extension set requires this special casing of the
562 instruction length calculation. Right now this is not causing any
563 problems as none of the known extensions overlap in opcode space,
564 but, if they ever do then we might need to start carrying
565 information around in the elf about which extensions are in use. */
566 if (major_opcode == 0xb)
568 bfd_byte minor_opcode = lsb & 0x1f;
570 if (minor_opcode < 4)
573 case bfd_mach_arc_arc600:
574 return (major_opcode > 0xb) ? 2 : 4;
577 case bfd_mach_arc_arcv2:
578 return (major_opcode > 0x7) ? 2 : 4;
586 /* Extract and return the value of OPERAND from the instruction whose value
587 is held in the array INSN. */
590 extract_operand_value (const struct arc_operand *operand, unsigned *insn)
594 /* Read the limm operand, if required. */
595 if (operand->flags & ARC_OPERAND_LIMM)
596 /* The second part of the instruction value will have been loaded as
597 part of the find_format call made earlier. */
601 if (operand->extract)
602 value = (*operand->extract) (insn[0], (int *) NULL);
605 if (operand->flags & ARC_OPERAND_ALIGNED32)
607 value = (insn[0] >> operand->shift)
608 & ((1 << (operand->bits - 2)) - 1);
613 value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
615 if (operand->flags & ARC_OPERAND_SIGNED)
617 int signbit = 1 << (operand->bits - 1);
618 value = (value ^ signbit) - signbit;
626 /* Find the next operand, and the operands value from ITER. Return TRUE if
627 there is another operand, otherwise return FALSE. If there is an
628 operand returned then the operand is placed into OPERAND, and the value
629 into VALUE. If there is no operand returned then OPERAND and VALUE are
633 operand_iterator_next (struct arc_operand_iterator *iter,
634 const struct arc_operand **operand,
637 if (iter->mode == OPERAND_ITERATOR_STANDARD)
639 if (*iter->state.standard.opidx == 0)
645 *operand = &arc_operands[*iter->state.standard.opidx];
646 *value = extract_operand_value (*operand, iter->insn);
647 iter->state.standard.opidx++;
651 const struct arc_operand *operand_base, *operand_limm;
652 int value_base, value_limm;
654 if (*iter->state.long_insn.opidx_limm == 0)
660 operand_base = &arc_operands[*iter->state.long_insn.opidx_base];
661 operand_limm = &arc_operands[*iter->state.long_insn.opidx_limm];
663 if (operand_base->flags & ARC_OPERAND_LIMM)
665 /* We've reached the end of the operand list. */
670 value_base = value_limm = 0;
671 if (!(operand_limm->flags & ARC_OPERAND_IGNORE))
673 /* This should never happen. If it does then the use of
674 extract_operand_value below will access memory beyond
676 assert ((operand_limm->flags & ARC_OPERAND_LIMM) == 0);
678 *operand = operand_limm;
679 value_limm = extract_operand_value (*operand, &iter->insn[1]);
682 if (!(operand_base->flags & ARC_OPERAND_IGNORE))
684 *operand = operand_base;
685 value_base = extract_operand_value (*operand, iter->insn);
688 /* This is a bit of a fudge. There's no reason why simply ORing
689 together the two values is the right thing to do, however, for all
690 the cases we currently have, it is the right thing, so, for now,
691 I've put off solving the more complex problem. */
692 *value = value_base | value_limm;
694 iter->state.long_insn.opidx_base++;
695 iter->state.long_insn.opidx_limm++;
700 /* Disassemble ARC instructions. */
703 print_insn_arc (bfd_vma memaddr,
704 struct disassemble_info *info)
707 unsigned int lowbyte, highbyte;
709 unsigned int insn_len;
710 unsigned insn[2] = { 0, 0 };
712 const struct arc_opcode *opcode;
713 bfd_boolean need_comma;
714 bfd_boolean open_braket;
716 const struct arc_operand *operand;
718 struct arc_operand_iterator iter;
720 memset (&iter, 0, sizeof (iter));
721 lowbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0);
722 highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1);
726 case bfd_mach_arc_arc700:
727 isa_mask = ARC_OPCODE_ARC700;
730 case bfd_mach_arc_arc600:
731 isa_mask = ARC_OPCODE_ARC600;
734 case bfd_mach_arc_arcv2:
736 isa_mask = ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARCv2EM;
740 /* This variable may be set by the instruction decoder. It suggests
741 the number of bytes objdump should display on a single line. If
742 the instruction decoder sets this, it should always set it to
743 the same value in order to get reasonable looking output. */
745 info->bytes_per_line = 8;
747 /* In the next lines, we set two info variables control the way
748 objdump displays the raw data. For example, if bytes_per_line is
749 8 and bytes_per_chunk is 4, the output will look like this:
750 00: 00000000 00000000
751 with the chunks displayed according to "display_endian". */
754 && !(info->section->flags & SEC_CODE))
756 /* This is not a CODE section. */
757 switch (info->section->size)
762 size = info->section->size;
765 size = (info->section->size & 0x01) ? 1 : 4;
768 info->bytes_per_chunk = 1;
769 info->display_endian = info->endian;
774 info->bytes_per_chunk = 2;
775 info->display_endian = info->endian;
778 /* Read the insn into a host word. */
779 status = (*info->read_memory_func) (memaddr, buffer, size, info);
782 (*info->memory_error_func) (status, memaddr, info);
787 && !(info->section->flags & SEC_CODE))
792 data = bfd_get_bits (buffer, size * 8,
793 info->display_endian == BFD_ENDIAN_BIG);
797 (*info->fprintf_func) (info->stream, ".byte\t0x%02lx", data);
800 (*info->fprintf_func) (info->stream, ".short\t0x%04lx", data);
803 (*info->fprintf_func) (info->stream, ".word\t0x%08lx", data);
811 insn_len = arc_insn_length (buffer[lowbyte], buffer[highbyte], info);
812 pr_debug ("instruction length = %d bytes\n", insn_len);
816 insn[0] = (buffer[lowbyte] << 8) | buffer[highbyte];
820 /* An unknown instruction is treated as being length 4. This is
821 possibly not the best solution, but matches the behaviour that was
822 in place before the table based instruction length look-up was
825 /* This is a long instruction: Read the remaning 2 bytes. */
826 status = (*info->read_memory_func) (memaddr + 2, &buffer[2], 2, info);
829 (*info->memory_error_func) (status, memaddr + 2, info);
832 insn[0] = ARRANGE_ENDIAN (info, buffer);
836 /* Set some defaults for the insn info. */
837 info->insn_info_valid = 1;
838 info->branch_delay_insns = 0;
840 info->insn_type = dis_nonbranch;
844 /* FIXME to be moved in dissasemble_init_for_target. */
845 info->disassembler_needs_relocs = TRUE;
847 /* Find the first match in the opcode table. */
848 if (!find_format (memaddr, insn, &insn_len, isa_mask, info, &opcode, &iter))
854 (*info->fprintf_func) (info->stream, ".long %#04x", insn[0]);
856 (*info->fprintf_func) (info->stream, ".long %#08x", insn[0]);
858 info->insn_type = dis_noninsn;
862 /* Print the mnemonic. */
863 (*info->fprintf_func) (info->stream, "%s", opcode->name);
865 /* Preselect the insn class. */
866 switch (opcode->insn_class)
870 if (!strncmp (opcode->name, "bl", 2)
871 || !strncmp (opcode->name, "jl", 2))
873 if (opcode->subclass == COND)
874 info->insn_type = dis_condjsr;
876 info->insn_type = dis_jsr;
880 if (opcode->subclass == COND)
881 info->insn_type = dis_condbranch;
883 info->insn_type = dis_branch;
887 info->insn_type = dis_dref; /* FIXME! DB indicates mov as memory! */
890 info->insn_type = dis_nonbranch;
894 pr_debug ("%s: 0x%08x\n", opcode->name, opcode->opcode);
896 print_flags (opcode, insn, info);
898 if (opcode->operands[0] != 0)
899 (*info->fprintf_func) (info->stream, "\t");
904 /* Now extract and print the operands. */
906 while (operand_iterator_next (&iter, &operand, &value))
908 if (open_braket && (operand->flags & ARC_OPERAND_BRAKET))
910 (*info->fprintf_func) (info->stream, "]");
915 /* Only take input from real operands. */
916 if ((operand->flags & ARC_OPERAND_FAKE)
917 && !(operand->flags & ARC_OPERAND_BRAKET))
920 if ((operand->flags & ARC_OPERAND_IGNORE)
921 && (operand->flags & ARC_OPERAND_IR)
926 (*info->fprintf_func) (info->stream, ",");
928 if (!open_braket && (operand->flags & ARC_OPERAND_BRAKET))
930 (*info->fprintf_func) (info->stream, "[");
936 /* Print the operand as directed by the flags. */
937 if (operand->flags & ARC_OPERAND_IR)
941 assert (value >=0 && value < 64);
942 rname = arcExtMap_coreRegName (value);
944 rname = regnames[value];
945 (*info->fprintf_func) (info->stream, "%s", rname);
946 if (operand->flags & ARC_OPERAND_TRUNCATE)
948 rname = arcExtMap_coreRegName (value + 1);
950 rname = regnames[value + 1];
951 (*info->fprintf_func) (info->stream, "%s", rname);
954 else if (operand->flags & ARC_OPERAND_LIMM)
956 const char *rname = get_auxreg (opcode, value, isa_mask);
957 if (rname && open_braket)
958 (*info->fprintf_func) (info->stream, "%s", rname);
961 (*info->fprintf_func) (info->stream, "%#x", value);
962 if (info->insn_type == dis_branch
963 || info->insn_type == dis_jsr)
964 info->target = (bfd_vma) value;
967 else if (operand->flags & ARC_OPERAND_PCREL)
970 if (info->flags & INSN_HAS_RELOC)
972 (*info->print_address_func) ((memaddr & ~3) + value, info);
974 info->target = (bfd_vma) (memaddr & ~3) + value;
976 else if (operand->flags & ARC_OPERAND_SIGNED)
978 const char *rname = get_auxreg (opcode, value, isa_mask);
979 if (rname && open_braket)
980 (*info->fprintf_func) (info->stream, "%s", rname);
982 (*info->fprintf_func) (info->stream, "%d", value);
986 if (operand->flags & ARC_OPERAND_TRUNCATE
987 && !(operand->flags & ARC_OPERAND_ALIGNED32)
988 && !(operand->flags & ARC_OPERAND_ALIGNED16)
989 && value > 0 && value <= 14)
990 (*info->fprintf_func) (info->stream, "r13-%s",
991 regnames[13 + value - 1]);
994 const char *rname = get_auxreg (opcode, value, isa_mask);
995 if (rname && open_braket)
996 (*info->fprintf_func) (info->stream, "%s", rname);
998 (*info->fprintf_func) (info->stream, "%#x", value);
1010 arc_get_disassembler (bfd *abfd)
1012 /* Read the extenssion insns and registers, if any. */
1013 build_ARC_extmap (abfd);
1018 return print_insn_arc;
1021 /* Disassemble ARC instructions. Used by debugger. */
1024 arcAnalyzeInstr (bfd_vma memaddr,
1025 struct disassemble_info *info)
1027 struct arcDisState ret;
1028 memset (&ret, 0, sizeof (struct arcDisState));
1030 ret.instructionLen = print_insn_arc (memaddr, info);
1033 ret.words[0] = insn[0];
1034 ret.words[1] = insn[1];
1036 ret.coreRegName = _coreRegName;
1037 ret.auxRegName = _auxRegName;
1038 ret.condCodeName = _condCodeName;
1039 ret.instName = _instName;
1046 eval: (c-set-style "gnu")