1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
2 Copyright (C) 2012-2018 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
21 #ifndef OPCODES_AARCH64_OPC_H
22 #define OPCODES_AARCH64_OPC_H
25 #include "opcode/aarch64.h"
27 /* Instruction fields.
28 Keep synced with fields. */
29 enum aarch64_field_kind
151 /* Field description. */
158 typedef struct aarch64_field aarch64_field;
160 extern const aarch64_field fields[];
162 /* Operand description. */
164 struct aarch64_operand
166 enum aarch64_operand_class op_class;
168 /* Name of the operand code; used mainly for the purpose of internal
174 /* The associated instruction bit-fields; no operand has more than 4
176 enum aarch64_field_kind fields[4];
178 /* Brief description */
182 typedef struct aarch64_operand aarch64_operand;
184 extern const aarch64_operand aarch64_operands[];
188 #define OPD_F_HAS_INSERTER 0x00000001
189 #define OPD_F_HAS_EXTRACTOR 0x00000002
190 #define OPD_F_SEXT 0x00000004 /* Require sign-extension. */
191 #define OPD_F_SHIFT_BY_2 0x00000008 /* Need to left shift the field
192 value by 2 to get the value
193 of an immediate operand. */
194 #define OPD_F_MAYBE_SP 0x00000010 /* May potentially be SP. */
195 #define OPD_F_OD_MASK 0x000000e0 /* Operand-dependent data. */
196 #define OPD_F_OD_LSB 5
197 #define OPD_F_NO_ZR 0x00000100 /* ZR index not allowed. */
199 /* Register flags. */
202 #define F_DEPRECATED (1 << 0) /* Deprecated system register. */
205 #define F_ARCHEXT (1 << 1) /* Architecture dependent system register. */
208 #define F_HASXT (1 << 2) /* System instruction register <Xt>
212 #define F_REG_READ (1 << 3) /* Register can only be used to read values
216 #define F_REG_WRITE (1 << 4) /* Register can only be written to but not
219 static inline bfd_boolean
220 operand_has_inserter (const aarch64_operand *operand)
222 return (operand->flags & OPD_F_HAS_INSERTER) ? TRUE : FALSE;
225 static inline bfd_boolean
226 operand_has_extractor (const aarch64_operand *operand)
228 return (operand->flags & OPD_F_HAS_EXTRACTOR) ? TRUE : FALSE;
231 static inline bfd_boolean
232 operand_need_sign_extension (const aarch64_operand *operand)
234 return (operand->flags & OPD_F_SEXT) ? TRUE : FALSE;
237 static inline bfd_boolean
238 operand_need_shift_by_two (const aarch64_operand *operand)
240 return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE;
243 static inline bfd_boolean
244 operand_maybe_stack_pointer (const aarch64_operand *operand)
246 return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE;
249 /* Return the value of the operand-specific data field (OPD_F_OD_MASK). */
250 static inline unsigned int
251 get_operand_specific_data (const aarch64_operand *operand)
253 return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
256 /* Return the width of field number N of operand *OPERAND. */
257 static inline unsigned
258 get_operand_field_width (const aarch64_operand *operand, unsigned n)
260 assert (operand->fields[n] != FLD_NIL);
261 return fields[operand->fields[n]].width;
264 /* Return the total width of the operand *OPERAND. */
265 static inline unsigned
266 get_operand_fields_width (const aarch64_operand *operand)
270 while (operand->fields[i] != FLD_NIL)
271 width += fields[operand->fields[i++]].width;
272 assert (width > 0 && width < 32);
276 static inline const aarch64_operand *
277 get_operand_from_code (enum aarch64_opnd code)
279 return aarch64_operands + code;
282 /* Operand qualifier and operand constraint checking. */
284 int aarch64_match_operands_constraint (aarch64_inst *,
285 aarch64_operand_error *);
287 /* Operand qualifier related functions. */
288 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t);
289 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t);
290 aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t);
291 int aarch64_find_best_match (const aarch64_inst *,
292 const aarch64_opnd_qualifier_seq_t *,
293 int, aarch64_opnd_qualifier_t *);
296 reset_operand_qualifier (aarch64_inst *inst, int idx)
298 assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode));
299 inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
302 /* Inline functions operating on instruction bit-field(s). */
304 /* Generate a mask that has WIDTH number of consecutive 1s. */
306 static inline aarch64_insn
309 return ((aarch64_insn) 1 << width) - 1;
312 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0. */
314 gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret)
316 const aarch64_field *field = &fields[kind];
317 if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width)
319 ret->lsb = field->lsb + lsb_rel;
324 /* Insert VALUE into FIELD of CODE. MASK can be zero or the base mask
328 insert_field_2 (const aarch64_field *field, aarch64_insn *code,
329 aarch64_insn value, aarch64_insn mask)
331 assert (field->width < 32 && field->width >= 1 && field->lsb >= 0
332 && field->lsb + field->width <= 32);
333 value &= gen_mask (field->width);
334 value <<= field->lsb;
335 /* In some opcodes, field can be part of the base opcode, e.g. the size
336 field in FADD. The following helps avoid corrupt the base opcode. */
341 /* Extract FIELD of CODE and return the value. MASK can be zero or the base
342 mask of the opcode. */
344 static inline aarch64_insn
345 extract_field_2 (const aarch64_field *field, aarch64_insn code,
349 /* Clear any bit that is a part of the base opcode. */
351 value = (code >> field->lsb) & gen_mask (field->width);
355 /* Insert VALUE into field KIND of CODE. MASK can be zero or the base mask
359 insert_field (enum aarch64_field_kind kind, aarch64_insn *code,
360 aarch64_insn value, aarch64_insn mask)
362 insert_field_2 (&fields[kind], code, value, mask);
365 /* Extract field KIND of CODE and return the value. MASK can be zero or the
366 base mask of the opcode. */
368 static inline aarch64_insn
369 extract_field (enum aarch64_field_kind kind, aarch64_insn code,
372 return extract_field_2 (&fields[kind], code, mask);
376 extract_fields (aarch64_insn code, aarch64_insn mask, ...);
378 /* Inline functions selecting operand to do the encoding/decoding for a
379 certain instruction bit-field. */
381 /* Select the operand to do the encoding/decoding of the 'sf' field.
382 The heuristic-based rule is that the result operand is respected more. */
385 select_operand_for_sf_field_coding (const aarch64_opcode *opcode)
388 if (aarch64_get_operand_class (opcode->operands[0])
389 == AARCH64_OPND_CLASS_INT_REG)
392 else if (aarch64_get_operand_class (opcode->operands[1])
393 == AARCH64_OPND_CLASS_INT_REG)
394 /* e.g. float2fix. */
397 { assert (0); abort (); }
401 /* Select the operand to do the encoding/decoding of the 'type' field in
402 the floating-point instructions.
403 The heuristic-based rule is that the source operand is respected more. */
406 select_operand_for_fptype_field_coding (const aarch64_opcode *opcode)
409 if (aarch64_get_operand_class (opcode->operands[1])
410 == AARCH64_OPND_CLASS_FP_REG)
413 else if (aarch64_get_operand_class (opcode->operands[0])
414 == AARCH64_OPND_CLASS_FP_REG)
415 /* e.g. float2fix. */
418 { assert (0); abort (); }
422 /* Select the operand to do the encoding/decoding of the 'size' field in
423 the AdvSIMD scalar instructions.
424 The heuristic-based rule is that the destination operand is respected
428 select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode)
430 int src_size = 0, dst_size = 0;
431 if (aarch64_get_operand_class (opcode->operands[0])
432 == AARCH64_OPND_CLASS_SISD_REG)
433 dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]);
434 if (aarch64_get_operand_class (opcode->operands[1])
435 == AARCH64_OPND_CLASS_SISD_REG)
436 src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
437 if (src_size == dst_size && src_size == 0)
438 { assert (0); abort (); }
439 /* When the result is not a sisd register or it is a long operantion. */
440 if (dst_size == 0 || dst_size == src_size << 1)
446 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
447 the AdvSIMD instructions. */
449 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *);
453 aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind);
454 enum aarch64_modifier_kind
455 aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean);
458 bfd_boolean aarch64_wide_constant_p (int64_t, int, unsigned int *);
459 bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
460 int aarch64_shrink_expanded_imm8 (uint64_t);
462 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST]. */
464 copy_operand_info (aarch64_inst *inst, int dst, int src)
466 assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM
467 && src < AARCH64_MAX_OPND_NUM);
468 memcpy (&inst->operands[dst], &inst->operands[src],
469 sizeof (aarch64_opnd_info));
470 inst->operands[dst].idx = dst;
473 /* A primitive log caculator. */
475 static inline unsigned int
476 get_logsz (unsigned int size)
478 const unsigned char ls[16] =
479 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
485 assert (ls[size - 1] != (unsigned char)-1);
489 #endif /* OPCODES_AARCH64_OPC_H */