1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
2 Copyright (C) 2012-2019 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
21 #ifndef OPCODES_AARCH64_OPC_H
22 #define OPCODES_AARCH64_OPC_H
25 #include "opcode/aarch64.h"
27 /* Instruction fields.
28 Keep synced with fields. */
29 enum aarch64_field_kind
153 /* Field description. */
160 typedef struct aarch64_field aarch64_field;
162 extern const aarch64_field fields[];
164 /* Operand description. */
166 struct aarch64_operand
168 enum aarch64_operand_class op_class;
170 /* Name of the operand code; used mainly for the purpose of internal
176 /* The associated instruction bit-fields; no operand has more than 4
178 enum aarch64_field_kind fields[4];
180 /* Brief description */
184 typedef struct aarch64_operand aarch64_operand;
186 extern const aarch64_operand aarch64_operands[];
189 verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
190 bfd_boolean, aarch64_operand_error *, aarch64_instr_sequence*);
194 #define OPD_F_HAS_INSERTER 0x00000001
195 #define OPD_F_HAS_EXTRACTOR 0x00000002
196 #define OPD_F_SEXT 0x00000004 /* Require sign-extension. */
197 #define OPD_F_SHIFT_BY_2 0x00000008 /* Need to left shift the field
198 value by 2 to get the value
199 of an immediate operand. */
200 #define OPD_F_MAYBE_SP 0x00000010 /* May potentially be SP. */
201 #define OPD_F_OD_MASK 0x000000e0 /* Operand-dependent data. */
202 #define OPD_F_OD_LSB 5
203 #define OPD_F_NO_ZR 0x00000100 /* ZR index not allowed. */
204 #define OPD_F_SHIFT_BY_4 0x00000200 /* Need to left shift the field
205 value by 4 to get the value
206 of an immediate operand. */
209 /* Register flags. */
212 #define F_DEPRECATED (1 << 0) /* Deprecated system register. */
215 #define F_ARCHEXT (1 << 1) /* Architecture dependent system register. */
218 #define F_HASXT (1 << 2) /* System instruction register <Xt>
222 #define F_REG_READ (1 << 3) /* Register can only be used to read values
226 #define F_REG_WRITE (1 << 4) /* Register can only be written to but not
229 /* HINT operand flags. */
230 #define HINT_OPD_F_NOPRINT (1 << 0) /* Should not be printed. */
232 /* Encode 7-bit HINT #imm in the lower 8 bits. Use higher bits for flags. */
233 #define HINT_ENCODE(flag, val) ((flag << 8) | val)
234 #define HINT_FLAG(val) (val >> 8)
235 #define HINT_VAL(val) (val & 0xff)
237 static inline bfd_boolean
238 operand_has_inserter (const aarch64_operand *operand)
240 return (operand->flags & OPD_F_HAS_INSERTER) ? TRUE : FALSE;
243 static inline bfd_boolean
244 operand_has_extractor (const aarch64_operand *operand)
246 return (operand->flags & OPD_F_HAS_EXTRACTOR) ? TRUE : FALSE;
249 static inline bfd_boolean
250 operand_need_sign_extension (const aarch64_operand *operand)
252 return (operand->flags & OPD_F_SEXT) ? TRUE : FALSE;
255 static inline bfd_boolean
256 operand_need_shift_by_two (const aarch64_operand *operand)
258 return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE;
261 static inline bfd_boolean
262 operand_need_shift_by_four (const aarch64_operand *operand)
264 return (operand->flags & OPD_F_SHIFT_BY_4) ? TRUE : FALSE;
267 static inline bfd_boolean
268 operand_maybe_stack_pointer (const aarch64_operand *operand)
270 return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE;
273 /* Return the value of the operand-specific data field (OPD_F_OD_MASK). */
274 static inline unsigned int
275 get_operand_specific_data (const aarch64_operand *operand)
277 return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
280 /* Return the width of field number N of operand *OPERAND. */
281 static inline unsigned
282 get_operand_field_width (const aarch64_operand *operand, unsigned n)
284 assert (operand->fields[n] != FLD_NIL);
285 return fields[operand->fields[n]].width;
288 /* Return the total width of the operand *OPERAND. */
289 static inline unsigned
290 get_operand_fields_width (const aarch64_operand *operand)
294 while (operand->fields[i] != FLD_NIL)
295 width += fields[operand->fields[i++]].width;
296 assert (width > 0 && width < 32);
300 static inline const aarch64_operand *
301 get_operand_from_code (enum aarch64_opnd code)
303 return aarch64_operands + code;
306 /* Operand qualifier and operand constraint checking. */
308 int aarch64_match_operands_constraint (aarch64_inst *,
309 aarch64_operand_error *);
311 /* Operand qualifier related functions. */
312 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t);
313 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t);
314 aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t);
315 int aarch64_find_best_match (const aarch64_inst *,
316 const aarch64_opnd_qualifier_seq_t *,
317 int, aarch64_opnd_qualifier_t *);
320 reset_operand_qualifier (aarch64_inst *inst, int idx)
322 assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode));
323 inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
326 /* Inline functions operating on instruction bit-field(s). */
328 /* Generate a mask that has WIDTH number of consecutive 1s. */
330 static inline aarch64_insn
333 return ((aarch64_insn) 1 << width) - 1;
336 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0. */
338 gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret)
340 const aarch64_field *field = &fields[kind];
341 if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width)
343 ret->lsb = field->lsb + lsb_rel;
348 /* Insert VALUE into FIELD of CODE. MASK can be zero or the base mask
352 insert_field_2 (const aarch64_field *field, aarch64_insn *code,
353 aarch64_insn value, aarch64_insn mask)
355 assert (field->width < 32 && field->width >= 1 && field->lsb >= 0
356 && field->lsb + field->width <= 32);
357 value &= gen_mask (field->width);
358 value <<= field->lsb;
359 /* In some opcodes, field can be part of the base opcode, e.g. the size
360 field in FADD. The following helps avoid corrupt the base opcode. */
365 /* Extract FIELD of CODE and return the value. MASK can be zero or the base
366 mask of the opcode. */
368 static inline aarch64_insn
369 extract_field_2 (const aarch64_field *field, aarch64_insn code,
373 /* Clear any bit that is a part of the base opcode. */
375 value = (code >> field->lsb) & gen_mask (field->width);
379 /* Insert VALUE into field KIND of CODE. MASK can be zero or the base mask
383 insert_field (enum aarch64_field_kind kind, aarch64_insn *code,
384 aarch64_insn value, aarch64_insn mask)
386 insert_field_2 (&fields[kind], code, value, mask);
389 /* Extract field KIND of CODE and return the value. MASK can be zero or the
390 base mask of the opcode. */
392 static inline aarch64_insn
393 extract_field (enum aarch64_field_kind kind, aarch64_insn code,
396 return extract_field_2 (&fields[kind], code, mask);
400 extract_fields (aarch64_insn code, aarch64_insn mask, ...);
402 /* Inline functions selecting operand to do the encoding/decoding for a
403 certain instruction bit-field. */
405 /* Select the operand to do the encoding/decoding of the 'sf' field.
406 The heuristic-based rule is that the result operand is respected more. */
409 select_operand_for_sf_field_coding (const aarch64_opcode *opcode)
412 if (aarch64_get_operand_class (opcode->operands[0])
413 == AARCH64_OPND_CLASS_INT_REG)
416 else if (aarch64_get_operand_class (opcode->operands[1])
417 == AARCH64_OPND_CLASS_INT_REG)
418 /* e.g. float2fix. */
421 { assert (0); abort (); }
425 /* Select the operand to do the encoding/decoding of the 'type' field in
426 the floating-point instructions.
427 The heuristic-based rule is that the source operand is respected more. */
430 select_operand_for_fptype_field_coding (const aarch64_opcode *opcode)
433 if (aarch64_get_operand_class (opcode->operands[1])
434 == AARCH64_OPND_CLASS_FP_REG)
437 else if (aarch64_get_operand_class (opcode->operands[0])
438 == AARCH64_OPND_CLASS_FP_REG)
439 /* e.g. float2fix. */
442 { assert (0); abort (); }
446 /* Select the operand to do the encoding/decoding of the 'size' field in
447 the AdvSIMD scalar instructions.
448 The heuristic-based rule is that the destination operand is respected
452 select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode)
454 int src_size = 0, dst_size = 0;
455 if (aarch64_get_operand_class (opcode->operands[0])
456 == AARCH64_OPND_CLASS_SISD_REG)
457 dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]);
458 if (aarch64_get_operand_class (opcode->operands[1])
459 == AARCH64_OPND_CLASS_SISD_REG)
460 src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
461 if (src_size == dst_size && src_size == 0)
462 { assert (0); abort (); }
463 /* When the result is not a sisd register or it is a long operantion. */
464 if (dst_size == 0 || dst_size == src_size << 1)
470 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
471 the AdvSIMD instructions. */
473 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *);
477 aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind);
478 enum aarch64_modifier_kind
479 aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean);
482 bfd_boolean aarch64_wide_constant_p (int64_t, int, unsigned int *);
483 bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
484 int aarch64_shrink_expanded_imm8 (uint64_t);
486 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST]. */
488 copy_operand_info (aarch64_inst *inst, int dst, int src)
490 assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM
491 && src < AARCH64_MAX_OPND_NUM);
492 memcpy (&inst->operands[dst], &inst->operands[src],
493 sizeof (aarch64_opnd_info));
494 inst->operands[dst].idx = dst;
497 /* A primitive log caculator. */
499 static inline unsigned int
500 get_logsz (unsigned int size)
502 const unsigned char ls[16] =
503 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
509 assert (ls[size - 1] != (unsigned char)-1);
513 #endif /* OPCODES_AARCH64_OPC_H */