1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
2 Copyright (C) 2012-2019 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
21 #ifndef OPCODES_AARCH64_OPC_H
22 #define OPCODES_AARCH64_OPC_H
25 #include "opcode/aarch64.h"
27 /* Instruction fields.
28 Keep synced with fields. */
29 enum aarch64_field_kind
159 /* Field description. */
166 typedef struct aarch64_field aarch64_field;
168 extern const aarch64_field fields[];
170 /* Operand description. */
172 struct aarch64_operand
174 enum aarch64_operand_class op_class;
176 /* Name of the operand code; used mainly for the purpose of internal
182 /* The associated instruction bit-fields; no operand has more than 4
184 enum aarch64_field_kind fields[4];
186 /* Brief description */
190 typedef struct aarch64_operand aarch64_operand;
192 extern const aarch64_operand aarch64_operands[];
195 verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
196 bfd_boolean, aarch64_operand_error *, aarch64_instr_sequence*);
200 #define OPD_F_HAS_INSERTER 0x00000001
201 #define OPD_F_HAS_EXTRACTOR 0x00000002
202 #define OPD_F_SEXT 0x00000004 /* Require sign-extension. */
203 #define OPD_F_SHIFT_BY_2 0x00000008 /* Need to left shift the field
204 value by 2 to get the value
205 of an immediate operand. */
206 #define OPD_F_MAYBE_SP 0x00000010 /* May potentially be SP. */
207 #define OPD_F_OD_MASK 0x000000e0 /* Operand-dependent data. */
208 #define OPD_F_OD_LSB 5
209 #define OPD_F_NO_ZR 0x00000100 /* ZR index not allowed. */
210 #define OPD_F_SHIFT_BY_4 0x00000200 /* Need to left shift the field
211 value by 4 to get the value
212 of an immediate operand. */
215 /* Register flags. */
218 #define F_DEPRECATED (1 << 0) /* Deprecated system register. */
221 #define F_ARCHEXT (1 << 1) /* Architecture dependent system register. */
224 #define F_HASXT (1 << 2) /* System instruction register <Xt>
228 #define F_REG_READ (1 << 3) /* Register can only be used to read values
232 #define F_REG_WRITE (1 << 4) /* Register can only be written to but not
235 /* HINT operand flags. */
236 #define HINT_OPD_F_NOPRINT (1 << 0) /* Should not be printed. */
238 /* Encode 7-bit HINT #imm in the lower 8 bits. Use higher bits for flags. */
239 #define HINT_ENCODE(flag, val) ((flag << 8) | val)
240 #define HINT_FLAG(val) (val >> 8)
241 #define HINT_VAL(val) (val & 0xff)
243 static inline bfd_boolean
244 operand_has_inserter (const aarch64_operand *operand)
246 return (operand->flags & OPD_F_HAS_INSERTER) ? TRUE : FALSE;
249 static inline bfd_boolean
250 operand_has_extractor (const aarch64_operand *operand)
252 return (operand->flags & OPD_F_HAS_EXTRACTOR) ? TRUE : FALSE;
255 static inline bfd_boolean
256 operand_need_sign_extension (const aarch64_operand *operand)
258 return (operand->flags & OPD_F_SEXT) ? TRUE : FALSE;
261 static inline bfd_boolean
262 operand_need_shift_by_two (const aarch64_operand *operand)
264 return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE;
267 static inline bfd_boolean
268 operand_need_shift_by_four (const aarch64_operand *operand)
270 return (operand->flags & OPD_F_SHIFT_BY_4) ? TRUE : FALSE;
273 static inline bfd_boolean
274 operand_maybe_stack_pointer (const aarch64_operand *operand)
276 return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE;
279 /* Return the value of the operand-specific data field (OPD_F_OD_MASK). */
280 static inline unsigned int
281 get_operand_specific_data (const aarch64_operand *operand)
283 return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
286 /* Return the width of field number N of operand *OPERAND. */
287 static inline unsigned
288 get_operand_field_width (const aarch64_operand *operand, unsigned n)
290 assert (operand->fields[n] != FLD_NIL);
291 return fields[operand->fields[n]].width;
294 /* Return the total width of the operand *OPERAND. */
295 static inline unsigned
296 get_operand_fields_width (const aarch64_operand *operand)
300 while (operand->fields[i] != FLD_NIL)
301 width += fields[operand->fields[i++]].width;
302 assert (width > 0 && width < 32);
306 static inline const aarch64_operand *
307 get_operand_from_code (enum aarch64_opnd code)
309 return aarch64_operands + code;
312 /* Operand qualifier and operand constraint checking. */
314 int aarch64_match_operands_constraint (aarch64_inst *,
315 aarch64_operand_error *);
317 /* Operand qualifier related functions. */
318 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t);
319 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t);
320 aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t);
321 int aarch64_find_best_match (const aarch64_inst *,
322 const aarch64_opnd_qualifier_seq_t *,
323 int, aarch64_opnd_qualifier_t *);
326 reset_operand_qualifier (aarch64_inst *inst, int idx)
328 assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode));
329 inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
332 /* Inline functions operating on instruction bit-field(s). */
334 /* Generate a mask that has WIDTH number of consecutive 1s. */
336 static inline aarch64_insn
339 return ((aarch64_insn) 1 << width) - 1;
342 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0. */
344 gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret)
346 const aarch64_field *field = &fields[kind];
347 if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width)
349 ret->lsb = field->lsb + lsb_rel;
354 /* Insert VALUE into FIELD of CODE. MASK can be zero or the base mask
358 insert_field_2 (const aarch64_field *field, aarch64_insn *code,
359 aarch64_insn value, aarch64_insn mask)
361 assert (field->width < 32 && field->width >= 1 && field->lsb >= 0
362 && field->lsb + field->width <= 32);
363 value &= gen_mask (field->width);
364 value <<= field->lsb;
365 /* In some opcodes, field can be part of the base opcode, e.g. the size
366 field in FADD. The following helps avoid corrupt the base opcode. */
371 /* Extract FIELD of CODE and return the value. MASK can be zero or the base
372 mask of the opcode. */
374 static inline aarch64_insn
375 extract_field_2 (const aarch64_field *field, aarch64_insn code,
379 /* Clear any bit that is a part of the base opcode. */
381 value = (code >> field->lsb) & gen_mask (field->width);
385 /* Insert VALUE into field KIND of CODE. MASK can be zero or the base mask
389 insert_field (enum aarch64_field_kind kind, aarch64_insn *code,
390 aarch64_insn value, aarch64_insn mask)
392 insert_field_2 (&fields[kind], code, value, mask);
395 /* Extract field KIND of CODE and return the value. MASK can be zero or the
396 base mask of the opcode. */
398 static inline aarch64_insn
399 extract_field (enum aarch64_field_kind kind, aarch64_insn code,
402 return extract_field_2 (&fields[kind], code, mask);
406 extract_fields (aarch64_insn code, aarch64_insn mask, ...);
408 /* Inline functions selecting operand to do the encoding/decoding for a
409 certain instruction bit-field. */
411 /* Select the operand to do the encoding/decoding of the 'sf' field.
412 The heuristic-based rule is that the result operand is respected more. */
415 select_operand_for_sf_field_coding (const aarch64_opcode *opcode)
418 if (aarch64_get_operand_class (opcode->operands[0])
419 == AARCH64_OPND_CLASS_INT_REG)
422 else if (aarch64_get_operand_class (opcode->operands[1])
423 == AARCH64_OPND_CLASS_INT_REG)
424 /* e.g. float2fix. */
427 { assert (0); abort (); }
431 /* Select the operand to do the encoding/decoding of the 'type' field in
432 the floating-point instructions.
433 The heuristic-based rule is that the source operand is respected more. */
436 select_operand_for_fptype_field_coding (const aarch64_opcode *opcode)
439 if (aarch64_get_operand_class (opcode->operands[1])
440 == AARCH64_OPND_CLASS_FP_REG)
443 else if (aarch64_get_operand_class (opcode->operands[0])
444 == AARCH64_OPND_CLASS_FP_REG)
445 /* e.g. float2fix. */
448 { assert (0); abort (); }
452 /* Select the operand to do the encoding/decoding of the 'size' field in
453 the AdvSIMD scalar instructions.
454 The heuristic-based rule is that the destination operand is respected
458 select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode)
460 int src_size = 0, dst_size = 0;
461 if (aarch64_get_operand_class (opcode->operands[0])
462 == AARCH64_OPND_CLASS_SISD_REG)
463 dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]);
464 if (aarch64_get_operand_class (opcode->operands[1])
465 == AARCH64_OPND_CLASS_SISD_REG)
466 src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
467 if (src_size == dst_size && src_size == 0)
468 { assert (0); abort (); }
469 /* When the result is not a sisd register or it is a long operantion. */
470 if (dst_size == 0 || dst_size == src_size << 1)
476 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
477 the AdvSIMD instructions. */
479 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *);
483 aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind);
484 enum aarch64_modifier_kind
485 aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean);
488 bfd_boolean aarch64_wide_constant_p (int64_t, int, unsigned int *);
489 bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
490 int aarch64_shrink_expanded_imm8 (uint64_t);
492 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST]. */
494 copy_operand_info (aarch64_inst *inst, int dst, int src)
496 assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM
497 && src < AARCH64_MAX_OPND_NUM);
498 memcpy (&inst->operands[dst], &inst->operands[src],
499 sizeof (aarch64_opnd_info));
500 inst->operands[dst].idx = dst;
503 /* A primitive log caculator. */
505 static inline unsigned int
506 get_logsz (unsigned int size)
508 const unsigned char ls[16] =
509 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
515 assert (ls[size - 1] != (unsigned char)-1);
519 #endif /* OPCODES_AARCH64_OPC_H */