1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
2 Copyright (C) 2012-2016 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
21 #ifndef OPCODES_AARCH64_OPC_H
22 #define OPCODES_AARCH64_OPC_H
25 #include "opcode/aarch64.h"
27 /* Instruction fields.
28 Keep synced with fields. */
29 enum aarch64_field_kind
96 /* Field description. */
103 typedef struct aarch64_field aarch64_field;
105 extern const aarch64_field fields[];
107 /* Operand description. */
109 struct aarch64_operand
111 enum aarch64_operand_class op_class;
113 /* Name of the operand code; used mainly for the purpose of internal
119 /* The associated instruction bit-fields; no operand has more than 4
121 enum aarch64_field_kind fields[4];
123 /* Brief description */
127 typedef struct aarch64_operand aarch64_operand;
129 extern const aarch64_operand aarch64_operands[];
133 #define OPD_F_HAS_INSERTER 0x00000001
134 #define OPD_F_HAS_EXTRACTOR 0x00000002
135 #define OPD_F_SEXT 0x00000004 /* Require sign-extension. */
136 #define OPD_F_SHIFT_BY_2 0x00000008 /* Need to left shift the field
137 value by 2 to get the value
138 of an immediate operand. */
139 #define OPD_F_MAYBE_SP 0x00000010 /* May potentially be SP. */
141 static inline bfd_boolean
142 operand_has_inserter (const aarch64_operand *operand)
144 return (operand->flags & OPD_F_HAS_INSERTER) ? TRUE : FALSE;
147 static inline bfd_boolean
148 operand_has_extractor (const aarch64_operand *operand)
150 return (operand->flags & OPD_F_HAS_EXTRACTOR) ? TRUE : FALSE;
153 static inline bfd_boolean
154 operand_need_sign_extension (const aarch64_operand *operand)
156 return (operand->flags & OPD_F_SEXT) ? TRUE : FALSE;
159 static inline bfd_boolean
160 operand_need_shift_by_two (const aarch64_operand *operand)
162 return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE;
165 static inline bfd_boolean
166 operand_maybe_stack_pointer (const aarch64_operand *operand)
168 return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE;
171 /* Return the total width of the operand *OPERAND. */
172 static inline unsigned
173 get_operand_fields_width (const aarch64_operand *operand)
177 while (operand->fields[i] != FLD_NIL)
178 width += fields[operand->fields[i++]].width;
179 assert (width > 0 && width < 32);
183 static inline const aarch64_operand *
184 get_operand_from_code (enum aarch64_opnd code)
186 return aarch64_operands + code;
189 /* Operand qualifier and operand constraint checking. */
191 int aarch64_match_operands_constraint (aarch64_inst *,
192 aarch64_operand_error *);
194 /* Operand qualifier related functions. */
195 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t);
196 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t);
197 aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t);
198 int aarch64_find_best_match (const aarch64_inst *,
199 const aarch64_opnd_qualifier_seq_t *,
200 int, aarch64_opnd_qualifier_t *);
203 reset_operand_qualifier (aarch64_inst *inst, int idx)
205 assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode));
206 inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
209 /* Inline functions operating on instruction bit-field(s). */
211 /* Generate a mask that has WIDTH number of consecutive 1s. */
213 static inline aarch64_insn
216 return ((aarch64_insn) 1 << width) - 1;
219 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0. */
221 gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret)
223 const aarch64_field *field = &fields[kind];
224 if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width)
226 ret->lsb = field->lsb + lsb_rel;
231 /* Insert VALUE into FIELD of CODE. MASK can be zero or the base mask
235 insert_field_2 (const aarch64_field *field, aarch64_insn *code,
236 aarch64_insn value, aarch64_insn mask)
238 assert (field->width < 32 && field->width >= 1 && field->lsb >= 0
239 && field->lsb + field->width <= 32);
240 value &= gen_mask (field->width);
241 value <<= field->lsb;
242 /* In some opcodes, field can be part of the base opcode, e.g. the size
243 field in FADD. The following helps avoid corrupt the base opcode. */
248 /* Extract FIELD of CODE and return the value. MASK can be zero or the base
249 mask of the opcode. */
251 static inline aarch64_insn
252 extract_field_2 (const aarch64_field *field, aarch64_insn code,
256 /* Clear any bit that is a part of the base opcode. */
258 value = (code >> field->lsb) & gen_mask (field->width);
262 /* Insert VALUE into field KIND of CODE. MASK can be zero or the base mask
266 insert_field (enum aarch64_field_kind kind, aarch64_insn *code,
267 aarch64_insn value, aarch64_insn mask)
269 insert_field_2 (&fields[kind], code, value, mask);
272 /* Extract field KIND of CODE and return the value. MASK can be zero or the
273 base mask of the opcode. */
275 static inline aarch64_insn
276 extract_field (enum aarch64_field_kind kind, aarch64_insn code,
279 return extract_field_2 (&fields[kind], code, mask);
282 /* Inline functions selecting operand to do the encoding/decoding for a
283 certain instruction bit-field. */
285 /* Select the operand to do the encoding/decoding of the 'sf' field.
286 The heuristic-based rule is that the result operand is respected more. */
289 select_operand_for_sf_field_coding (const aarch64_opcode *opcode)
292 if (aarch64_get_operand_class (opcode->operands[0])
293 == AARCH64_OPND_CLASS_INT_REG)
296 else if (aarch64_get_operand_class (opcode->operands[1])
297 == AARCH64_OPND_CLASS_INT_REG)
298 /* e.g. float2fix. */
301 { assert (0); abort (); }
305 /* Select the operand to do the encoding/decoding of the 'type' field in
306 the floating-point instructions.
307 The heuristic-based rule is that the source operand is respected more. */
310 select_operand_for_fptype_field_coding (const aarch64_opcode *opcode)
313 if (aarch64_get_operand_class (opcode->operands[1])
314 == AARCH64_OPND_CLASS_FP_REG)
317 else if (aarch64_get_operand_class (opcode->operands[0])
318 == AARCH64_OPND_CLASS_FP_REG)
319 /* e.g. float2fix. */
322 { assert (0); abort (); }
326 /* Select the operand to do the encoding/decoding of the 'size' field in
327 the AdvSIMD scalar instructions.
328 The heuristic-based rule is that the destination operand is respected
332 select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode)
334 int src_size = 0, dst_size = 0;
335 if (aarch64_get_operand_class (opcode->operands[0])
336 == AARCH64_OPND_CLASS_SISD_REG)
337 dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]);
338 if (aarch64_get_operand_class (opcode->operands[1])
339 == AARCH64_OPND_CLASS_SISD_REG)
340 src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
341 if (src_size == dst_size && src_size == 0)
342 { assert (0); abort (); }
343 /* When the result is not a sisd register or it is a long operantion. */
344 if (dst_size == 0 || dst_size == src_size << 1)
350 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
351 the AdvSIMD instructions. */
353 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *);
357 aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind);
358 enum aarch64_modifier_kind
359 aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean);
362 bfd_boolean aarch64_wide_constant_p (int64_t, int, unsigned int *);
363 bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
364 int aarch64_shrink_expanded_imm8 (uint64_t);
366 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST]. */
368 copy_operand_info (aarch64_inst *inst, int dst, int src)
370 assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM
371 && src < AARCH64_MAX_OPND_NUM);
372 memcpy (&inst->operands[dst], &inst->operands[src],
373 sizeof (aarch64_opnd_info));
374 inst->operands[dst].idx = dst;
377 /* A primitive log caculator. */
379 static inline unsigned int
380 get_logsz (unsigned int size)
382 const unsigned char ls[16] =
383 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
389 assert (ls[size - 1] != (unsigned char)-1);
393 #endif /* OPCODES_AARCH64_OPC_H */