1 /* aarch64-dis.c -- AArch64 disassembler.
2 Copyright (C) 2009-2016 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
22 #include "bfd_stdint.h"
24 #include "libiberty.h"
26 #include "aarch64-dis.h"
36 /* Cached mapping symbol state. */
43 static enum map_type last_type;
44 static int last_mapping_sym = -1;
45 static bfd_vma last_mapping_addr = 0;
48 static int no_aliases = 0; /* If set disassemble as most general inst. */
52 set_default_aarch64_dis_options (struct disassemble_info *info ATTRIBUTE_UNUSED)
57 parse_aarch64_dis_option (const char *option, unsigned int len ATTRIBUTE_UNUSED)
59 /* Try to match options that are simple flags */
60 if (CONST_STRNEQ (option, "no-aliases"))
66 if (CONST_STRNEQ (option, "aliases"))
73 if (CONST_STRNEQ (option, "debug_dump"))
78 #endif /* DEBUG_AARCH64 */
81 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
85 parse_aarch64_dis_options (const char *options)
87 const char *option_end;
92 while (*options != '\0')
94 /* Skip empty options. */
101 /* We know that *options is neither NUL or a comma. */
102 option_end = options + 1;
103 while (*option_end != ',' && *option_end != '\0')
106 parse_aarch64_dis_option (options, option_end - options);
108 /* Go on to the next one. If option_end points to a comma, it
109 will be skipped above. */
110 options = option_end;
114 /* Functions doing the instruction disassembling. */
116 /* The unnamed arguments consist of the number of fields and information about
117 these fields where the VALUE will be extracted from CODE and returned.
118 MASK can be zero or the base mask of the opcode.
120 N.B. the fields are required to be in such an order than the most signficant
121 field for VALUE comes the first, e.g. the <index> in
122 SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
123 is encoded in H:L:M in some cases, the fields H:L:M should be passed in
124 the order of H, L, M. */
126 static inline aarch64_insn
127 extract_fields (aarch64_insn code, aarch64_insn mask, ...)
130 const aarch64_field *field;
131 enum aarch64_field_kind kind;
135 num = va_arg (va, uint32_t);
137 aarch64_insn value = 0x0;
140 kind = va_arg (va, enum aarch64_field_kind);
141 field = &fields[kind];
142 value <<= field->width;
143 value |= extract_field (kind, code, mask);
148 /* Extract the value of all fields in SELF->fields from instruction CODE.
149 The least significant bit comes from the final field. */
152 extract_all_fields (const aarch64_operand *self, aarch64_insn code)
156 enum aarch64_field_kind kind;
159 for (i = 0; i < ARRAY_SIZE (self->fields) && self->fields[i] != FLD_NIL; ++i)
161 kind = self->fields[i];
162 value <<= fields[kind].width;
163 value |= extract_field (kind, code, 0);
168 /* Sign-extend bit I of VALUE. */
169 static inline int32_t
170 sign_extend (aarch64_insn value, unsigned i)
172 uint32_t ret = value;
175 if ((value >> i) & 0x1)
177 uint32_t val = (uint32_t)(-1) << i;
180 return (int32_t) ret;
183 /* N.B. the following inline helpfer functions create a dependency on the
184 order of operand qualifier enumerators. */
186 /* Given VALUE, return qualifier for a general purpose register. */
187 static inline enum aarch64_opnd_qualifier
188 get_greg_qualifier_from_value (aarch64_insn value)
190 enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_W + value;
192 && aarch64_get_qualifier_standard_value (qualifier) == value);
196 /* Given VALUE, return qualifier for a vector register. This does not support
197 decoding instructions that accept the 2H vector type. */
199 static inline enum aarch64_opnd_qualifier
200 get_vreg_qualifier_from_value (aarch64_insn value)
202 enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_V_8B + value;
204 /* Instructions using vector type 2H should not call this function. Skip over
206 if (qualifier >= AARCH64_OPND_QLF_V_2H)
210 && aarch64_get_qualifier_standard_value (qualifier) == value);
214 /* Given VALUE, return qualifier for an FP or AdvSIMD scalar register. */
215 static inline enum aarch64_opnd_qualifier
216 get_sreg_qualifier_from_value (aarch64_insn value)
218 enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_S_B + value;
221 && aarch64_get_qualifier_standard_value (qualifier) == value);
225 /* Given the instruction in *INST which is probably half way through the
226 decoding and our caller wants to know the expected qualifier for operand
227 I. Return such a qualifier if we can establish it; otherwise return
228 AARCH64_OPND_QLF_NIL. */
230 static aarch64_opnd_qualifier_t
231 get_expected_qualifier (const aarch64_inst *inst, int i)
233 aarch64_opnd_qualifier_seq_t qualifiers;
234 /* Should not be called if the qualifier is known. */
235 assert (inst->operands[i].qualifier == AARCH64_OPND_QLF_NIL);
236 if (aarch64_find_best_match (inst, inst->opcode->qualifiers_list,
238 return qualifiers[i];
240 return AARCH64_OPND_QLF_NIL;
243 /* Operand extractors. */
246 aarch64_ext_regno (const aarch64_operand *self, aarch64_opnd_info *info,
247 const aarch64_insn code,
248 const aarch64_inst *inst ATTRIBUTE_UNUSED)
250 info->reg.regno = extract_field (self->fields[0], code, 0);
255 aarch64_ext_regno_pair (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info,
256 const aarch64_insn code ATTRIBUTE_UNUSED,
257 const aarch64_inst *inst ATTRIBUTE_UNUSED)
259 assert (info->idx == 1
261 info->reg.regno = inst->operands[info->idx - 1].reg.regno + 1;
265 /* e.g. IC <ic_op>{, <Xt>}. */
267 aarch64_ext_regrt_sysins (const aarch64_operand *self, aarch64_opnd_info *info,
268 const aarch64_insn code,
269 const aarch64_inst *inst ATTRIBUTE_UNUSED)
271 info->reg.regno = extract_field (self->fields[0], code, 0);
272 assert (info->idx == 1
273 && (aarch64_get_operand_class (inst->operands[0].type)
274 == AARCH64_OPND_CLASS_SYSTEM));
275 /* This will make the constraint checking happy and more importantly will
276 help the disassembler determine whether this operand is optional or
278 info->present = aarch64_sys_ins_reg_has_xt (inst->operands[0].sysins_op);
283 /* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
285 aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info,
286 const aarch64_insn code,
287 const aarch64_inst *inst ATTRIBUTE_UNUSED)
290 info->reglane.regno = extract_field (self->fields[0], code,
293 /* Index and/or type. */
294 if (inst->opcode->iclass == asisdone
295 || inst->opcode->iclass == asimdins)
297 if (info->type == AARCH64_OPND_En
298 && inst->opcode->operands[0] == AARCH64_OPND_Ed)
301 /* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]. */
302 assert (info->idx == 1); /* Vn */
303 aarch64_insn value = extract_field (FLD_imm4, code, 0);
304 /* Depend on AARCH64_OPND_Ed to determine the qualifier. */
305 info->qualifier = get_expected_qualifier (inst, info->idx);
306 shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier));
307 info->reglane.index = value >> shift;
311 /* index and type for e.g. DUP <V><d>, <Vn>.<T>[<index>].
319 aarch64_insn value = extract_field (FLD_imm5, code, 0);
320 while (++pos <= 3 && (value & 0x1) == 0)
324 info->qualifier = get_sreg_qualifier_from_value (pos);
325 info->reglane.index = (unsigned) (value >> 1);
330 /* Index only for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
331 or SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
333 /* Need information in other operand(s) to help decoding. */
334 info->qualifier = get_expected_qualifier (inst, info->idx);
335 switch (info->qualifier)
337 case AARCH64_OPND_QLF_S_H:
339 info->reglane.index = extract_fields (code, 0, 3, FLD_H, FLD_L,
341 info->reglane.regno &= 0xf;
343 case AARCH64_OPND_QLF_S_S:
345 info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L);
347 case AARCH64_OPND_QLF_S_D:
349 info->reglane.index = extract_field (FLD_H, code, 0);
360 aarch64_ext_reglist (const aarch64_operand *self, aarch64_opnd_info *info,
361 const aarch64_insn code,
362 const aarch64_inst *inst ATTRIBUTE_UNUSED)
365 info->reglist.first_regno = extract_field (self->fields[0], code, 0);
367 info->reglist.num_regs = extract_field (FLD_len, code, 0) + 1;
371 /* Decode Rt and opcode fields of Vt in AdvSIMD load/store instructions. */
373 aarch64_ext_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED,
374 aarch64_opnd_info *info, const aarch64_insn code,
375 const aarch64_inst *inst)
378 /* Number of elements in each structure to be loaded/stored. */
379 unsigned expected_num = get_opcode_dependent_value (inst->opcode);
383 unsigned is_reserved;
385 unsigned num_elements;
401 info->reglist.first_regno = extract_field (FLD_Rt, code, 0);
403 value = extract_field (FLD_opcode, code, 0);
404 if (expected_num != data[value].num_elements || data[value].is_reserved)
406 info->reglist.num_regs = data[value].num_regs;
411 /* Decode Rt and S fields of Vt in AdvSIMD load single structure to all
412 lanes instructions. */
414 aarch64_ext_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED,
415 aarch64_opnd_info *info, const aarch64_insn code,
416 const aarch64_inst *inst)
421 info->reglist.first_regno = extract_field (FLD_Rt, code, 0);
423 value = extract_field (FLD_S, code, 0);
425 /* Number of registers is equal to the number of elements in
426 each structure to be loaded/stored. */
427 info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
428 assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4);
430 /* Except when it is LD1R. */
431 if (info->reglist.num_regs == 1 && value == (aarch64_insn) 1)
432 info->reglist.num_regs = 2;
437 /* Decode Q, opcode<2:1>, S, size and Rt fields of Vt in AdvSIMD
438 load/store single element instructions. */
440 aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED,
441 aarch64_opnd_info *info, const aarch64_insn code,
442 const aarch64_inst *inst ATTRIBUTE_UNUSED)
444 aarch64_field field = {0, 0};
445 aarch64_insn QSsize; /* fields Q:S:size. */
446 aarch64_insn opcodeh2; /* opcode<2:1> */
449 info->reglist.first_regno = extract_field (FLD_Rt, code, 0);
451 /* Decode the index, opcode<2:1> and size. */
452 gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field);
453 opcodeh2 = extract_field_2 (&field, code, 0);
454 QSsize = extract_fields (code, 0, 3, FLD_Q, FLD_S, FLD_vldst_size);
458 info->qualifier = AARCH64_OPND_QLF_S_B;
459 /* Index encoded in "Q:S:size". */
460 info->reglist.index = QSsize;
466 info->qualifier = AARCH64_OPND_QLF_S_H;
467 /* Index encoded in "Q:S:size<1>". */
468 info->reglist.index = QSsize >> 1;
471 if ((QSsize >> 1) & 0x1)
474 if ((QSsize & 0x1) == 0)
476 info->qualifier = AARCH64_OPND_QLF_S_S;
477 /* Index encoded in "Q:S". */
478 info->reglist.index = QSsize >> 2;
482 if (extract_field (FLD_S, code, 0))
485 info->qualifier = AARCH64_OPND_QLF_S_D;
486 /* Index encoded in "Q". */
487 info->reglist.index = QSsize >> 3;
494 info->reglist.has_index = 1;
495 info->reglist.num_regs = 0;
496 /* Number of registers is equal to the number of elements in
497 each structure to be loaded/stored. */
498 info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
499 assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4);
504 /* Decode fields immh:immb and/or Q for e.g.
505 SSHR <Vd>.<T>, <Vn>.<T>, #<shift>
506 or SSHR <V><d>, <V><n>, #<shift>. */
509 aarch64_ext_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED,
510 aarch64_opnd_info *info, const aarch64_insn code,
511 const aarch64_inst *inst)
514 aarch64_insn Q, imm, immh;
515 enum aarch64_insn_class iclass = inst->opcode->iclass;
517 immh = extract_field (FLD_immh, code, 0);
520 imm = extract_fields (code, 0, 2, FLD_immh, FLD_immb);
522 /* Get highest set bit in immh. */
523 while (--pos >= 0 && (immh & 0x8) == 0)
526 assert ((iclass == asimdshf || iclass == asisdshf)
527 && (info->type == AARCH64_OPND_IMM_VLSR
528 || info->type == AARCH64_OPND_IMM_VLSL));
530 if (iclass == asimdshf)
532 Q = extract_field (FLD_Q, code, 0);
534 0000 x SEE AdvSIMD modified immediate
544 get_vreg_qualifier_from_value ((pos << 1) | (int) Q);
547 info->qualifier = get_sreg_qualifier_from_value (pos);
549 if (info->type == AARCH64_OPND_IMM_VLSR)
551 0000 SEE AdvSIMD modified immediate
552 0001 (16-UInt(immh:immb))
553 001x (32-UInt(immh:immb))
554 01xx (64-UInt(immh:immb))
555 1xxx (128-UInt(immh:immb)) */
556 info->imm.value = (16 << pos) - imm;
560 0000 SEE AdvSIMD modified immediate
561 0001 (UInt(immh:immb)-8)
562 001x (UInt(immh:immb)-16)
563 01xx (UInt(immh:immb)-32)
564 1xxx (UInt(immh:immb)-64) */
565 info->imm.value = imm - (8 << pos);
570 /* Decode shift immediate for e.g. sshr (imm). */
572 aarch64_ext_shll_imm (const aarch64_operand *self ATTRIBUTE_UNUSED,
573 aarch64_opnd_info *info, const aarch64_insn code,
574 const aarch64_inst *inst ATTRIBUTE_UNUSED)
578 val = extract_field (FLD_size, code, 0);
581 case 0: imm = 8; break;
582 case 1: imm = 16; break;
583 case 2: imm = 32; break;
586 info->imm.value = imm;
590 /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
591 value in the field(s) will be extracted as unsigned immediate value. */
593 aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info,
594 const aarch64_insn code,
595 const aarch64_inst *inst ATTRIBUTE_UNUSED)
599 imm = extract_all_fields (self, code);
601 if (operand_need_sign_extension (self))
602 imm = sign_extend (imm, get_operand_fields_width (self) - 1);
604 if (operand_need_shift_by_two (self))
607 if (info->type == AARCH64_OPND_ADDR_ADRP)
610 info->imm.value = imm;
614 /* Decode imm and its shifter for e.g. MOVZ <Wd>, #<imm16>{, LSL #<shift>}. */
616 aarch64_ext_imm_half (const aarch64_operand *self, aarch64_opnd_info *info,
617 const aarch64_insn code,
618 const aarch64_inst *inst ATTRIBUTE_UNUSED)
620 aarch64_ext_imm (self, info, code, inst);
621 info->shifter.kind = AARCH64_MOD_LSL;
622 info->shifter.amount = extract_field (FLD_hw, code, 0) << 4;
626 /* Decode cmode and "a:b:c:d:e:f:g:h" for e.g.
627 MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}. */
629 aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
630 aarch64_opnd_info *info,
631 const aarch64_insn code,
632 const aarch64_inst *inst ATTRIBUTE_UNUSED)
635 enum aarch64_opnd_qualifier opnd0_qualifier = inst->operands[0].qualifier;
636 aarch64_field field = {0, 0};
638 assert (info->idx == 1);
640 if (info->type == AARCH64_OPND_SIMD_FPIMM)
643 /* a:b:c:d:e:f:g:h */
644 imm = extract_fields (code, 0, 2, FLD_abc, FLD_defgh);
645 if (!info->imm.is_fp && aarch64_get_qualifier_esize (opnd0_qualifier) == 8)
647 /* Either MOVI <Dd>, #<imm>
648 or MOVI <Vd>.2D, #<imm>.
649 <imm> is a 64-bit immediate
650 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh',
651 encoded in "a:b:c:d:e:f:g:h". */
653 unsigned abcdefgh = imm;
654 for (imm = 0ull, i = 0; i < 8; i++)
655 if (((abcdefgh >> i) & 0x1) != 0)
656 imm |= 0xffull << (8 * i);
658 info->imm.value = imm;
661 info->qualifier = get_expected_qualifier (inst, info->idx);
662 switch (info->qualifier)
664 case AARCH64_OPND_QLF_NIL:
666 info->shifter.kind = AARCH64_MOD_NONE;
668 case AARCH64_OPND_QLF_LSL:
670 info->shifter.kind = AARCH64_MOD_LSL;
671 switch (aarch64_get_qualifier_esize (opnd0_qualifier))
673 case 4: gen_sub_field (FLD_cmode, 1, 2, &field); break; /* per word */
674 case 2: gen_sub_field (FLD_cmode, 1, 1, &field); break; /* per half */
675 case 1: gen_sub_field (FLD_cmode, 1, 0, &field); break; /* per byte */
676 default: assert (0); return 0;
678 /* 00: 0; 01: 8; 10:16; 11:24. */
679 info->shifter.amount = extract_field_2 (&field, code, 0) << 3;
681 case AARCH64_OPND_QLF_MSL:
683 info->shifter.kind = AARCH64_MOD_MSL;
684 gen_sub_field (FLD_cmode, 0, 1, &field); /* per word */
685 info->shifter.amount = extract_field_2 (&field, code, 0) ? 16 : 8;
695 /* Decode an 8-bit floating-point immediate. */
697 aarch64_ext_fpimm (const aarch64_operand *self, aarch64_opnd_info *info,
698 const aarch64_insn code,
699 const aarch64_inst *inst ATTRIBUTE_UNUSED)
701 info->imm.value = extract_all_fields (self, code);
706 /* Decode scale for e.g. SCVTF <Dd>, <Wn>, #<fbits>. */
708 aarch64_ext_fbits (const aarch64_operand *self ATTRIBUTE_UNUSED,
709 aarch64_opnd_info *info, const aarch64_insn code,
710 const aarch64_inst *inst ATTRIBUTE_UNUSED)
712 info->imm.value = 64- extract_field (FLD_scale, code, 0);
716 /* Decode arithmetic immediate for e.g.
717 SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}. */
719 aarch64_ext_aimm (const aarch64_operand *self ATTRIBUTE_UNUSED,
720 aarch64_opnd_info *info, const aarch64_insn code,
721 const aarch64_inst *inst ATTRIBUTE_UNUSED)
725 info->shifter.kind = AARCH64_MOD_LSL;
727 value = extract_field (FLD_shift, code, 0);
730 info->shifter.amount = value ? 12 : 0;
731 /* imm12 (unsigned) */
732 info->imm.value = extract_field (FLD_imm12, code, 0);
737 /* Return true if VALUE is a valid logical immediate encoding, storing the
738 decoded value in *RESULT if so. ESIZE is the number of bytes in the
739 decoded immediate. */
741 decode_limm (uint32_t esize, aarch64_insn value, int64_t *result)
747 /* value is N:immr:imms. */
749 R = (value >> 6) & 0x3f;
750 N = (value >> 12) & 0x1;
752 /* The immediate value is S+1 bits to 1, left rotated by SIMDsize - R
753 (in other words, right rotated by R), then replicated. */
757 mask = 0xffffffffffffffffull;
763 case 0x00 ... 0x1f: /* 0xxxxx */ simd_size = 32; break;
764 case 0x20 ... 0x2f: /* 10xxxx */ simd_size = 16; S &= 0xf; break;
765 case 0x30 ... 0x37: /* 110xxx */ simd_size = 8; S &= 0x7; break;
766 case 0x38 ... 0x3b: /* 1110xx */ simd_size = 4; S &= 0x3; break;
767 case 0x3c ... 0x3d: /* 11110x */ simd_size = 2; S &= 0x1; break;
770 mask = (1ull << simd_size) - 1;
771 /* Top bits are IGNORED. */
775 if (simd_size > esize * 8)
778 /* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected. */
779 if (S == simd_size - 1)
781 /* S+1 consecutive bits to 1. */
782 /* NOTE: S can't be 63 due to detection above. */
783 imm = (1ull << (S + 1)) - 1;
784 /* Rotate to the left by simd_size - R. */
786 imm = ((imm << (simd_size - R)) & mask) | (imm >> R);
787 /* Replicate the value according to SIMD size. */
790 case 2: imm = (imm << 2) | imm;
791 case 4: imm = (imm << 4) | imm;
792 case 8: imm = (imm << 8) | imm;
793 case 16: imm = (imm << 16) | imm;
794 case 32: imm = (imm << 32) | imm;
796 default: assert (0); return 0;
799 *result = imm & ~((uint64_t) -1 << (esize * 4) << (esize * 4));
804 /* Decode a logical immediate for e.g. ORR <Wd|WSP>, <Wn>, #<imm>. */
806 aarch64_ext_limm (const aarch64_operand *self,
807 aarch64_opnd_info *info, const aarch64_insn code,
808 const aarch64_inst *inst)
813 value = extract_fields (code, 0, 3, self->fields[0], self->fields[1],
815 esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier);
816 return decode_limm (esize, value, &info->imm.value);
819 /* Decode a logical immediate for the BIC alias of AND (etc.). */
821 aarch64_ext_inv_limm (const aarch64_operand *self,
822 aarch64_opnd_info *info, const aarch64_insn code,
823 const aarch64_inst *inst)
825 if (!aarch64_ext_limm (self, info, code, inst))
827 info->imm.value = ~info->imm.value;
831 /* Decode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
832 or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */
834 aarch64_ext_ft (const aarch64_operand *self ATTRIBUTE_UNUSED,
835 aarch64_opnd_info *info,
836 const aarch64_insn code, const aarch64_inst *inst)
841 info->reg.regno = extract_field (FLD_Rt, code, 0);
844 value = extract_field (FLD_ldst_size, code, 0);
845 if (inst->opcode->iclass == ldstpair_indexed
846 || inst->opcode->iclass == ldstnapair_offs
847 || inst->opcode->iclass == ldstpair_off
848 || inst->opcode->iclass == loadlit)
850 enum aarch64_opnd_qualifier qualifier;
853 case 0: qualifier = AARCH64_OPND_QLF_S_S; break;
854 case 1: qualifier = AARCH64_OPND_QLF_S_D; break;
855 case 2: qualifier = AARCH64_OPND_QLF_S_Q; break;
858 info->qualifier = qualifier;
863 value = extract_fields (code, 0, 2, FLD_opc1, FLD_ldst_size);
866 info->qualifier = get_sreg_qualifier_from_value (value);
872 /* Decode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */
874 aarch64_ext_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
875 aarch64_opnd_info *info,
877 const aarch64_inst *inst ATTRIBUTE_UNUSED)
880 info->addr.base_regno = extract_field (FLD_Rn, code, 0);
884 /* Decode the address operand for e.g.
885 STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
887 aarch64_ext_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED,
888 aarch64_opnd_info *info,
889 aarch64_insn code, const aarch64_inst *inst)
891 aarch64_insn S, value;
894 info->addr.base_regno = extract_field (FLD_Rn, code, 0);
896 info->addr.offset.regno = extract_field (FLD_Rm, code, 0);
898 value = extract_field (FLD_option, code, 0);
900 aarch64_get_operand_modifier_from_value (value, TRUE /* extend_p */);
901 /* Fix-up the shifter kind; although the table-driven approach is
902 efficient, it is slightly inflexible, thus needing this fix-up. */
903 if (info->shifter.kind == AARCH64_MOD_UXTX)
904 info->shifter.kind = AARCH64_MOD_LSL;
906 S = extract_field (FLD_S, code, 0);
909 info->shifter.amount = 0;
910 info->shifter.amount_present = 0;
915 /* Need information in other operand(s) to help achieve the decoding
917 info->qualifier = get_expected_qualifier (inst, info->idx);
918 /* Get the size of the data element that is accessed, which may be
919 different from that of the source register size, e.g. in strb/ldrb. */
920 size = aarch64_get_qualifier_esize (info->qualifier);
921 info->shifter.amount = get_logsz (size);
922 info->shifter.amount_present = 1;
928 /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>], #<simm>. */
930 aarch64_ext_addr_simm (const aarch64_operand *self, aarch64_opnd_info *info,
931 aarch64_insn code, const aarch64_inst *inst)
934 info->qualifier = get_expected_qualifier (inst, info->idx);
937 info->addr.base_regno = extract_field (FLD_Rn, code, 0);
938 /* simm (imm9 or imm7) */
939 imm = extract_field (self->fields[0], code, 0);
940 info->addr.offset.imm = sign_extend (imm, fields[self->fields[0]].width - 1);
941 if (self->fields[0] == FLD_imm7)
942 /* scaled immediate in ld/st pair instructions. */
943 info->addr.offset.imm *= aarch64_get_qualifier_esize (info->qualifier);
945 if (inst->opcode->iclass == ldst_unscaled
946 || inst->opcode->iclass == ldstnapair_offs
947 || inst->opcode->iclass == ldstpair_off
948 || inst->opcode->iclass == ldst_unpriv)
949 info->addr.writeback = 0;
952 /* pre/post- index */
953 info->addr.writeback = 1;
954 if (extract_field (self->fields[1], code, 0) == 1)
955 info->addr.preind = 1;
957 info->addr.postind = 1;
963 /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<simm>}]. */
965 aarch64_ext_addr_uimm12 (const aarch64_operand *self, aarch64_opnd_info *info,
967 const aarch64_inst *inst ATTRIBUTE_UNUSED)
970 info->qualifier = get_expected_qualifier (inst, info->idx);
971 shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier));
973 info->addr.base_regno = extract_field (self->fields[0], code, 0);
975 info->addr.offset.imm = extract_field (self->fields[1], code, 0) << shift;
979 /* Decode the address operand for e.g.
980 LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */
982 aarch64_ext_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED,
983 aarch64_opnd_info *info,
984 aarch64_insn code, const aarch64_inst *inst)
986 /* The opcode dependent area stores the number of elements in
987 each structure to be loaded/stored. */
988 int is_ld1r = get_opcode_dependent_value (inst->opcode) == 1;
991 info->addr.base_regno = extract_field (FLD_Rn, code, 0);
993 info->addr.offset.regno = extract_field (FLD_Rm, code, 0);
994 if (info->addr.offset.regno == 31)
996 if (inst->opcode->operands[0] == AARCH64_OPND_LVt_AL)
997 /* Special handling of loading single structure to all lane. */
998 info->addr.offset.imm = (is_ld1r ? 1
999 : inst->operands[0].reglist.num_regs)
1000 * aarch64_get_qualifier_esize (inst->operands[0].qualifier);
1002 info->addr.offset.imm = inst->operands[0].reglist.num_regs
1003 * aarch64_get_qualifier_esize (inst->operands[0].qualifier)
1004 * aarch64_get_qualifier_nelem (inst->operands[0].qualifier);
1007 info->addr.offset.is_reg = 1;
1008 info->addr.writeback = 1;
1013 /* Decode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>. */
1015 aarch64_ext_cond (const aarch64_operand *self ATTRIBUTE_UNUSED,
1016 aarch64_opnd_info *info,
1017 aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED)
1021 value = extract_field (FLD_cond, code, 0);
1022 info->cond = get_cond_from_value (value);
1026 /* Decode the system register operand for e.g. MRS <Xt>, <systemreg>. */
1028 aarch64_ext_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED,
1029 aarch64_opnd_info *info,
1031 const aarch64_inst *inst ATTRIBUTE_UNUSED)
1033 /* op0:op1:CRn:CRm:op2 */
1034 info->sysreg = extract_fields (code, 0, 5, FLD_op0, FLD_op1, FLD_CRn,
1039 /* Decode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>. */
1041 aarch64_ext_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED,
1042 aarch64_opnd_info *info, aarch64_insn code,
1043 const aarch64_inst *inst ATTRIBUTE_UNUSED)
1047 info->pstatefield = extract_fields (code, 0, 2, FLD_op1, FLD_op2);
1048 for (i = 0; aarch64_pstatefields[i].name != NULL; ++i)
1049 if (aarch64_pstatefields[i].value == (aarch64_insn)info->pstatefield)
1051 /* Reserved value in <pstatefield>. */
1055 /* Decode the system instruction op operand for e.g. AT <at_op>, <Xt>. */
1057 aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
1058 aarch64_opnd_info *info,
1060 const aarch64_inst *inst ATTRIBUTE_UNUSED)
1064 const aarch64_sys_ins_reg *sysins_ops;
1065 /* op0:op1:CRn:CRm:op2 */
1066 value = extract_fields (code, 0, 5,
1067 FLD_op0, FLD_op1, FLD_CRn,
1072 case AARCH64_OPND_SYSREG_AT: sysins_ops = aarch64_sys_regs_at; break;
1073 case AARCH64_OPND_SYSREG_DC: sysins_ops = aarch64_sys_regs_dc; break;
1074 case AARCH64_OPND_SYSREG_IC: sysins_ops = aarch64_sys_regs_ic; break;
1075 case AARCH64_OPND_SYSREG_TLBI: sysins_ops = aarch64_sys_regs_tlbi; break;
1076 default: assert (0); return 0;
1079 for (i = 0; sysins_ops[i].name != NULL; ++i)
1080 if (sysins_ops[i].value == value)
1082 info->sysins_op = sysins_ops + i;
1083 DEBUG_TRACE ("%s found value: %x, has_xt: %d, i: %d.",
1084 info->sysins_op->name,
1085 (unsigned)info->sysins_op->value,
1086 aarch64_sys_ins_reg_has_xt (info->sysins_op), i);
1093 /* Decode the memory barrier option operand for e.g. DMB <option>|#<imm>. */
1096 aarch64_ext_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED,
1097 aarch64_opnd_info *info,
1099 const aarch64_inst *inst ATTRIBUTE_UNUSED)
1102 info->barrier = aarch64_barrier_options + extract_field (FLD_CRm, code, 0);
1106 /* Decode the prefetch operation option operand for e.g.
1107 PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */
1110 aarch64_ext_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED,
1111 aarch64_opnd_info *info,
1112 aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED)
1115 info->prfop = aarch64_prfops + extract_field (FLD_Rt, code, 0);
1119 /* Decode the hint number for an alias taking an operand. Set info->hint_option
1120 to the matching name/value pair in aarch64_hint_options. */
1123 aarch64_ext_hint (const aarch64_operand *self ATTRIBUTE_UNUSED,
1124 aarch64_opnd_info *info,
1126 const aarch64_inst *inst ATTRIBUTE_UNUSED)
1129 unsigned hint_number;
1132 hint_number = extract_fields (code, 0, 2, FLD_CRm, FLD_op2);
1134 for (i = 0; aarch64_hint_options[i].name != NULL; i++)
1136 if (hint_number == aarch64_hint_options[i].value)
1138 info->hint_option = &(aarch64_hint_options[i]);
1146 /* Decode the extended register operand for e.g.
1147 STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1149 aarch64_ext_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED,
1150 aarch64_opnd_info *info,
1152 const aarch64_inst *inst ATTRIBUTE_UNUSED)
1157 info->reg.regno = extract_field (FLD_Rm, code, 0);
1159 value = extract_field (FLD_option, code, 0);
1160 info->shifter.kind =
1161 aarch64_get_operand_modifier_from_value (value, TRUE /* extend_p */);
1163 info->shifter.amount = extract_field (FLD_imm3, code, 0);
1165 /* This makes the constraint checking happy. */
1166 info->shifter.operator_present = 1;
1168 /* Assume inst->operands[0].qualifier has been resolved. */
1169 assert (inst->operands[0].qualifier != AARCH64_OPND_QLF_NIL);
1170 info->qualifier = AARCH64_OPND_QLF_W;
1171 if (inst->operands[0].qualifier == AARCH64_OPND_QLF_X
1172 && (info->shifter.kind == AARCH64_MOD_UXTX
1173 || info->shifter.kind == AARCH64_MOD_SXTX))
1174 info->qualifier = AARCH64_OPND_QLF_X;
1179 /* Decode the shifted register operand for e.g.
1180 SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}. */
1182 aarch64_ext_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
1183 aarch64_opnd_info *info,
1185 const aarch64_inst *inst ATTRIBUTE_UNUSED)
1190 info->reg.regno = extract_field (FLD_Rm, code, 0);
1192 value = extract_field (FLD_shift, code, 0);
1193 info->shifter.kind =
1194 aarch64_get_operand_modifier_from_value (value, FALSE /* extend_p */);
1195 if (info->shifter.kind == AARCH64_MOD_ROR
1196 && inst->opcode->iclass != log_shift)
1197 /* ROR is not available for the shifted register operand in arithmetic
1201 info->shifter.amount = extract_field (FLD_imm6, code, 0);
1203 /* This makes the constraint checking happy. */
1204 info->shifter.operator_present = 1;
1209 /* Decode an SVE address [<base>, #<offset>*<factor>, MUL VL],
1210 where <offset> is given by the OFFSET parameter and where <factor> is
1211 1 plus SELF's operand-dependent value. fields[0] specifies the field
1212 that holds <base>. */
1214 aarch64_ext_sve_addr_reg_mul_vl (const aarch64_operand *self,
1215 aarch64_opnd_info *info, aarch64_insn code,
1218 info->addr.base_regno = extract_field (self->fields[0], code, 0);
1219 info->addr.offset.imm = offset * (1 + get_operand_specific_data (self));
1220 info->addr.offset.is_reg = FALSE;
1221 info->addr.writeback = FALSE;
1222 info->addr.preind = TRUE;
1224 info->shifter.kind = AARCH64_MOD_MUL_VL;
1225 info->shifter.amount = 1;
1226 info->shifter.operator_present = (info->addr.offset.imm != 0);
1227 info->shifter.amount_present = FALSE;
1231 /* Decode an SVE address [<base>, #<simm4>*<factor>, MUL VL],
1232 where <simm4> is a 4-bit signed value and where <factor> is 1 plus
1233 SELF's operand-dependent value. fields[0] specifies the field that
1234 holds <base>. <simm4> is encoded in the SVE_imm4 field. */
1236 aarch64_ext_sve_addr_ri_s4xvl (const aarch64_operand *self,
1237 aarch64_opnd_info *info, aarch64_insn code,
1238 const aarch64_inst *inst ATTRIBUTE_UNUSED)
1242 offset = extract_field (FLD_SVE_imm4, code, 0);
1243 offset = ((offset + 8) & 15) - 8;
1244 return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset);
1247 /* Decode an SVE address [<base>, #<simm6>*<factor>, MUL VL],
1248 where <simm6> is a 6-bit signed value and where <factor> is 1 plus
1249 SELF's operand-dependent value. fields[0] specifies the field that
1250 holds <base>. <simm6> is encoded in the SVE_imm6 field. */
1252 aarch64_ext_sve_addr_ri_s6xvl (const aarch64_operand *self,
1253 aarch64_opnd_info *info, aarch64_insn code,
1254 const aarch64_inst *inst ATTRIBUTE_UNUSED)
1258 offset = extract_field (FLD_SVE_imm6, code, 0);
1259 offset = (((offset + 32) & 63) - 32);
1260 return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset);
1263 /* Decode an SVE address [<base>, #<simm9>*<factor>, MUL VL],
1264 where <simm9> is a 9-bit signed value and where <factor> is 1 plus
1265 SELF's operand-dependent value. fields[0] specifies the field that
1266 holds <base>. <simm9> is encoded in the concatenation of the SVE_imm6
1267 and imm3 fields, with imm3 being the less-significant part. */
1269 aarch64_ext_sve_addr_ri_s9xvl (const aarch64_operand *self,
1270 aarch64_opnd_info *info,
1272 const aarch64_inst *inst ATTRIBUTE_UNUSED)
1276 offset = extract_fields (code, 0, 2, FLD_SVE_imm6, FLD_imm3);
1277 offset = (((offset + 256) & 511) - 256);
1278 return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset);
1281 /* Decode an SVE address [<base>, #<offset> << <shift>], where <offset>
1282 is given by the OFFSET parameter and where <shift> is SELF's operand-
1283 dependent value. fields[0] specifies the base register field <base>. */
1285 aarch64_ext_sve_addr_reg_imm (const aarch64_operand *self,
1286 aarch64_opnd_info *info, aarch64_insn code,
1289 info->addr.base_regno = extract_field (self->fields[0], code, 0);
1290 info->addr.offset.imm = offset * (1 << get_operand_specific_data (self));
1291 info->addr.offset.is_reg = FALSE;
1292 info->addr.writeback = FALSE;
1293 info->addr.preind = TRUE;
1294 info->shifter.operator_present = FALSE;
1295 info->shifter.amount_present = FALSE;
1299 /* Decode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6>
1300 is a 6-bit unsigned number and where <shift> is SELF's operand-dependent
1301 value. fields[0] specifies the base register field. */
1303 aarch64_ext_sve_addr_ri_u6 (const aarch64_operand *self,
1304 aarch64_opnd_info *info, aarch64_insn code,
1305 const aarch64_inst *inst ATTRIBUTE_UNUSED)
1307 int offset = extract_field (FLD_SVE_imm6, code, 0);
1308 return aarch64_ext_sve_addr_reg_imm (self, info, code, offset);
1311 /* Decode an SVE address [X<n>, X<m>{, LSL #<shift>}], where <shift>
1312 is SELF's operand-dependent value. fields[0] specifies the base
1313 register field and fields[1] specifies the offset register field. */
1315 aarch64_ext_sve_addr_rr_lsl (const aarch64_operand *self,
1316 aarch64_opnd_info *info, aarch64_insn code,
1317 const aarch64_inst *inst ATTRIBUTE_UNUSED)
1321 index = extract_field (self->fields[1], code, 0);
1322 if (index == 31 && (self->flags & OPD_F_NO_ZR) != 0)
1325 info->addr.base_regno = extract_field (self->fields[0], code, 0);
1326 info->addr.offset.regno = index;
1327 info->addr.offset.is_reg = TRUE;
1328 info->addr.writeback = FALSE;
1329 info->addr.preind = TRUE;
1330 info->shifter.kind = AARCH64_MOD_LSL;
1331 info->shifter.amount = get_operand_specific_data (self);
1332 info->shifter.operator_present = (info->shifter.amount != 0);
1333 info->shifter.amount_present = (info->shifter.amount != 0);
1337 /* Decode an SVE address [X<n>, Z<m>.<T>, (S|U)XTW {#<shift>}], where
1338 <shift> is SELF's operand-dependent value. fields[0] specifies the
1339 base register field, fields[1] specifies the offset register field and
1340 fields[2] is a single-bit field that selects SXTW over UXTW. */
1342 aarch64_ext_sve_addr_rz_xtw (const aarch64_operand *self,
1343 aarch64_opnd_info *info, aarch64_insn code,
1344 const aarch64_inst *inst ATTRIBUTE_UNUSED)
1346 info->addr.base_regno = extract_field (self->fields[0], code, 0);
1347 info->addr.offset.regno = extract_field (self->fields[1], code, 0);
1348 info->addr.offset.is_reg = TRUE;
1349 info->addr.writeback = FALSE;
1350 info->addr.preind = TRUE;
1351 if (extract_field (self->fields[2], code, 0))
1352 info->shifter.kind = AARCH64_MOD_SXTW;
1354 info->shifter.kind = AARCH64_MOD_UXTW;
1355 info->shifter.amount = get_operand_specific_data (self);
1356 info->shifter.operator_present = TRUE;
1357 info->shifter.amount_present = (info->shifter.amount != 0);
1361 /* Decode an SVE address [Z<n>.<T>, #<imm5> << <shift>], where <imm5> is a
1362 5-bit unsigned number and where <shift> is SELF's operand-dependent value.
1363 fields[0] specifies the base register field. */
1365 aarch64_ext_sve_addr_zi_u5 (const aarch64_operand *self,
1366 aarch64_opnd_info *info, aarch64_insn code,
1367 const aarch64_inst *inst ATTRIBUTE_UNUSED)
1369 int offset = extract_field (FLD_imm5, code, 0);
1370 return aarch64_ext_sve_addr_reg_imm (self, info, code, offset);
1373 /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, <modifier> {#<msz>}}],
1374 where <modifier> is given by KIND and where <msz> is a 2-bit unsigned
1375 number. fields[0] specifies the base register field and fields[1]
1376 specifies the offset register field. */
1378 aarch64_ext_sve_addr_zz (const aarch64_operand *self, aarch64_opnd_info *info,
1379 aarch64_insn code, enum aarch64_modifier_kind kind)
1381 info->addr.base_regno = extract_field (self->fields[0], code, 0);
1382 info->addr.offset.regno = extract_field (self->fields[1], code, 0);
1383 info->addr.offset.is_reg = TRUE;
1384 info->addr.writeback = FALSE;
1385 info->addr.preind = TRUE;
1386 info->shifter.kind = kind;
1387 info->shifter.amount = extract_field (FLD_SVE_msz, code, 0);
1388 info->shifter.operator_present = (kind != AARCH64_MOD_LSL
1389 || info->shifter.amount != 0);
1390 info->shifter.amount_present = (info->shifter.amount != 0);
1394 /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, LSL #<msz>}], where
1395 <msz> is a 2-bit unsigned number. fields[0] specifies the base register
1396 field and fields[1] specifies the offset register field. */
1398 aarch64_ext_sve_addr_zz_lsl (const aarch64_operand *self,
1399 aarch64_opnd_info *info, aarch64_insn code,
1400 const aarch64_inst *inst ATTRIBUTE_UNUSED)
1402 return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_LSL);
1405 /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, SXTW {#<msz>}], where
1406 <msz> is a 2-bit unsigned number. fields[0] specifies the base register
1407 field and fields[1] specifies the offset register field. */
1409 aarch64_ext_sve_addr_zz_sxtw (const aarch64_operand *self,
1410 aarch64_opnd_info *info, aarch64_insn code,
1411 const aarch64_inst *inst ATTRIBUTE_UNUSED)
1413 return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_SXTW);
1416 /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, UXTW {#<msz>}], where
1417 <msz> is a 2-bit unsigned number. fields[0] specifies the base register
1418 field and fields[1] specifies the offset register field. */
1420 aarch64_ext_sve_addr_zz_uxtw (const aarch64_operand *self,
1421 aarch64_opnd_info *info, aarch64_insn code,
1422 const aarch64_inst *inst ATTRIBUTE_UNUSED)
1424 return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_UXTW);
1427 /* Finish decoding an SVE arithmetic immediate, given that INFO already
1428 has the raw field value and that the low 8 bits decode to VALUE. */
1430 decode_sve_aimm (aarch64_opnd_info *info, int64_t value)
1432 info->shifter.kind = AARCH64_MOD_LSL;
1433 info->shifter.amount = 0;
1434 if (info->imm.value & 0x100)
1437 /* Decode 0x100 as #0, LSL #8. */
1438 info->shifter.amount = 8;
1442 info->shifter.operator_present = (info->shifter.amount != 0);
1443 info->shifter.amount_present = (info->shifter.amount != 0);
1444 info->imm.value = value;
1448 /* Decode an SVE ADD/SUB immediate. */
1450 aarch64_ext_sve_aimm (const aarch64_operand *self,
1451 aarch64_opnd_info *info, const aarch64_insn code,
1452 const aarch64_inst *inst)
1454 return (aarch64_ext_imm (self, info, code, inst)
1455 && decode_sve_aimm (info, (uint8_t) info->imm.value));
1458 /* Decode an SVE CPY/DUP immediate. */
1460 aarch64_ext_sve_asimm (const aarch64_operand *self,
1461 aarch64_opnd_info *info, const aarch64_insn code,
1462 const aarch64_inst *inst)
1464 return (aarch64_ext_imm (self, info, code, inst)
1465 && decode_sve_aimm (info, (int8_t) info->imm.value));
1468 /* Decode Zn[MM], where MM has a 7-bit triangular encoding. The fields
1469 array specifies which field to use for Zn. MM is encoded in the
1470 concatenation of imm5 and SVE_tszh, with imm5 being the less
1471 significant part. */
1473 aarch64_ext_sve_index (const aarch64_operand *self,
1474 aarch64_opnd_info *info, aarch64_insn code,
1475 const aarch64_inst *inst ATTRIBUTE_UNUSED)
1479 info->reglane.regno = extract_field (self->fields[0], code, 0);
1480 val = extract_fields (code, 0, 2, FLD_SVE_tszh, FLD_imm5);
1481 if ((val & 15) == 0)
1483 while ((val & 1) == 0)
1485 info->reglane.index = val / 2;
1489 /* Decode a logical immediate for the MOV alias of SVE DUPM. */
1491 aarch64_ext_sve_limm_mov (const aarch64_operand *self,
1492 aarch64_opnd_info *info, const aarch64_insn code,
1493 const aarch64_inst *inst)
1495 int esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier);
1496 return (aarch64_ext_limm (self, info, code, inst)
1497 && aarch64_sve_dupm_mov_immediate_p (info->imm.value, esize));
1500 /* Decode {Zn.<T> - Zm.<T>}. The fields array specifies which field
1501 to use for Zn. The opcode-dependent value specifies the number
1502 of registers in the list. */
1504 aarch64_ext_sve_reglist (const aarch64_operand *self,
1505 aarch64_opnd_info *info, aarch64_insn code,
1506 const aarch64_inst *inst ATTRIBUTE_UNUSED)
1508 info->reglist.first_regno = extract_field (self->fields[0], code, 0);
1509 info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
1513 /* Decode <pattern>{, MUL #<amount>}. The fields array specifies which
1514 fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4
1517 aarch64_ext_sve_scale (const aarch64_operand *self,
1518 aarch64_opnd_info *info, aarch64_insn code,
1519 const aarch64_inst *inst)
1523 if (!aarch64_ext_imm (self, info, code, inst))
1525 val = extract_field (FLD_SVE_imm4, code, 0);
1526 info->shifter.kind = AARCH64_MOD_MUL;
1527 info->shifter.amount = val + 1;
1528 info->shifter.operator_present = (val != 0);
1529 info->shifter.amount_present = (val != 0);
1533 /* Return the top set bit in VALUE, which is expected to be relatively
1536 get_top_bit (uint64_t value)
1538 while ((value & -value) != value)
1539 value -= value & -value;
1543 /* Decode an SVE shift-left immediate. */
1545 aarch64_ext_sve_shlimm (const aarch64_operand *self,
1546 aarch64_opnd_info *info, const aarch64_insn code,
1547 const aarch64_inst *inst)
1549 if (!aarch64_ext_imm (self, info, code, inst)
1550 || info->imm.value == 0)
1553 info->imm.value -= get_top_bit (info->imm.value);
1557 /* Decode an SVE shift-right immediate. */
1559 aarch64_ext_sve_shrimm (const aarch64_operand *self,
1560 aarch64_opnd_info *info, const aarch64_insn code,
1561 const aarch64_inst *inst)
1563 if (!aarch64_ext_imm (self, info, code, inst)
1564 || info->imm.value == 0)
1567 info->imm.value = get_top_bit (info->imm.value) * 2 - info->imm.value;
1571 /* Bitfields that are commonly used to encode certain operands' information
1572 may be partially used as part of the base opcode in some instructions.
1573 For example, the bit 1 of the field 'size' in
1574 FCVTXN <Vb><d>, <Va><n>
1575 is actually part of the base opcode, while only size<0> is available
1576 for encoding the register type. Another example is the AdvSIMD
1577 instruction ORR (register), in which the field 'size' is also used for
1578 the base opcode, leaving only the field 'Q' available to encode the
1579 vector register arrangement specifier '8B' or '16B'.
1581 This function tries to deduce the qualifier from the value of partially
1582 constrained field(s). Given the VALUE of such a field or fields, the
1583 qualifiers CANDIDATES and the MASK (indicating which bits are valid for
1584 operand encoding), the function returns the matching qualifier or
1585 AARCH64_OPND_QLF_NIL if nothing matches.
1587 N.B. CANDIDATES is a group of possible qualifiers that are valid for
1588 one operand; it has a maximum of AARCH64_MAX_QLF_SEQ_NUM qualifiers and
1589 may end with AARCH64_OPND_QLF_NIL. */
1591 static enum aarch64_opnd_qualifier
1592 get_qualifier_from_partial_encoding (aarch64_insn value,
1593 const enum aarch64_opnd_qualifier* \
1598 DEBUG_TRACE ("enter with value: %d, mask: %d", (int)value, (int)mask);
1599 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
1601 aarch64_insn standard_value;
1602 if (candidates[i] == AARCH64_OPND_QLF_NIL)
1604 standard_value = aarch64_get_qualifier_standard_value (candidates[i]);
1605 if ((standard_value & mask) == (value & mask))
1606 return candidates[i];
1608 return AARCH64_OPND_QLF_NIL;
1611 /* Given a list of qualifier sequences, return all possible valid qualifiers
1612 for operand IDX in QUALIFIERS.
1613 Assume QUALIFIERS is an array whose length is large enough. */
1616 get_operand_possible_qualifiers (int idx,
1617 const aarch64_opnd_qualifier_seq_t *list,
1618 enum aarch64_opnd_qualifier *qualifiers)
1621 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
1622 if ((qualifiers[i] = list[i][idx]) == AARCH64_OPND_QLF_NIL)
1626 /* Decode the size Q field for e.g. SHADD.
1627 We tag one operand with the qualifer according to the code;
1628 whether the qualifier is valid for this opcode or not, it is the
1629 duty of the semantic checking. */
1632 decode_sizeq (aarch64_inst *inst)
1635 enum aarch64_opnd_qualifier qualifier;
1637 aarch64_insn value, mask;
1638 enum aarch64_field_kind fld_sz;
1639 enum aarch64_opnd_qualifier candidates[AARCH64_MAX_QLF_SEQ_NUM];
1641 if (inst->opcode->iclass == asisdlse
1642 || inst->opcode->iclass == asisdlsep
1643 || inst->opcode->iclass == asisdlso
1644 || inst->opcode->iclass == asisdlsop)
1645 fld_sz = FLD_vldst_size;
1650 value = extract_fields (code, inst->opcode->mask, 2, fld_sz, FLD_Q);
1651 /* Obtain the info that which bits of fields Q and size are actually
1652 available for operand encoding. Opcodes like FMAXNM and FMLA have
1653 size[1] unavailable. */
1654 mask = extract_fields (~inst->opcode->mask, 0, 2, fld_sz, FLD_Q);
1656 /* The index of the operand we are going to tag a qualifier and the qualifer
1657 itself are reasoned from the value of the size and Q fields and the
1658 possible valid qualifier lists. */
1659 idx = aarch64_select_operand_for_sizeq_field_coding (inst->opcode);
1660 DEBUG_TRACE ("key idx: %d", idx);
1662 /* For most related instruciton, size:Q are fully available for operand
1666 inst->operands[idx].qualifier = get_vreg_qualifier_from_value (value);
1670 get_operand_possible_qualifiers (idx, inst->opcode->qualifiers_list,
1672 #ifdef DEBUG_AARCH64
1676 for (i = 0; candidates[i] != AARCH64_OPND_QLF_NIL
1677 && i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
1678 DEBUG_TRACE ("qualifier %d: %s", i,
1679 aarch64_get_qualifier_name(candidates[i]));
1680 DEBUG_TRACE ("%d, %d", (int)value, (int)mask);
1682 #endif /* DEBUG_AARCH64 */
1684 qualifier = get_qualifier_from_partial_encoding (value, candidates, mask);
1686 if (qualifier == AARCH64_OPND_QLF_NIL)
1689 inst->operands[idx].qualifier = qualifier;
1693 /* Decode size[0]:Q, i.e. bit 22 and bit 30, for
1694 e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
1697 decode_asimd_fcvt (aarch64_inst *inst)
1699 aarch64_field field = {0, 0};
1701 enum aarch64_opnd_qualifier qualifier;
1703 gen_sub_field (FLD_size, 0, 1, &field);
1704 value = extract_field_2 (&field, inst->value, 0);
1705 qualifier = value == 0 ? AARCH64_OPND_QLF_V_4S
1706 : AARCH64_OPND_QLF_V_2D;
1707 switch (inst->opcode->op)
1711 /* FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
1712 inst->operands[1].qualifier = qualifier;
1716 /* FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */
1717 inst->operands[0].qualifier = qualifier;
1727 /* Decode size[0], i.e. bit 22, for
1728 e.g. FCVTXN <Vb><d>, <Va><n>. */
1731 decode_asisd_fcvtxn (aarch64_inst *inst)
1733 aarch64_field field = {0, 0};
1734 gen_sub_field (FLD_size, 0, 1, &field);
1735 if (!extract_field_2 (&field, inst->value, 0))
1737 inst->operands[0].qualifier = AARCH64_OPND_QLF_S_S;
1741 /* Decode the 'opc' field for e.g. FCVT <Dd>, <Sn>. */
1743 decode_fcvt (aarch64_inst *inst)
1745 enum aarch64_opnd_qualifier qualifier;
1747 const aarch64_field field = {15, 2};
1750 value = extract_field_2 (&field, inst->value, 0);
1753 case 0: qualifier = AARCH64_OPND_QLF_S_S; break;
1754 case 1: qualifier = AARCH64_OPND_QLF_S_D; break;
1755 case 3: qualifier = AARCH64_OPND_QLF_S_H; break;
1758 inst->operands[0].qualifier = qualifier;
1763 /* Do miscellaneous decodings that are not common enough to be driven by
1767 do_misc_decoding (aarch64_inst *inst)
1769 switch (inst->opcode->op)
1772 return decode_fcvt (inst);
1777 return decode_asimd_fcvt (inst);
1779 return decode_asisd_fcvtxn (inst);
1785 /* Opcodes that have fields shared by multiple operands are usually flagged
1786 with flags. In this function, we detect such flags, decode the related
1787 field(s) and store the information in one of the related operands. The
1788 'one' operand is not any operand but one of the operands that can
1789 accommadate all the information that has been decoded. */
1792 do_special_decoding (aarch64_inst *inst)
1796 /* Condition for truly conditional executed instructions, e.g. b.cond. */
1797 if (inst->opcode->flags & F_COND)
1799 value = extract_field (FLD_cond2, inst->value, 0);
1800 inst->cond = get_cond_from_value (value);
1803 if (inst->opcode->flags & F_SF)
1805 idx = select_operand_for_sf_field_coding (inst->opcode);
1806 value = extract_field (FLD_sf, inst->value, 0);
1807 inst->operands[idx].qualifier = get_greg_qualifier_from_value (value);
1808 if ((inst->opcode->flags & F_N)
1809 && extract_field (FLD_N, inst->value, 0) != value)
1813 if (inst->opcode->flags & F_LSE_SZ)
1815 idx = select_operand_for_sf_field_coding (inst->opcode);
1816 value = extract_field (FLD_lse_sz, inst->value, 0);
1817 inst->operands[idx].qualifier = get_greg_qualifier_from_value (value);
1819 /* size:Q fields. */
1820 if (inst->opcode->flags & F_SIZEQ)
1821 return decode_sizeq (inst);
1823 if (inst->opcode->flags & F_FPTYPE)
1825 idx = select_operand_for_fptype_field_coding (inst->opcode);
1826 value = extract_field (FLD_type, inst->value, 0);
1829 case 0: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_S; break;
1830 case 1: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_D; break;
1831 case 3: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_H; break;
1836 if (inst->opcode->flags & F_SSIZE)
1838 /* N.B. some opcodes like FCMGT <V><d>, <V><n>, #0 have the size[1] as part
1839 of the base opcode. */
1841 enum aarch64_opnd_qualifier candidates[AARCH64_MAX_QLF_SEQ_NUM];
1842 idx = select_operand_for_scalar_size_field_coding (inst->opcode);
1843 value = extract_field (FLD_size, inst->value, inst->opcode->mask);
1844 mask = extract_field (FLD_size, ~inst->opcode->mask, 0);
1845 /* For most related instruciton, the 'size' field is fully available for
1846 operand encoding. */
1848 inst->operands[idx].qualifier = get_sreg_qualifier_from_value (value);
1851 get_operand_possible_qualifiers (idx, inst->opcode->qualifiers_list,
1853 inst->operands[idx].qualifier
1854 = get_qualifier_from_partial_encoding (value, candidates, mask);
1858 if (inst->opcode->flags & F_T)
1860 /* Num of consecutive '0's on the right side of imm5<3:0>. */
1863 assert (aarch64_get_operand_class (inst->opcode->operands[0])
1864 == AARCH64_OPND_CLASS_SIMD_REG);
1875 val = extract_field (FLD_imm5, inst->value, 0);
1876 while ((val & 0x1) == 0 && ++num <= 3)
1880 Q = (unsigned) extract_field (FLD_Q, inst->value, inst->opcode->mask);
1881 inst->operands[0].qualifier =
1882 get_vreg_qualifier_from_value ((num << 1) | Q);
1885 if (inst->opcode->flags & F_GPRSIZE_IN_Q)
1887 /* Use Rt to encode in the case of e.g.
1888 STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */
1889 idx = aarch64_operand_index (inst->opcode->operands, AARCH64_OPND_Rt);
1892 /* Otherwise use the result operand, which has to be a integer
1894 assert (aarch64_get_operand_class (inst->opcode->operands[0])
1895 == AARCH64_OPND_CLASS_INT_REG);
1898 assert (idx == 0 || idx == 1);
1899 value = extract_field (FLD_Q, inst->value, 0);
1900 inst->operands[idx].qualifier = get_greg_qualifier_from_value (value);
1903 if (inst->opcode->flags & F_LDS_SIZE)
1905 aarch64_field field = {0, 0};
1906 assert (aarch64_get_operand_class (inst->opcode->operands[0])
1907 == AARCH64_OPND_CLASS_INT_REG);
1908 gen_sub_field (FLD_opc, 0, 1, &field);
1909 value = extract_field_2 (&field, inst->value, 0);
1910 inst->operands[0].qualifier
1911 = value ? AARCH64_OPND_QLF_W : AARCH64_OPND_QLF_X;
1914 /* Miscellaneous decoding; done as the last step. */
1915 if (inst->opcode->flags & F_MISC)
1916 return do_misc_decoding (inst);
1921 /* Converters converting a real opcode instruction to its alias form. */
1923 /* ROR <Wd>, <Ws>, #<shift>
1925 EXTR <Wd>, <Ws>, <Ws>, #<shift>. */
1927 convert_extr_to_ror (aarch64_inst *inst)
1929 if (inst->operands[1].reg.regno == inst->operands[2].reg.regno)
1931 copy_operand_info (inst, 2, 3);
1932 inst->operands[3].type = AARCH64_OPND_NIL;
1938 /* UXTL<Q> <Vd>.<Ta>, <Vn>.<Tb>
1940 USHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #0. */
1942 convert_shll_to_xtl (aarch64_inst *inst)
1944 if (inst->operands[2].imm.value == 0)
1946 inst->operands[2].type = AARCH64_OPND_NIL;
1953 UBFM <Xd>, <Xn>, #<shift>, #63.
1955 LSR <Xd>, <Xn>, #<shift>. */
1957 convert_bfm_to_sr (aarch64_inst *inst)
1961 imms = inst->operands[3].imm.value;
1962 val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 31 : 63;
1965 inst->operands[3].type = AARCH64_OPND_NIL;
1972 /* Convert MOV to ORR. */
1974 convert_orr_to_mov (aarch64_inst *inst)
1976 /* MOV <Vd>.<T>, <Vn>.<T>
1978 ORR <Vd>.<T>, <Vn>.<T>, <Vn>.<T>. */
1979 if (inst->operands[1].reg.regno == inst->operands[2].reg.regno)
1981 inst->operands[2].type = AARCH64_OPND_NIL;
1987 /* When <imms> >= <immr>, the instruction written:
1988 SBFX <Xd>, <Xn>, #<lsb>, #<width>
1990 SBFM <Xd>, <Xn>, #<lsb>, #(<lsb>+<width>-1). */
1993 convert_bfm_to_bfx (aarch64_inst *inst)
1997 immr = inst->operands[2].imm.value;
1998 imms = inst->operands[3].imm.value;
2002 inst->operands[2].imm.value = lsb;
2003 inst->operands[3].imm.value = imms + 1 - lsb;
2004 /* The two opcodes have different qualifiers for
2005 the immediate operands; reset to help the checking. */
2006 reset_operand_qualifier (inst, 2);
2007 reset_operand_qualifier (inst, 3);
2014 /* When <imms> < <immr>, the instruction written:
2015 SBFIZ <Xd>, <Xn>, #<lsb>, #<width>
2017 SBFM <Xd>, <Xn>, #((64-<lsb>)&0x3f), #(<width>-1). */
2020 convert_bfm_to_bfi (aarch64_inst *inst)
2022 int64_t immr, imms, val;
2024 immr = inst->operands[2].imm.value;
2025 imms = inst->operands[3].imm.value;
2026 val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 32 : 64;
2029 inst->operands[2].imm.value = (val - immr) & (val - 1);
2030 inst->operands[3].imm.value = imms + 1;
2031 /* The two opcodes have different qualifiers for
2032 the immediate operands; reset to help the checking. */
2033 reset_operand_qualifier (inst, 2);
2034 reset_operand_qualifier (inst, 3);
2041 /* The instruction written:
2042 BFC <Xd>, #<lsb>, #<width>
2044 BFM <Xd>, XZR, #((64-<lsb>)&0x3f), #(<width>-1). */
2047 convert_bfm_to_bfc (aarch64_inst *inst)
2049 int64_t immr, imms, val;
2051 /* Should have been assured by the base opcode value. */
2052 assert (inst->operands[1].reg.regno == 0x1f);
2054 immr = inst->operands[2].imm.value;
2055 imms = inst->operands[3].imm.value;
2056 val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 32 : 64;
2059 /* Drop XZR from the second operand. */
2060 copy_operand_info (inst, 1, 2);
2061 copy_operand_info (inst, 2, 3);
2062 inst->operands[3].type = AARCH64_OPND_NIL;
2064 /* Recalculate the immediates. */
2065 inst->operands[1].imm.value = (val - immr) & (val - 1);
2066 inst->operands[2].imm.value = imms + 1;
2068 /* The two opcodes have different qualifiers for the operands; reset to
2069 help the checking. */
2070 reset_operand_qualifier (inst, 1);
2071 reset_operand_qualifier (inst, 2);
2072 reset_operand_qualifier (inst, 3);
2080 /* The instruction written:
2081 LSL <Xd>, <Xn>, #<shift>
2083 UBFM <Xd>, <Xn>, #((64-<shift>)&0x3f), #(63-<shift>). */
2086 convert_ubfm_to_lsl (aarch64_inst *inst)
2088 int64_t immr = inst->operands[2].imm.value;
2089 int64_t imms = inst->operands[3].imm.value;
2091 = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 31 : 63;
2093 if ((immr == 0 && imms == val) || immr == imms + 1)
2095 inst->operands[3].type = AARCH64_OPND_NIL;
2096 inst->operands[2].imm.value = val - imms;
2103 /* CINC <Wd>, <Wn>, <cond>
2105 CSINC <Wd>, <Wn>, <Wn>, invert(<cond>)
2106 where <cond> is not AL or NV. */
2109 convert_from_csel (aarch64_inst *inst)
2111 if (inst->operands[1].reg.regno == inst->operands[2].reg.regno
2112 && (inst->operands[3].cond->value & 0xe) != 0xe)
2114 copy_operand_info (inst, 2, 3);
2115 inst->operands[2].cond = get_inverted_cond (inst->operands[3].cond);
2116 inst->operands[3].type = AARCH64_OPND_NIL;
2122 /* CSET <Wd>, <cond>
2124 CSINC <Wd>, WZR, WZR, invert(<cond>)
2125 where <cond> is not AL or NV. */
2128 convert_csinc_to_cset (aarch64_inst *inst)
2130 if (inst->operands[1].reg.regno == 0x1f
2131 && inst->operands[2].reg.regno == 0x1f
2132 && (inst->operands[3].cond->value & 0xe) != 0xe)
2134 copy_operand_info (inst, 1, 3);
2135 inst->operands[1].cond = get_inverted_cond (inst->operands[3].cond);
2136 inst->operands[3].type = AARCH64_OPND_NIL;
2137 inst->operands[2].type = AARCH64_OPND_NIL;
2145 MOVZ <Wd>, #<imm16>, LSL #<shift>.
2147 A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
2148 ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
2149 or where a MOVN has an immediate that could be encoded by MOVZ, or where
2150 MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the
2151 machine-instruction mnemonic must be used. */
2154 convert_movewide_to_mov (aarch64_inst *inst)
2156 uint64_t value = inst->operands[1].imm.value;
2157 /* MOVZ/MOVN #0 have a shift amount other than LSL #0. */
2158 if (value == 0 && inst->operands[1].shifter.amount != 0)
2160 inst->operands[1].type = AARCH64_OPND_IMM_MOV;
2161 inst->operands[1].shifter.kind = AARCH64_MOD_NONE;
2162 value <<= inst->operands[1].shifter.amount;
2163 /* As an alias convertor, it has to be clear that the INST->OPCODE
2164 is the opcode of the real instruction. */
2165 if (inst->opcode->op == OP_MOVN)
2167 int is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W;
2169 /* A MOVN has an immediate that could be encoded by MOVZ. */
2170 if (aarch64_wide_constant_p (value, is32, NULL) == TRUE)
2173 inst->operands[1].imm.value = value;
2174 inst->operands[1].shifter.amount = 0;
2180 ORR <Wd>, WZR, #<imm>.
2182 A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
2183 ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
2184 or where a MOVN has an immediate that could be encoded by MOVZ, or where
2185 MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the
2186 machine-instruction mnemonic must be used. */
2189 convert_movebitmask_to_mov (aarch64_inst *inst)
2194 /* Should have been assured by the base opcode value. */
2195 assert (inst->operands[1].reg.regno == 0x1f);
2196 copy_operand_info (inst, 1, 2);
2197 is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W;
2198 inst->operands[1].type = AARCH64_OPND_IMM_MOV;
2199 value = inst->operands[1].imm.value;
2200 /* ORR has an immediate that could be generated by a MOVZ or MOVN
2202 if (inst->operands[0].reg.regno != 0x1f
2203 && (aarch64_wide_constant_p (value, is32, NULL) == TRUE
2204 || aarch64_wide_constant_p (~value, is32, NULL) == TRUE))
2207 inst->operands[2].type = AARCH64_OPND_NIL;
2211 /* Some alias opcodes are disassembled by being converted from their real-form.
2212 N.B. INST->OPCODE is the real opcode rather than the alias. */
2215 convert_to_alias (aarch64_inst *inst, const aarch64_opcode *alias)
2221 return convert_bfm_to_sr (inst);
2223 return convert_ubfm_to_lsl (inst);
2227 return convert_from_csel (inst);
2230 return convert_csinc_to_cset (inst);
2234 return convert_bfm_to_bfx (inst);
2238 return convert_bfm_to_bfi (inst);
2240 return convert_bfm_to_bfc (inst);
2242 return convert_orr_to_mov (inst);
2243 case OP_MOV_IMM_WIDE:
2244 case OP_MOV_IMM_WIDEN:
2245 return convert_movewide_to_mov (inst);
2246 case OP_MOV_IMM_LOG:
2247 return convert_movebitmask_to_mov (inst);
2249 return convert_extr_to_ror (inst);
2254 return convert_shll_to_xtl (inst);
2260 static int aarch64_opcode_decode (const aarch64_opcode *, const aarch64_insn,
2261 aarch64_inst *, int);
2263 /* Given the instruction information in *INST, check if the instruction has
2264 any alias form that can be used to represent *INST. If the answer is yes,
2265 update *INST to be in the form of the determined alias. */
2267 /* In the opcode description table, the following flags are used in opcode
2268 entries to help establish the relations between the real and alias opcodes:
2270 F_ALIAS: opcode is an alias
2271 F_HAS_ALIAS: opcode has alias(es)
2274 F_P3: Disassembly preference priority 1-3 (the larger the
2275 higher). If nothing is specified, it is the priority
2276 0 by default, i.e. the lowest priority.
2278 Although the relation between the machine and the alias instructions are not
2279 explicitly described, it can be easily determined from the base opcode
2280 values, masks and the flags F_ALIAS and F_HAS_ALIAS in their opcode
2281 description entries:
2283 The mask of an alias opcode must be equal to or a super-set (i.e. more
2284 constrained) of that of the aliased opcode; so is the base opcode value.
2286 if (opcode_has_alias (real) && alias_opcode_p (opcode)
2287 && (opcode->mask & real->mask) == real->mask
2288 && (real->mask & opcode->opcode) == (real->mask & real->opcode))
2289 then OPCODE is an alias of, and only of, the REAL instruction
2291 The alias relationship is forced flat-structured to keep related algorithm
2292 simple; an opcode entry cannot be flagged with both F_ALIAS and F_HAS_ALIAS.
2294 During the disassembling, the decoding decision tree (in
2295 opcodes/aarch64-dis-2.c) always returns an machine instruction opcode entry;
2296 if the decoding of such a machine instruction succeeds (and -Mno-aliases is
2297 not specified), the disassembler will check whether there is any alias
2298 instruction exists for this real instruction. If there is, the disassembler
2299 will try to disassemble the 32-bit binary again using the alias's rule, or
2300 try to convert the IR to the form of the alias. In the case of the multiple
2301 aliases, the aliases are tried one by one from the highest priority
2302 (currently the flag F_P3) to the lowest priority (no priority flag), and the
2303 first succeeds first adopted.
2305 You may ask why there is a need for the conversion of IR from one form to
2306 another in handling certain aliases. This is because on one hand it avoids
2307 adding more operand code to handle unusual encoding/decoding; on other
2308 hand, during the disassembling, the conversion is an effective approach to
2309 check the condition of an alias (as an alias may be adopted only if certain
2310 conditions are met).
2312 In order to speed up the alias opcode lookup, aarch64-gen has preprocessed
2313 aarch64_opcode_table and generated aarch64_find_alias_opcode and
2314 aarch64_find_next_alias_opcode (in opcodes/aarch64-dis-2.c) to help. */
2317 determine_disassembling_preference (struct aarch64_inst *inst)
2319 const aarch64_opcode *opcode;
2320 const aarch64_opcode *alias;
2322 opcode = inst->opcode;
2324 /* This opcode does not have an alias, so use itself. */
2325 if (opcode_has_alias (opcode) == FALSE)
2328 alias = aarch64_find_alias_opcode (opcode);
2331 #ifdef DEBUG_AARCH64
2334 const aarch64_opcode *tmp = alias;
2335 printf ("#### LIST orderd: ");
2338 printf ("%s, ", tmp->name);
2339 tmp = aarch64_find_next_alias_opcode (tmp);
2343 #endif /* DEBUG_AARCH64 */
2345 for (; alias; alias = aarch64_find_next_alias_opcode (alias))
2347 DEBUG_TRACE ("try %s", alias->name);
2348 assert (alias_opcode_p (alias) || opcode_has_alias (opcode));
2350 /* An alias can be a pseudo opcode which will never be used in the
2351 disassembly, e.g. BIC logical immediate is such a pseudo opcode
2353 if (pseudo_opcode_p (alias))
2355 DEBUG_TRACE ("skip pseudo %s", alias->name);
2359 if ((inst->value & alias->mask) != alias->opcode)
2361 DEBUG_TRACE ("skip %s as base opcode not match", alias->name);
2364 /* No need to do any complicated transformation on operands, if the alias
2365 opcode does not have any operand. */
2366 if (aarch64_num_of_operands (alias) == 0 && alias->opcode == inst->value)
2368 DEBUG_TRACE ("succeed with 0-operand opcode %s", alias->name);
2369 aarch64_replace_opcode (inst, alias);
2372 if (alias->flags & F_CONV)
2375 memcpy (©, inst, sizeof (aarch64_inst));
2376 /* ALIAS is the preference as long as the instruction can be
2377 successfully converted to the form of ALIAS. */
2378 if (convert_to_alias (©, alias) == 1)
2380 aarch64_replace_opcode (©, alias);
2381 assert (aarch64_match_operands_constraint (©, NULL));
2382 DEBUG_TRACE ("succeed with %s via conversion", alias->name);
2383 memcpy (inst, ©, sizeof (aarch64_inst));
2389 /* Directly decode the alias opcode. */
2391 memset (&temp, '\0', sizeof (aarch64_inst));
2392 if (aarch64_opcode_decode (alias, inst->value, &temp, 1) == 1)
2394 DEBUG_TRACE ("succeed with %s via direct decoding", alias->name);
2395 memcpy (inst, &temp, sizeof (aarch64_inst));
2402 /* Decode the CODE according to OPCODE; fill INST. Return 0 if the decoding
2403 fails, which meanes that CODE is not an instruction of OPCODE; otherwise
2406 If OPCODE has alias(es) and NOALIASES_P is 0, an alias opcode may be
2407 determined and used to disassemble CODE; this is done just before the
2411 aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code,
2412 aarch64_inst *inst, int noaliases_p)
2416 DEBUG_TRACE ("enter with %s", opcode->name);
2418 assert (opcode && inst);
2420 /* Check the base opcode. */
2421 if ((code & opcode->mask) != (opcode->opcode & opcode->mask))
2423 DEBUG_TRACE ("base opcode match FAIL");
2428 memset (inst, '\0', sizeof (aarch64_inst));
2430 inst->opcode = opcode;
2433 /* Assign operand codes and indexes. */
2434 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2436 if (opcode->operands[i] == AARCH64_OPND_NIL)
2438 inst->operands[i].type = opcode->operands[i];
2439 inst->operands[i].idx = i;
2442 /* Call the opcode decoder indicated by flags. */
2443 if (opcode_has_special_coder (opcode) && do_special_decoding (inst) == 0)
2445 DEBUG_TRACE ("opcode flag-based decoder FAIL");
2449 /* Call operand decoders. */
2450 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2452 const aarch64_operand *opnd;
2453 enum aarch64_opnd type;
2455 type = opcode->operands[i];
2456 if (type == AARCH64_OPND_NIL)
2458 opnd = &aarch64_operands[type];
2459 if (operand_has_extractor (opnd)
2460 && (! aarch64_extract_operand (opnd, &inst->operands[i], code, inst)))
2462 DEBUG_TRACE ("operand decoder FAIL at operand %d", i);
2467 /* If the opcode has a verifier, then check it now. */
2468 if (opcode->verifier && ! opcode->verifier (opcode, code))
2470 DEBUG_TRACE ("operand verifier FAIL");
2474 /* Match the qualifiers. */
2475 if (aarch64_match_operands_constraint (inst, NULL) == 1)
2477 /* Arriving here, the CODE has been determined as a valid instruction
2478 of OPCODE and *INST has been filled with information of this OPCODE
2479 instruction. Before the return, check if the instruction has any
2480 alias and should be disassembled in the form of its alias instead.
2481 If the answer is yes, *INST will be updated. */
2483 determine_disassembling_preference (inst);
2484 DEBUG_TRACE ("SUCCESS");
2489 DEBUG_TRACE ("constraint matching FAIL");
2496 /* This does some user-friendly fix-up to *INST. It is currently focus on
2497 the adjustment of qualifiers to help the printed instruction
2498 recognized/understood more easily. */
2501 user_friendly_fixup (aarch64_inst *inst)
2503 switch (inst->opcode->iclass)
2506 /* TBNZ Xn|Wn, #uimm6, label
2507 Test and Branch Not Zero: conditionally jumps to label if bit number
2508 uimm6 in register Xn is not zero. The bit number implies the width of
2509 the register, which may be written and should be disassembled as Wn if
2510 uimm is less than 32. Limited to a branch offset range of +/- 32KiB.
2512 if (inst->operands[1].imm.value < 32)
2513 inst->operands[0].qualifier = AARCH64_OPND_QLF_W;
2519 /* Decode INSN and fill in *INST the instruction information. An alias
2520 opcode may be filled in *INSN if NOALIASES_P is FALSE. Return zero on
2524 aarch64_decode_insn (aarch64_insn insn, aarch64_inst *inst,
2525 bfd_boolean noaliases_p)
2527 const aarch64_opcode *opcode = aarch64_opcode_lookup (insn);
2529 #ifdef DEBUG_AARCH64
2532 const aarch64_opcode *tmp = opcode;
2534 DEBUG_TRACE ("opcode lookup:");
2537 aarch64_verbose (" %s", tmp->name);
2538 tmp = aarch64_find_next_opcode (tmp);
2541 #endif /* DEBUG_AARCH64 */
2543 /* A list of opcodes may have been found, as aarch64_opcode_lookup cannot
2544 distinguish some opcodes, e.g. SSHR and MOVI, which almost share the same
2545 opcode field and value, apart from the difference that one of them has an
2546 extra field as part of the opcode, but such a field is used for operand
2547 encoding in other opcode(s) ('immh' in the case of the example). */
2548 while (opcode != NULL)
2550 /* But only one opcode can be decoded successfully for, as the
2551 decoding routine will check the constraint carefully. */
2552 if (aarch64_opcode_decode (opcode, insn, inst, noaliases_p) == 1)
2554 opcode = aarch64_find_next_opcode (opcode);
2560 /* Print operands. */
2563 print_operands (bfd_vma pc, const aarch64_opcode *opcode,
2564 const aarch64_opnd_info *opnds, struct disassemble_info *info)
2566 int i, pcrel_p, num_printed;
2567 for (i = 0, num_printed = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2570 /* We regard the opcode operand info more, however we also look into
2571 the inst->operands to support the disassembling of the optional
2573 The two operand code should be the same in all cases, apart from
2574 when the operand can be optional. */
2575 if (opcode->operands[i] == AARCH64_OPND_NIL
2576 || opnds[i].type == AARCH64_OPND_NIL)
2579 /* Generate the operand string in STR. */
2580 aarch64_print_operand (str, sizeof (str), pc, opcode, opnds, i, &pcrel_p,
2583 /* Print the delimiter (taking account of omitted operand(s)). */
2585 (*info->fprintf_func) (info->stream, "%s",
2586 num_printed++ == 0 ? "\t" : ", ");
2588 /* Print the operand. */
2590 (*info->print_address_func) (info->target, info);
2592 (*info->fprintf_func) (info->stream, "%s", str);
2596 /* Print the instruction mnemonic name. */
2599 print_mnemonic_name (const aarch64_inst *inst, struct disassemble_info *info)
2601 if (inst->opcode->flags & F_COND)
2603 /* For instructions that are truly conditionally executed, e.g. b.cond,
2604 prepare the full mnemonic name with the corresponding condition
2609 ptr = strchr (inst->opcode->name, '.');
2610 assert (ptr && inst->cond);
2611 len = ptr - inst->opcode->name;
2613 strncpy (name, inst->opcode->name, len);
2615 (*info->fprintf_func) (info->stream, "%s.%s", name, inst->cond->names[0]);
2618 (*info->fprintf_func) (info->stream, "%s", inst->opcode->name);
2621 /* Print the instruction according to *INST. */
2624 print_aarch64_insn (bfd_vma pc, const aarch64_inst *inst,
2625 struct disassemble_info *info)
2627 print_mnemonic_name (inst, info);
2628 print_operands (pc, inst->opcode, inst->operands, info);
2631 /* Entry-point of the instruction disassembler and printer. */
2634 print_insn_aarch64_word (bfd_vma pc,
2636 struct disassemble_info *info)
2638 static const char *err_msg[6] =
2641 [-ERR_UND] = "undefined",
2642 [-ERR_UNP] = "unpredictable",
2649 info->insn_info_valid = 1;
2650 info->branch_delay_insns = 0;
2651 info->data_size = 0;
2655 if (info->flags & INSN_HAS_RELOC)
2656 /* If the instruction has a reloc associated with it, then
2657 the offset field in the instruction will actually be the
2658 addend for the reloc. (If we are using REL type relocs).
2659 In such cases, we can ignore the pc when computing
2660 addresses, since the addend is not currently pc-relative. */
2663 ret = aarch64_decode_insn (word, &inst, no_aliases);
2665 if (((word >> 21) & 0x3ff) == 1)
2667 /* RESERVED for ALES. */
2668 assert (ret != ERR_OK);
2677 /* Handle undefined instructions. */
2678 info->insn_type = dis_noninsn;
2679 (*info->fprintf_func) (info->stream,".inst\t0x%08x ; %s",
2680 word, err_msg[-ret]);
2683 user_friendly_fixup (&inst);
2684 print_aarch64_insn (pc, &inst, info);
2691 /* Disallow mapping symbols ($x, $d etc) from
2692 being displayed in symbol relative addresses. */
2695 aarch64_symbol_is_valid (asymbol * sym,
2696 struct disassemble_info * info ATTRIBUTE_UNUSED)
2703 name = bfd_asymbol_name (sym);
2707 || (name[1] != 'x' && name[1] != 'd')
2708 || (name[2] != '\0' && name[2] != '.'));
2711 /* Print data bytes on INFO->STREAM. */
2714 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
2716 struct disassemble_info *info)
2718 switch (info->bytes_per_chunk)
2721 info->fprintf_func (info->stream, ".byte\t0x%02x", word);
2724 info->fprintf_func (info->stream, ".short\t0x%04x", word);
2727 info->fprintf_func (info->stream, ".word\t0x%08x", word);
2734 /* Try to infer the code or data type from a symbol.
2735 Returns nonzero if *MAP_TYPE was set. */
2738 get_sym_code_type (struct disassemble_info *info, int n,
2739 enum map_type *map_type)
2741 elf_symbol_type *es;
2745 es = *(elf_symbol_type **)(info->symtab + n);
2746 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2748 /* If the symbol has function type then use that. */
2749 if (type == STT_FUNC)
2751 *map_type = MAP_INSN;
2755 /* Check for mapping symbols. */
2756 name = bfd_asymbol_name(info->symtab[n]);
2758 && (name[1] == 'x' || name[1] == 'd')
2759 && (name[2] == '\0' || name[2] == '.'))
2761 *map_type = (name[1] == 'x' ? MAP_INSN : MAP_DATA);
2768 /* Entry-point of the AArch64 disassembler. */
2771 print_insn_aarch64 (bfd_vma pc,
2772 struct disassemble_info *info)
2774 bfd_byte buffer[INSNLEN];
2776 void (*printer) (bfd_vma, uint32_t, struct disassemble_info *);
2777 bfd_boolean found = FALSE;
2778 unsigned int size = 4;
2781 if (info->disassembler_options)
2783 set_default_aarch64_dis_options (info);
2785 parse_aarch64_dis_options (info->disassembler_options);
2787 /* To avoid repeated parsing of these options, we remove them here. */
2788 info->disassembler_options = NULL;
2791 /* Aarch64 instructions are always little-endian */
2792 info->endian_code = BFD_ENDIAN_LITTLE;
2794 /* First check the full symtab for a mapping symbol, even if there
2795 are no usable non-mapping symbols for this address. */
2796 if (info->symtab_size != 0
2797 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
2799 enum map_type type = MAP_INSN;
2804 if (pc <= last_mapping_addr)
2805 last_mapping_sym = -1;
2807 /* Start scanning at the start of the function, or wherever
2808 we finished last time. */
2809 n = info->symtab_pos + 1;
2810 if (n < last_mapping_sym)
2811 n = last_mapping_sym;
2813 /* Scan up to the location being disassembled. */
2814 for (; n < info->symtab_size; n++)
2816 addr = bfd_asymbol_value (info->symtab[n]);
2819 if ((info->section == NULL
2820 || info->section == info->symtab[n]->section)
2821 && get_sym_code_type (info, n, &type))
2830 n = info->symtab_pos;
2831 if (n < last_mapping_sym)
2832 n = last_mapping_sym;
2834 /* No mapping symbol found at this address. Look backwards
2835 for a preceeding one. */
2838 if (get_sym_code_type (info, n, &type))
2847 last_mapping_sym = last_sym;
2850 /* Look a little bit ahead to see if we should print out
2851 less than four bytes of data. If there's a symbol,
2852 mapping or otherwise, after two bytes then don't
2854 if (last_type == MAP_DATA)
2856 size = 4 - (pc & 3);
2857 for (n = last_sym + 1; n < info->symtab_size; n++)
2859 addr = bfd_asymbol_value (info->symtab[n]);
2862 if (addr - pc < size)
2867 /* If the next symbol is after three bytes, we need to
2868 print only part of the data, so that we can use either
2871 size = (pc & 1) ? 1 : 2;
2875 if (last_type == MAP_DATA)
2877 /* size was set above. */
2878 info->bytes_per_chunk = size;
2879 info->display_endian = info->endian;
2880 printer = print_insn_data;
2884 info->bytes_per_chunk = size = INSNLEN;
2885 info->display_endian = info->endian_code;
2886 printer = print_insn_aarch64_word;
2889 status = (*info->read_memory_func) (pc, buffer, size, info);
2892 (*info->memory_error_func) (status, pc, info);
2896 data = bfd_get_bits (buffer, size * 8,
2897 info->display_endian == BFD_ENDIAN_BIG);
2899 (*printer) (pc, data, info);
2905 print_aarch64_disassembler_options (FILE *stream)
2907 fprintf (stream, _("\n\
2908 The following AARCH64 specific disassembler options are supported for use\n\
2909 with the -M switch (multiple options should be separated by commas):\n"));
2911 fprintf (stream, _("\n\
2912 no-aliases Don't print instruction aliases.\n"));
2914 fprintf (stream, _("\n\
2915 aliases Do print instruction aliases.\n"));
2917 #ifdef DEBUG_AARCH64
2918 fprintf (stream, _("\n\
2919 debug_dump Temp switch for debug trace.\n"));
2920 #endif /* DEBUG_AARCH64 */
2922 fprintf (stream, _("\n"));