1 /* aarch64-asm.c -- AArch64 assembler support.
2 Copyright (C) 2012-2016 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
23 #include "libiberty.h"
24 #include "aarch64-asm.h"
28 /* The unnamed arguments consist of the number of fields and information about
29 these fields where the VALUE will be inserted into CODE. MASK can be zero or
30 the base mask of the opcode.
32 N.B. the fields are required to be in such an order than the least signficant
33 field for VALUE comes the first, e.g. the <index> in
34 SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
35 is encoded in H:L:M in some cases, the fields H:L:M should be passed in
36 the order of M, L, H. */
39 insert_fields (aarch64_insn *code, aarch64_insn value, aarch64_insn mask, ...)
42 const aarch64_field *field;
43 enum aarch64_field_kind kind;
47 num = va_arg (va, uint32_t);
51 kind = va_arg (va, enum aarch64_field_kind);
52 field = &fields[kind];
53 insert_field (kind, code, value, mask);
54 value >>= field->width;
59 /* Insert a raw field value VALUE into all fields in SELF->fields.
60 The least significant bit goes in the final field. */
63 insert_all_fields (const aarch64_operand *self, aarch64_insn *code,
67 enum aarch64_field_kind kind;
69 for (i = ARRAY_SIZE (self->fields); i-- > 0; )
70 if (self->fields[i] != FLD_NIL)
72 kind = self->fields[i];
73 insert_field (kind, code, value, 0);
74 value >>= fields[kind].width;
78 /* Operand inserters. */
80 /* Insert register number. */
82 aarch64_ins_regno (const aarch64_operand *self, const aarch64_opnd_info *info,
84 const aarch64_inst *inst ATTRIBUTE_UNUSED)
86 insert_field (self->fields[0], code, info->reg.regno, 0);
90 /* Insert register number, index and/or other data for SIMD register element
91 operand, e.g. the last source operand in
92 SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
94 aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
95 aarch64_insn *code, const aarch64_inst *inst)
98 insert_field (self->fields[0], code, info->reglane.regno, inst->opcode->mask);
99 /* index and/or type */
100 if (inst->opcode->iclass == asisdone || inst->opcode->iclass == asimdins)
102 int pos = info->qualifier - AARCH64_OPND_QLF_S_B;
103 if (info->type == AARCH64_OPND_En
104 && inst->opcode->operands[0] == AARCH64_OPND_Ed)
106 /* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]. */
107 assert (info->idx == 1); /* Vn */
108 aarch64_insn value = info->reglane.index << pos;
109 insert_field (FLD_imm4, code, value, 0);
113 /* index and type for e.g. DUP <V><d>, <Vn>.<T>[<index>].
120 aarch64_insn value = ((info->reglane.index << 1) | 1) << pos;
121 insert_field (FLD_imm5, code, value, 0);
126 /* index for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
127 or SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
128 switch (info->qualifier)
130 case AARCH64_OPND_QLF_S_H:
132 insert_fields (code, info->reglane.index, 0, 3, FLD_M, FLD_L, FLD_H);
134 case AARCH64_OPND_QLF_S_S:
136 insert_fields (code, info->reglane.index, 0, 2, FLD_L, FLD_H);
138 case AARCH64_OPND_QLF_S_D:
140 insert_field (FLD_H, code, info->reglane.index, 0);
149 /* Insert regno and len field of a register list operand, e.g. Vn in TBL. */
151 aarch64_ins_reglist (const aarch64_operand *self, const aarch64_opnd_info *info,
153 const aarch64_inst *inst ATTRIBUTE_UNUSED)
156 insert_field (self->fields[0], code, info->reglist.first_regno, 0);
158 insert_field (FLD_len, code, info->reglist.num_regs - 1, 0);
162 /* Insert Rt and opcode fields for a register list operand, e.g. Vt
163 in AdvSIMD load/store instructions. */
165 aarch64_ins_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED,
166 const aarch64_opnd_info *info, aarch64_insn *code,
167 const aarch64_inst *inst)
169 aarch64_insn value = 0;
170 /* Number of elements in each structure to be loaded/stored. */
171 unsigned num = get_opcode_dependent_value (inst->opcode);
174 insert_field (FLD_Rt, code, info->reglist.first_regno, 0);
179 switch (info->reglist.num_regs)
181 case 1: value = 0x7; break;
182 case 2: value = 0xa; break;
183 case 3: value = 0x6; break;
184 case 4: value = 0x2; break;
189 value = info->reglist.num_regs == 4 ? 0x3 : 0x8;
200 insert_field (FLD_opcode, code, value, 0);
205 /* Insert Rt and S fields for a register list operand, e.g. Vt in AdvSIMD load
206 single structure to all lanes instructions. */
208 aarch64_ins_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED,
209 const aarch64_opnd_info *info, aarch64_insn *code,
210 const aarch64_inst *inst)
213 /* The opcode dependent area stores the number of elements in
214 each structure to be loaded/stored. */
215 int is_ld1r = get_opcode_dependent_value (inst->opcode) == 1;
218 insert_field (FLD_Rt, code, info->reglist.first_regno, 0);
220 value = (aarch64_insn) 0;
221 if (is_ld1r && info->reglist.num_regs == 2)
222 /* OP_LD1R does not have alternating variant, but have "two consecutive"
224 value = (aarch64_insn) 1;
225 insert_field (FLD_S, code, value, 0);
230 /* Insert Q, opcode<2:1>, S, size and Rt fields for a register element list
231 operand e.g. Vt in AdvSIMD load/store single element instructions. */
233 aarch64_ins_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED,
234 const aarch64_opnd_info *info, aarch64_insn *code,
235 const aarch64_inst *inst ATTRIBUTE_UNUSED)
237 aarch64_field field = {0, 0};
238 aarch64_insn QSsize = 0; /* fields Q:S:size. */
239 aarch64_insn opcodeh2 = 0; /* opcode<2:1> */
241 assert (info->reglist.has_index);
244 insert_field (FLD_Rt, code, info->reglist.first_regno, 0);
245 /* Encode the index, opcode<2:1> and size. */
246 switch (info->qualifier)
248 case AARCH64_OPND_QLF_S_B:
249 /* Index encoded in "Q:S:size". */
250 QSsize = info->reglist.index;
253 case AARCH64_OPND_QLF_S_H:
254 /* Index encoded in "Q:S:size<1>". */
255 QSsize = info->reglist.index << 1;
258 case AARCH64_OPND_QLF_S_S:
259 /* Index encoded in "Q:S". */
260 QSsize = info->reglist.index << 2;
263 case AARCH64_OPND_QLF_S_D:
264 /* Index encoded in "Q". */
265 QSsize = info->reglist.index << 3 | 0x1;
271 insert_fields (code, QSsize, 0, 3, FLD_vldst_size, FLD_S, FLD_Q);
272 gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field);
273 insert_field_2 (&field, code, opcodeh2, 0);
278 /* Insert fields immh:immb and/or Q for e.g. the shift immediate in
279 SSHR <Vd>.<T>, <Vn>.<T>, #<shift>
280 or SSHR <V><d>, <V><n>, #<shift>. */
282 aarch64_ins_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED,
283 const aarch64_opnd_info *info,
284 aarch64_insn *code, const aarch64_inst *inst)
286 unsigned val = aarch64_get_qualifier_standard_value (info->qualifier);
289 if (inst->opcode->iclass == asimdshf)
293 0000 x SEE AdvSIMD modified immediate
302 Q = (val & 0x1) ? 1 : 0;
303 insert_field (FLD_Q, code, Q, inst->opcode->mask);
307 assert (info->type == AARCH64_OPND_IMM_VLSR
308 || info->type == AARCH64_OPND_IMM_VLSL);
310 if (info->type == AARCH64_OPND_IMM_VLSR)
313 0000 SEE AdvSIMD modified immediate
314 0001 (16-UInt(immh:immb))
315 001x (32-UInt(immh:immb))
316 01xx (64-UInt(immh:immb))
317 1xxx (128-UInt(immh:immb)) */
318 imm = (16 << (unsigned)val) - info->imm.value;
322 0000 SEE AdvSIMD modified immediate
323 0001 (UInt(immh:immb)-8)
324 001x (UInt(immh:immb)-16)
325 01xx (UInt(immh:immb)-32)
326 1xxx (UInt(immh:immb)-64) */
327 imm = info->imm.value + (8 << (unsigned)val);
328 insert_fields (code, imm, 0, 2, FLD_immb, FLD_immh);
333 /* Insert fields for e.g. the immediate operands in
334 BFM <Wd>, <Wn>, #<immr>, #<imms>. */
336 aarch64_ins_imm (const aarch64_operand *self, const aarch64_opnd_info *info,
338 const aarch64_inst *inst ATTRIBUTE_UNUSED)
342 imm = info->imm.value;
343 if (operand_need_shift_by_two (self))
345 insert_all_fields (self, code, imm);
349 /* Insert immediate and its shift amount for e.g. the last operand in
350 MOVZ <Wd>, #<imm16>{, LSL #<shift>}. */
352 aarch64_ins_imm_half (const aarch64_operand *self, const aarch64_opnd_info *info,
353 aarch64_insn *code, const aarch64_inst *inst)
356 aarch64_ins_imm (self, info, code, inst);
358 insert_field (FLD_hw, code, info->shifter.amount >> 4, 0);
362 /* Insert cmode and "a:b:c:d:e:f:g:h" fields for e.g. the last operand in
363 MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}. */
365 aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
366 const aarch64_opnd_info *info,
368 const aarch64_inst *inst ATTRIBUTE_UNUSED)
370 enum aarch64_opnd_qualifier opnd0_qualifier = inst->operands[0].qualifier;
371 uint64_t imm = info->imm.value;
372 enum aarch64_modifier_kind kind = info->shifter.kind;
373 int amount = info->shifter.amount;
374 aarch64_field field = {0, 0};
376 /* a:b:c:d:e:f:g:h */
377 if (!info->imm.is_fp && aarch64_get_qualifier_esize (opnd0_qualifier) == 8)
379 /* Either MOVI <Dd>, #<imm>
380 or MOVI <Vd>.2D, #<imm>.
381 <imm> is a 64-bit immediate
382 "aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh",
383 encoded in "a:b:c:d:e:f:g:h". */
384 imm = aarch64_shrink_expanded_imm8 (imm);
385 assert ((int)imm >= 0);
387 insert_fields (code, imm, 0, 2, FLD_defgh, FLD_abc);
389 if (kind == AARCH64_MOD_NONE)
392 /* shift amount partially in cmode */
393 assert (kind == AARCH64_MOD_LSL || kind == AARCH64_MOD_MSL);
394 if (kind == AARCH64_MOD_LSL)
396 /* AARCH64_MOD_LSL: shift zeros. */
397 int esize = aarch64_get_qualifier_esize (opnd0_qualifier);
398 assert (esize == 4 || esize == 2 || esize == 1);
399 /* For 8-bit move immediate, the optional LSL #0 does not require
405 gen_sub_field (FLD_cmode, 1, 2, &field); /* per word */
407 gen_sub_field (FLD_cmode, 1, 1, &field); /* per halfword */
411 /* AARCH64_MOD_MSL: shift ones. */
413 gen_sub_field (FLD_cmode, 0, 1, &field); /* per word */
415 insert_field_2 (&field, code, amount, 0);
420 /* Insert #<fbits> for the immediate operand in fp fix-point instructions,
421 e.g. SCVTF <Dd>, <Wn>, #<fbits>. */
423 aarch64_ins_fbits (const aarch64_operand *self, const aarch64_opnd_info *info,
425 const aarch64_inst *inst ATTRIBUTE_UNUSED)
427 insert_field (self->fields[0], code, 64 - info->imm.value, 0);
431 /* Insert arithmetic immediate for e.g. the last operand in
432 SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}. */
434 aarch64_ins_aimm (const aarch64_operand *self, const aarch64_opnd_info *info,
435 aarch64_insn *code, const aarch64_inst *inst ATTRIBUTE_UNUSED)
438 aarch64_insn value = info->shifter.amount ? 1 : 0;
439 insert_field (self->fields[0], code, value, 0);
440 /* imm12 (unsigned) */
441 insert_field (self->fields[1], code, info->imm.value, 0);
445 /* Insert logical/bitmask immediate for e.g. the last operand in
446 ORR <Wd|WSP>, <Wn>, #<imm>. */
448 aarch64_ins_limm (const aarch64_operand *self, const aarch64_opnd_info *info,
449 aarch64_insn *code, const aarch64_inst *inst ATTRIBUTE_UNUSED)
452 uint64_t imm = info->imm.value;
453 int esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier);
455 if (inst->opcode->op == OP_BIC)
457 if (aarch64_logical_immediate_p (imm, esize, &value) == FALSE)
458 /* The constraint check should have guaranteed this wouldn't happen. */
461 insert_fields (code, value, 0, 3, self->fields[2], self->fields[1],
466 /* Encode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
467 or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */
469 aarch64_ins_ft (const aarch64_operand *self, const aarch64_opnd_info *info,
470 aarch64_insn *code, const aarch64_inst *inst)
472 aarch64_insn value = 0;
474 assert (info->idx == 0);
477 aarch64_ins_regno (self, info, code, inst);
478 if (inst->opcode->iclass == ldstpair_indexed
479 || inst->opcode->iclass == ldstnapair_offs
480 || inst->opcode->iclass == ldstpair_off
481 || inst->opcode->iclass == loadlit)
484 switch (info->qualifier)
486 case AARCH64_OPND_QLF_S_S: value = 0; break;
487 case AARCH64_OPND_QLF_S_D: value = 1; break;
488 case AARCH64_OPND_QLF_S_Q: value = 2; break;
491 insert_field (FLD_ldst_size, code, value, 0);
496 value = aarch64_get_qualifier_standard_value (info->qualifier);
497 insert_fields (code, value, 0, 2, FLD_ldst_size, FLD_opc1);
503 /* Encode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */
505 aarch64_ins_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
506 const aarch64_opnd_info *info, aarch64_insn *code,
507 const aarch64_inst *inst ATTRIBUTE_UNUSED)
510 insert_field (FLD_Rn, code, info->addr.base_regno, 0);
514 /* Encode the address operand for e.g.
515 STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
517 aarch64_ins_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED,
518 const aarch64_opnd_info *info, aarch64_insn *code,
519 const aarch64_inst *inst ATTRIBUTE_UNUSED)
522 enum aarch64_modifier_kind kind = info->shifter.kind;
525 insert_field (FLD_Rn, code, info->addr.base_regno, 0);
527 insert_field (FLD_Rm, code, info->addr.offset.regno, 0);
529 if (kind == AARCH64_MOD_LSL)
530 kind = AARCH64_MOD_UXTX; /* Trick to enable the table-driven. */
531 insert_field (FLD_option, code, aarch64_get_operand_modifier_value (kind), 0);
533 if (info->qualifier != AARCH64_OPND_QLF_S_B)
534 S = info->shifter.amount != 0;
536 /* For STR <Bt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}},
540 Must be #0 if <extend> is explicitly LSL. */
541 S = info->shifter.operator_present && info->shifter.amount_present;
542 insert_field (FLD_S, code, S, 0);
547 /* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>, #<simm>]!. */
549 aarch64_ins_addr_simm (const aarch64_operand *self,
550 const aarch64_opnd_info *info,
552 const aarch64_inst *inst ATTRIBUTE_UNUSED)
557 insert_field (FLD_Rn, code, info->addr.base_regno, 0);
558 /* simm (imm9 or imm7) */
559 imm = info->addr.offset.imm;
560 if (self->fields[0] == FLD_imm7)
561 /* scaled immediate in ld/st pair instructions.. */
562 imm >>= get_logsz (aarch64_get_qualifier_esize (info->qualifier));
563 insert_field (self->fields[0], code, imm, 0);
564 /* pre/post- index */
565 if (info->addr.writeback)
567 assert (inst->opcode->iclass != ldst_unscaled
568 && inst->opcode->iclass != ldstnapair_offs
569 && inst->opcode->iclass != ldstpair_off
570 && inst->opcode->iclass != ldst_unpriv);
571 assert (info->addr.preind != info->addr.postind);
572 if (info->addr.preind)
573 insert_field (self->fields[1], code, 1, 0);
579 /* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<pimm>}]. */
581 aarch64_ins_addr_uimm12 (const aarch64_operand *self,
582 const aarch64_opnd_info *info,
584 const aarch64_inst *inst ATTRIBUTE_UNUSED)
586 int shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier));
589 insert_field (self->fields[0], code, info->addr.base_regno, 0);
591 insert_field (self->fields[1], code,info->addr.offset.imm >> shift, 0);
595 /* Encode the address operand for e.g.
596 LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */
598 aarch64_ins_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED,
599 const aarch64_opnd_info *info, aarch64_insn *code,
600 const aarch64_inst *inst ATTRIBUTE_UNUSED)
603 insert_field (FLD_Rn, code, info->addr.base_regno, 0);
605 if (info->addr.offset.is_reg)
606 insert_field (FLD_Rm, code, info->addr.offset.regno, 0);
608 insert_field (FLD_Rm, code, 0x1f, 0);
612 /* Encode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>. */
614 aarch64_ins_cond (const aarch64_operand *self ATTRIBUTE_UNUSED,
615 const aarch64_opnd_info *info, aarch64_insn *code,
616 const aarch64_inst *inst ATTRIBUTE_UNUSED)
619 insert_field (FLD_cond, code, info->cond->value, 0);
623 /* Encode the system register operand for e.g. MRS <Xt>, <systemreg>. */
625 aarch64_ins_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED,
626 const aarch64_opnd_info *info, aarch64_insn *code,
627 const aarch64_inst *inst ATTRIBUTE_UNUSED)
629 /* op0:op1:CRn:CRm:op2 */
630 insert_fields (code, info->sysreg, inst->opcode->mask, 5,
631 FLD_op2, FLD_CRm, FLD_CRn, FLD_op1, FLD_op0);
635 /* Encode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>. */
637 aarch64_ins_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED,
638 const aarch64_opnd_info *info, aarch64_insn *code,
639 const aarch64_inst *inst ATTRIBUTE_UNUSED)
642 insert_fields (code, info->pstatefield, inst->opcode->mask, 2,
647 /* Encode the system instruction op operand for e.g. AT <at_op>, <Xt>. */
649 aarch64_ins_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
650 const aarch64_opnd_info *info, aarch64_insn *code,
651 const aarch64_inst *inst ATTRIBUTE_UNUSED)
653 /* op1:CRn:CRm:op2 */
654 insert_fields (code, info->sysins_op->value, inst->opcode->mask, 4,
655 FLD_op2, FLD_CRm, FLD_CRn, FLD_op1);
659 /* Encode the memory barrier option operand for e.g. DMB <option>|#<imm>. */
662 aarch64_ins_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED,
663 const aarch64_opnd_info *info, aarch64_insn *code,
664 const aarch64_inst *inst ATTRIBUTE_UNUSED)
667 insert_field (FLD_CRm, code, info->barrier->value, 0);
671 /* Encode the prefetch operation option operand for e.g.
672 PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */
675 aarch64_ins_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED,
676 const aarch64_opnd_info *info, aarch64_insn *code,
677 const aarch64_inst *inst ATTRIBUTE_UNUSED)
680 insert_field (FLD_Rt, code, info->prfop->value, 0);
684 /* Encode the hint number for instructions that alias HINT but take an
688 aarch64_ins_hint (const aarch64_operand *self ATTRIBUTE_UNUSED,
689 const aarch64_opnd_info *info, aarch64_insn *code,
690 const aarch64_inst *inst ATTRIBUTE_UNUSED)
693 insert_fields (code, info->hint_option->value, 0, 2, FLD_op2, FLD_CRm);
697 /* Encode the extended register operand for e.g.
698 STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
700 aarch64_ins_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED,
701 const aarch64_opnd_info *info, aarch64_insn *code,
702 const aarch64_inst *inst ATTRIBUTE_UNUSED)
704 enum aarch64_modifier_kind kind;
707 insert_field (FLD_Rm, code, info->reg.regno, 0);
709 kind = info->shifter.kind;
710 if (kind == AARCH64_MOD_LSL)
711 kind = info->qualifier == AARCH64_OPND_QLF_W
712 ? AARCH64_MOD_UXTW : AARCH64_MOD_UXTX;
713 insert_field (FLD_option, code, aarch64_get_operand_modifier_value (kind), 0);
715 insert_field (FLD_imm3, code, info->shifter.amount, 0);
720 /* Encode the shifted register operand for e.g.
721 SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}. */
723 aarch64_ins_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
724 const aarch64_opnd_info *info, aarch64_insn *code,
725 const aarch64_inst *inst ATTRIBUTE_UNUSED)
728 insert_field (FLD_Rm, code, info->reg.regno, 0);
730 insert_field (FLD_shift, code,
731 aarch64_get_operand_modifier_value (info->shifter.kind), 0);
733 insert_field (FLD_imm6, code, info->shifter.amount, 0);
738 /* Miscellaneous encoding functions. */
740 /* Encode size[0], i.e. bit 22, for
741 e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
744 encode_asimd_fcvt (aarch64_inst *inst)
747 aarch64_field field = {0, 0};
748 enum aarch64_opnd_qualifier qualifier;
750 switch (inst->opcode->op)
754 /* FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
755 qualifier = inst->operands[1].qualifier;
759 /* FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */
760 qualifier = inst->operands[0].qualifier;
765 assert (qualifier == AARCH64_OPND_QLF_V_4S
766 || qualifier == AARCH64_OPND_QLF_V_2D);
767 value = (qualifier == AARCH64_OPND_QLF_V_4S) ? 0 : 1;
768 gen_sub_field (FLD_size, 0, 1, &field);
769 insert_field_2 (&field, &inst->value, value, 0);
772 /* Encode size[0], i.e. bit 22, for
773 e.g. FCVTXN <Vb><d>, <Va><n>. */
776 encode_asisd_fcvtxn (aarch64_inst *inst)
778 aarch64_insn val = 1;
779 aarch64_field field = {0, 0};
780 assert (inst->operands[0].qualifier == AARCH64_OPND_QLF_S_S);
781 gen_sub_field (FLD_size, 0, 1, &field);
782 insert_field_2 (&field, &inst->value, val, 0);
785 /* Encode the 'opc' field for e.g. FCVT <Dd>, <Sn>. */
787 encode_fcvt (aarch64_inst *inst)
790 const aarch64_field field = {15, 2};
793 switch (inst->operands[0].qualifier)
795 case AARCH64_OPND_QLF_S_S: val = 0; break;
796 case AARCH64_OPND_QLF_S_D: val = 1; break;
797 case AARCH64_OPND_QLF_S_H: val = 3; break;
800 insert_field_2 (&field, &inst->value, val, 0);
805 /* Do miscellaneous encodings that are not common enough to be driven by
809 do_misc_encoding (aarch64_inst *inst)
811 switch (inst->opcode->op)
820 encode_asimd_fcvt (inst);
823 encode_asisd_fcvtxn (inst);
829 /* Encode the 'size' and 'Q' field for e.g. SHADD. */
831 encode_sizeq (aarch64_inst *inst)
834 enum aarch64_field_kind kind;
837 /* Get the index of the operand whose information we are going to use
838 to encode the size and Q fields.
839 This is deduced from the possible valid qualifier lists. */
840 idx = aarch64_select_operand_for_sizeq_field_coding (inst->opcode);
841 DEBUG_TRACE ("idx: %d; qualifier: %s", idx,
842 aarch64_get_qualifier_name (inst->operands[idx].qualifier));
843 sizeq = aarch64_get_qualifier_standard_value (inst->operands[idx].qualifier);
845 insert_field (FLD_Q, &inst->value, sizeq & 0x1, inst->opcode->mask);
847 if (inst->opcode->iclass == asisdlse
848 || inst->opcode->iclass == asisdlsep
849 || inst->opcode->iclass == asisdlso
850 || inst->opcode->iclass == asisdlsop)
851 kind = FLD_vldst_size;
854 insert_field (kind, &inst->value, (sizeq >> 1) & 0x3, inst->opcode->mask);
857 /* Opcodes that have fields shared by multiple operands are usually flagged
858 with flags. In this function, we detect such flags and use the
859 information in one of the related operands to do the encoding. The 'one'
860 operand is not any operand but one of the operands that has the enough
861 information for such an encoding. */
864 do_special_encoding (struct aarch64_inst *inst)
867 aarch64_insn value = 0;
869 DEBUG_TRACE ("enter with coding 0x%x", (uint32_t) inst->value);
871 /* Condition for truly conditional executed instructions, e.g. b.cond. */
872 if (inst->opcode->flags & F_COND)
874 insert_field (FLD_cond2, &inst->value, inst->cond->value, 0);
876 if (inst->opcode->flags & F_SF)
878 idx = select_operand_for_sf_field_coding (inst->opcode);
879 value = (inst->operands[idx].qualifier == AARCH64_OPND_QLF_X
880 || inst->operands[idx].qualifier == AARCH64_OPND_QLF_SP)
882 insert_field (FLD_sf, &inst->value, value, 0);
883 if (inst->opcode->flags & F_N)
884 insert_field (FLD_N, &inst->value, value, inst->opcode->mask);
886 if (inst->opcode->flags & F_LSE_SZ)
888 idx = select_operand_for_sf_field_coding (inst->opcode);
889 value = (inst->operands[idx].qualifier == AARCH64_OPND_QLF_X
890 || inst->operands[idx].qualifier == AARCH64_OPND_QLF_SP)
892 insert_field (FLD_lse_sz, &inst->value, value, 0);
894 if (inst->opcode->flags & F_SIZEQ)
896 if (inst->opcode->flags & F_FPTYPE)
898 idx = select_operand_for_fptype_field_coding (inst->opcode);
899 switch (inst->operands[idx].qualifier)
901 case AARCH64_OPND_QLF_S_S: value = 0; break;
902 case AARCH64_OPND_QLF_S_D: value = 1; break;
903 case AARCH64_OPND_QLF_S_H: value = 3; break;
906 insert_field (FLD_type, &inst->value, value, 0);
908 if (inst->opcode->flags & F_SSIZE)
910 enum aarch64_opnd_qualifier qualifier;
911 idx = select_operand_for_scalar_size_field_coding (inst->opcode);
912 qualifier = inst->operands[idx].qualifier;
913 assert (qualifier >= AARCH64_OPND_QLF_S_B
914 && qualifier <= AARCH64_OPND_QLF_S_Q);
915 value = aarch64_get_qualifier_standard_value (qualifier);
916 insert_field (FLD_size, &inst->value, value, inst->opcode->mask);
918 if (inst->opcode->flags & F_T)
920 int num; /* num of consecutive '0's on the right side of imm5<3:0>. */
921 aarch64_field field = {0, 0};
922 enum aarch64_opnd_qualifier qualifier;
925 qualifier = inst->operands[idx].qualifier;
926 assert (aarch64_get_operand_class (inst->opcode->operands[0])
927 == AARCH64_OPND_CLASS_SIMD_REG
928 && qualifier >= AARCH64_OPND_QLF_V_8B
929 && qualifier <= AARCH64_OPND_QLF_V_2D);
940 value = aarch64_get_qualifier_standard_value (qualifier);
941 insert_field (FLD_Q, &inst->value, value & 0x1, inst->opcode->mask);
942 num = (int) value >> 1;
943 assert (num >= 0 && num <= 3);
944 gen_sub_field (FLD_imm5, 0, num + 1, &field);
945 insert_field_2 (&field, &inst->value, 1 << num, inst->opcode->mask);
947 if (inst->opcode->flags & F_GPRSIZE_IN_Q)
949 /* Use Rt to encode in the case of e.g.
950 STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */
951 enum aarch64_opnd_qualifier qualifier;
952 idx = aarch64_operand_index (inst->opcode->operands, AARCH64_OPND_Rt);
954 /* Otherwise use the result operand, which has to be a integer
957 assert (idx == 0 || idx == 1);
958 assert (aarch64_get_operand_class (inst->opcode->operands[idx])
959 == AARCH64_OPND_CLASS_INT_REG);
960 qualifier = inst->operands[idx].qualifier;
961 insert_field (FLD_Q, &inst->value,
962 aarch64_get_qualifier_standard_value (qualifier), 0);
964 if (inst->opcode->flags & F_LDS_SIZE)
966 /* e.g. LDRSB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
967 enum aarch64_opnd_qualifier qualifier;
968 aarch64_field field = {0, 0};
969 assert (aarch64_get_operand_class (inst->opcode->operands[0])
970 == AARCH64_OPND_CLASS_INT_REG);
971 gen_sub_field (FLD_opc, 0, 1, &field);
972 qualifier = inst->operands[0].qualifier;
973 insert_field_2 (&field, &inst->value,
974 1 - aarch64_get_qualifier_standard_value (qualifier), 0);
976 /* Miscellaneous encoding as the last step. */
977 if (inst->opcode->flags & F_MISC)
978 do_misc_encoding (inst);
980 DEBUG_TRACE ("exit with coding 0x%x", (uint32_t) inst->value);
983 /* Converters converting an alias opcode instruction to its real form. */
985 /* ROR <Wd>, <Ws>, #<shift>
987 EXTR <Wd>, <Ws>, <Ws>, #<shift>. */
989 convert_ror_to_extr (aarch64_inst *inst)
991 copy_operand_info (inst, 3, 2);
992 copy_operand_info (inst, 2, 1);
995 /* UXTL<Q> <Vd>.<Ta>, <Vn>.<Tb>
997 USHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #0. */
999 convert_xtl_to_shll (aarch64_inst *inst)
1001 inst->operands[2].qualifier = inst->operands[1].qualifier;
1002 inst->operands[2].imm.value = 0;
1006 LSR <Xd>, <Xn>, #<shift>
1008 UBFM <Xd>, <Xn>, #<shift>, #63. */
1010 convert_sr_to_bfm (aarch64_inst *inst)
1012 inst->operands[3].imm.value =
1013 inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 31 : 63;
1016 /* Convert MOV to ORR. */
1018 convert_mov_to_orr (aarch64_inst *inst)
1020 /* MOV <Vd>.<T>, <Vn>.<T>
1022 ORR <Vd>.<T>, <Vn>.<T>, <Vn>.<T>. */
1023 copy_operand_info (inst, 2, 1);
1026 /* When <imms> >= <immr>, the instruction written:
1027 SBFX <Xd>, <Xn>, #<lsb>, #<width>
1029 SBFM <Xd>, <Xn>, #<lsb>, #(<lsb>+<width>-1). */
1032 convert_bfx_to_bfm (aarch64_inst *inst)
1036 /* Convert the operand. */
1037 lsb = inst->operands[2].imm.value;
1038 width = inst->operands[3].imm.value;
1039 inst->operands[2].imm.value = lsb;
1040 inst->operands[3].imm.value = lsb + width - 1;
1043 /* When <imms> < <immr>, the instruction written:
1044 SBFIZ <Xd>, <Xn>, #<lsb>, #<width>
1046 SBFM <Xd>, <Xn>, #((64-<lsb>)&0x3f), #(<width>-1). */
1049 convert_bfi_to_bfm (aarch64_inst *inst)
1053 /* Convert the operand. */
1054 lsb = inst->operands[2].imm.value;
1055 width = inst->operands[3].imm.value;
1056 if (inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31)
1058 inst->operands[2].imm.value = (32 - lsb) & 0x1f;
1059 inst->operands[3].imm.value = width - 1;
1063 inst->operands[2].imm.value = (64 - lsb) & 0x3f;
1064 inst->operands[3].imm.value = width - 1;
1068 /* The instruction written:
1069 BFC <Xd>, #<lsb>, #<width>
1071 BFM <Xd>, XZR, #((64-<lsb>)&0x3f), #(<width>-1). */
1074 convert_bfc_to_bfm (aarch64_inst *inst)
1079 copy_operand_info (inst, 3, 2);
1080 copy_operand_info (inst, 2, 1);
1081 copy_operand_info (inst, 2, 0);
1082 inst->operands[1].reg.regno = 0x1f;
1084 /* Convert the immedate operand. */
1085 lsb = inst->operands[2].imm.value;
1086 width = inst->operands[3].imm.value;
1087 if (inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31)
1089 inst->operands[2].imm.value = (32 - lsb) & 0x1f;
1090 inst->operands[3].imm.value = width - 1;
1094 inst->operands[2].imm.value = (64 - lsb) & 0x3f;
1095 inst->operands[3].imm.value = width - 1;
1099 /* The instruction written:
1100 LSL <Xd>, <Xn>, #<shift>
1102 UBFM <Xd>, <Xn>, #((64-<shift>)&0x3f), #(63-<shift>). */
1105 convert_lsl_to_ubfm (aarch64_inst *inst)
1107 int64_t shift = inst->operands[2].imm.value;
1109 if (inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31)
1111 inst->operands[2].imm.value = (32 - shift) & 0x1f;
1112 inst->operands[3].imm.value = 31 - shift;
1116 inst->operands[2].imm.value = (64 - shift) & 0x3f;
1117 inst->operands[3].imm.value = 63 - shift;
1121 /* CINC <Wd>, <Wn>, <cond>
1123 CSINC <Wd>, <Wn>, <Wn>, invert(<cond>). */
1126 convert_to_csel (aarch64_inst *inst)
1128 copy_operand_info (inst, 3, 2);
1129 copy_operand_info (inst, 2, 1);
1130 inst->operands[3].cond = get_inverted_cond (inst->operands[3].cond);
1133 /* CSET <Wd>, <cond>
1135 CSINC <Wd>, WZR, WZR, invert(<cond>). */
1138 convert_cset_to_csinc (aarch64_inst *inst)
1140 copy_operand_info (inst, 3, 1);
1141 copy_operand_info (inst, 2, 0);
1142 copy_operand_info (inst, 1, 0);
1143 inst->operands[1].reg.regno = 0x1f;
1144 inst->operands[2].reg.regno = 0x1f;
1145 inst->operands[3].cond = get_inverted_cond (inst->operands[3].cond);
1150 MOVZ <Wd>, #<imm16>, LSL #<shift>. */
1153 convert_mov_to_movewide (aarch64_inst *inst)
1156 uint32_t shift_amount;
1159 switch (inst->opcode->op)
1161 case OP_MOV_IMM_WIDE:
1162 value = inst->operands[1].imm.value;
1164 case OP_MOV_IMM_WIDEN:
1165 value = ~inst->operands[1].imm.value;
1170 inst->operands[1].type = AARCH64_OPND_HALF;
1171 is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W;
1172 if (! aarch64_wide_constant_p (value, is32, &shift_amount))
1173 /* The constraint check should have guaranteed this wouldn't happen. */
1175 value >>= shift_amount;
1177 inst->operands[1].imm.value = value;
1178 inst->operands[1].shifter.kind = AARCH64_MOD_LSL;
1179 inst->operands[1].shifter.amount = shift_amount;
1184 ORR <Wd>, WZR, #<imm>. */
1187 convert_mov_to_movebitmask (aarch64_inst *inst)
1189 copy_operand_info (inst, 2, 1);
1190 inst->operands[1].reg.regno = 0x1f;
1191 inst->operands[1].skip = 0;
1194 /* Some alias opcodes are assembled by being converted to their real-form. */
1197 convert_to_real (aarch64_inst *inst, const aarch64_opcode *real)
1199 const aarch64_opcode *alias = inst->opcode;
1201 if ((alias->flags & F_CONV) == 0)
1202 goto convert_to_real_return;
1208 convert_sr_to_bfm (inst);
1211 convert_lsl_to_ubfm (inst);
1216 convert_to_csel (inst);
1220 convert_cset_to_csinc (inst);
1225 convert_bfx_to_bfm (inst);
1230 convert_bfi_to_bfm (inst);
1233 convert_bfc_to_bfm (inst);
1236 convert_mov_to_orr (inst);
1238 case OP_MOV_IMM_WIDE:
1239 case OP_MOV_IMM_WIDEN:
1240 convert_mov_to_movewide (inst);
1242 case OP_MOV_IMM_LOG:
1243 convert_mov_to_movebitmask (inst);
1246 convert_ror_to_extr (inst);
1252 convert_xtl_to_shll (inst);
1258 convert_to_real_return:
1259 aarch64_replace_opcode (inst, real);
1262 /* Encode *INST_ORI of the opcode code OPCODE.
1263 Return the encoded result in *CODE and if QLF_SEQ is not NULL, return the
1264 matched operand qualifier sequence in *QLF_SEQ. */
1267 aarch64_opcode_encode (const aarch64_opcode *opcode,
1268 const aarch64_inst *inst_ori, aarch64_insn *code,
1269 aarch64_opnd_qualifier_t *qlf_seq,
1270 aarch64_operand_error *mismatch_detail)
1273 const aarch64_opcode *aliased;
1274 aarch64_inst copy, *inst;
1276 DEBUG_TRACE ("enter with %s", opcode->name);
1278 /* Create a copy of *INST_ORI, so that we can do any change we want. */
1282 assert (inst->opcode == NULL || inst->opcode == opcode);
1283 if (inst->opcode == NULL)
1284 inst->opcode = opcode;
1286 /* Constrain the operands.
1287 After passing this, the encoding is guaranteed to succeed. */
1288 if (aarch64_match_operands_constraint (inst, mismatch_detail) == 0)
1290 DEBUG_TRACE ("FAIL since operand constraint not met");
1294 /* Get the base value.
1295 Note: this has to be before the aliasing handling below in order to
1296 get the base value from the alias opcode before we move on to the
1297 aliased opcode for encoding. */
1298 inst->value = opcode->opcode;
1300 /* No need to do anything else if the opcode does not have any operand. */
1301 if (aarch64_num_of_operands (opcode) == 0)
1304 /* Assign operand indexes and check types. Also put the matched
1305 operand qualifiers in *QLF_SEQ to return. */
1306 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
1308 assert (opcode->operands[i] == inst->operands[i].type);
1309 inst->operands[i].idx = i;
1310 if (qlf_seq != NULL)
1311 *qlf_seq = inst->operands[i].qualifier;
1314 aliased = aarch64_find_real_opcode (opcode);
1315 /* If the opcode is an alias and it does not ask for direct encoding by
1316 itself, the instruction will be transformed to the form of real opcode
1317 and the encoding will be carried out using the rules for the aliased
1319 if (aliased != NULL && (opcode->flags & F_CONV))
1321 DEBUG_TRACE ("real opcode '%s' has been found for the alias %s",
1322 aliased->name, opcode->name);
1323 /* Convert the operands to the form of the real opcode. */
1324 convert_to_real (inst, aliased);
1328 aarch64_opnd_info *info = inst->operands;
1330 /* Call the inserter of each operand. */
1331 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i, ++info)
1333 const aarch64_operand *opnd;
1334 enum aarch64_opnd type = opcode->operands[i];
1335 if (type == AARCH64_OPND_NIL)
1339 DEBUG_TRACE ("skip the incomplete operand %d", i);
1342 opnd = &aarch64_operands[type];
1343 if (operand_has_inserter (opnd))
1344 aarch64_insert_operand (opnd, info, &inst->value, inst);
1347 /* Call opcode encoders indicated by flags. */
1348 if (opcode_has_special_coder (opcode))
1349 do_special_encoding (inst);
1352 DEBUG_TRACE ("exit with %s", opcode->name);
1354 *code = inst->value;