1 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
3 * arc-dis.c (print_hex): New variable.
4 (parse_option): Check for hex option.
5 (print_insn_arc): Use hexadecimal representation for short
6 immediate values when requested.
7 (print_arc_disassembler_options): Add hex option to the list.
9 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
11 * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
12 (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
13 (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
14 (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
15 (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
16 (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
17 (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
18 (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
19 (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
20 (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
21 (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
22 (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
23 (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
24 (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
25 (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
26 (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
27 (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
28 (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
29 (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
31 (prealloc, prefetch*): Place them before ld instruction.
32 * arc-opc.c (skip_this_opcode): Add ARITH class.
34 2017-10-25 Alan Modra <amodra@gmail.com>
37 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
38 (cr16_words, cr16_allWords, processing_argument_number): Likewise.
39 (imm4flag, size_changed): Likewise.
40 * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
41 (words, allWords, processing_argument_number): Likewise.
42 (cst4flag, size_changed): Likewise.
43 * crx-opc.c (crx_cst4_map): Rename from cst4_map.
44 (crx_cst4_maps): Rename from cst4_maps.
45 (crx_no_op_insn): Rename from no_op_insn.
47 2017-10-24 Andrew Waterman <andrew@sifive.com>
49 * riscv-opc.c (match_c_addi16sp) : New function.
50 (match_c_addi4spn): New function.
51 (match_c_lui): Don't allow 0-immediate encodings.
52 (riscv_opcodes) <addi>: Use the above functions.
54 <c.addi4spn>: Likewise.
55 <c.addi16sp>: Likewise.
57 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
59 * i386-init.h: Regenerate
60 * i386-tbl.h: Likewise
62 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
64 * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
65 (enum): Add EVEX_W_0F3854_P_2.
66 * i386-dis-evex.h (evex_table): Updated.
67 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
68 CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
69 (cpu_flags): Add CpuAVX512_BITALG.
70 * i386-opc.h (enum): Add CpuAVX512_BITALG.
71 (i386_cpu_flags): Add cpuavx512_bitalg..
72 * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
73 * i386-init.h: Regenerate.
74 * i386-tbl.h: Likewise.
76 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
78 * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
79 * i386-dis-evex.h (evex_table): Updated.
80 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
81 CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
82 (cpu_flags): Add CpuAVX512_VNNI.
83 * i386-opc.h (enum): Add CpuAVX512_VNNI.
84 (i386_cpu_flags): Add cpuavx512_vnni.
85 * i386-opc.tbl Add Intel AVX512_VNNI instructions.
86 * i386-init.h: Regenerate.
87 * i386-tbl.h: Likewise.
89 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
91 * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
92 (enum): Remove VEX_LEN_0F3A44_P_2.
93 (vex_len_table): Ditto.
94 (enum): Remove VEX_W_0F3A44_P_2.
96 (prefix_table): Adjust instructions (see prefixes above).
97 * i386-dis-evex.h (evex_table):
98 Add new instructions (see prefixes above).
99 * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
100 (bitfield_cpu_flags): Ditto.
101 * i386-opc.h (enum): Ditto.
102 (i386_cpu_flags): Ditto.
103 (CpuUnused): Comment out to avoid zero-width field problem.
104 * i386-opc.tbl (vpclmulqdq): New instruction.
105 * i386-init.h: Regenerate.
108 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
110 * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
111 PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
112 (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
113 VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
114 (vex_len_table): Ditto.
115 (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
116 VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
117 (vew_w_table): Ditto.
118 (prefix_table): Adjust instructions (see prefixes above).
119 * i386-dis-evex.h (evex_table):
120 Add new instructions (see prefixes above).
121 * i386-gen.c (cpu_flag_init): Add VAES.
122 (bitfield_cpu_flags): Ditto.
123 * i386-opc.h (enum): Ditto.
124 (i386_cpu_flags): Ditto.
125 * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
126 * i386-init.h: Regenerate.
129 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
131 * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
132 PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
133 PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
134 (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
135 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
136 (prefix_table): Updated (see prefixes above).
137 (three_byte_table): Likewise.
138 (vex_w_table): Likewise.
139 * i386-dis-evex.h: Likewise.
140 * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
141 (cpu_flags): Add CpuGFNI.
142 * i386-opc.h (enum): Add CpuGFNI.
143 (i386_cpu_flags): Add cpugfni.
144 * i386-opc.tbl: Add Intel GFNI instructions.
145 * i386-init.h: Regenerate.
146 * i386-tbl.h: Likewise.
148 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
150 * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
151 Define EXbScalar and EXwScalar for OP_EX.
152 (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
153 PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
154 PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
155 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
156 (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
157 EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
158 EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
159 EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
160 (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
161 (OP_E_memory): Likewise.
162 * i386-dis-evex.h: Updated.
163 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
164 CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
165 (cpu_flags): Add CpuAVX512_VBMI2.
166 * i386-opc.h (enum): Add CpuAVX512_VBMI2.
167 (i386_cpu_flags): Add cpuavx512_vbmi2.
168 * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
169 * i386-init.h: Regenerate.
170 * i386-tbl.h: Likewise.
172 2017-10-18 Eric Botcazou <ebotcazou@adacore.com>
174 * visium-dis.c (disassem_class1) <case 0>: Print the operands.
176 2017-10-12 James Bowman <james.bowman@ftdichip.com>
178 * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
179 * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
180 K15. Add jmpix pattern.
182 2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
184 * s390-opc.txt (prno, tpei, irbm): New instructions added.
186 2017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
188 * s390-opc.c (INSTR_SI_RD): New macro.
189 (INSTR_S_RD): Adjust example instruction.
190 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
193 2017-10-01 Alexander Fedotov <alfedotov@gmail.com>
195 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
196 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
197 VLE multimple load/store instructions. Old e_ldm* variants are
199 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
201 2017-09-27 Nick Clifton <nickc@redhat.com>
204 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
205 names for the fmv.x.s and fmv.s.x instructions respectively.
207 2017-09-26 do <do@nerilex.org>
210 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
211 be used on CPUs that have emacs support.
213 2017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
215 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
217 2017-09-09 Kamil Rytarowski <n54@gmx.com>
219 * nds32-asm.c: Rename __BIT() to N32_BIT().
220 * nds32-asm.h: Likewise.
221 * nds32-dis.c: Likewise.
223 2017-09-09 H.J. Lu <hongjiu.lu@intel.com>
225 * i386-dis.c (last_active_prefix): Removed.
226 (ckprefix): Don't set last_active_prefix.
227 (NOTRACK_Fixup): Don't check last_active_prefix.
229 2017-08-31 Nick Clifton <nickc@redhat.com>
231 * po/fr.po: Updated French translation.
233 2017-08-31 James Bowman <james.bowman@ftdichip.com>
235 * ft32-dis.c (print_insn_ft32): Correct display of non-address
238 2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
239 Edmar Wienskoski <edmar.wienskoski@nxp.com>
241 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
242 PPC_OPCODE_EFS2 flag to "e200z4" entry.
243 New entries efs2 and spe2.
244 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
245 (SPE2_OPCD_SEGS): New macro.
246 (spe2_opcd_indices): New.
247 (disassemble_init_powerpc): Handle SPE2 opcodes.
248 (lookup_spe2): New function.
249 (print_insn_powerpc): call lookup_spe2.
250 * ppc-opc.c (insert_evuimm1_ex0): New function.
251 (extract_evuimm1_ex0): Likewise.
252 (insert_evuimm_lt8): Likewise.
253 (extract_evuimm_lt8): Likewise.
254 (insert_off_spe2): Likewise.
255 (extract_off_spe2): Likewise.
256 (insert_Ddd): Likewise.
257 (extract_Ddd): Likewise.
259 (EVUIMM_LT8): Likewise.
260 (EVUIMM_LT16): Adjust.
262 (EVUIMM_1): Likewise.
263 (EVUIMM_1_EX0): Likewise.
266 (VX_OFF_SPE2): Likewise.
269 (VX_MASK_DDD): New mask.
271 (VX_RA_CONST): New macro.
272 (VX_RA_CONST_MASK): Likewise.
273 (VX_RB_CONST): Likewise.
274 (VX_RB_CONST_MASK): Likewise.
275 (VX_OFF_SPE2_MASK): Likewise.
276 (VX_SPE_CRFD): Likewise.
277 (VX_SPE_CRFD_MASK VX): Likewise.
278 (VX_SPE2_CLR): Likewise.
279 (VX_SPE2_CLR_MASK): Likewise.
280 (VX_SPE2_SPLATB): Likewise.
281 (VX_SPE2_SPLATB_MASK): Likewise.
282 (VX_SPE2_OCTET): Likewise.
283 (VX_SPE2_OCTET_MASK): Likewise.
284 (VX_SPE2_DDHH): Likewise.
285 (VX_SPE2_DDHH_MASK): Likewise.
286 (VX_SPE2_HH): Likewise.
287 (VX_SPE2_HH_MASK): Likewise.
288 (VX_SPE2_EVMAR): Likewise.
289 (VX_SPE2_EVMAR_MASK): Likewise.
292 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
293 (powerpc_macros): Map old SPE instructions have new names
294 with the same opcodes. Add SPE2 instructions which just are
296 (spe2_opcodes): Add SPE2 opcodes.
298 2017-08-23 Alan Modra <amodra@gmail.com>
300 * ppc-opc.c: Formatting and comment fixes. Move insert and
301 extract functions earlier, deleting forward declarations.
302 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
305 2017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
307 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
309 2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
310 Edmar Wienskoski <edmar.wienskoski@nxp.com>
312 * ppc-opc.c (insert_evuimm2_ex0): New function.
313 (extract_evuimm2_ex0): Likewise.
314 (insert_evuimm4_ex0): Likewise.
315 (extract_evuimm4_ex0): Likewise.
316 (insert_evuimm8_ex0): Likewise.
317 (extract_evuimm8_ex0): Likewise.
318 (insert_evuimm_lt16): Likewise.
319 (extract_evuimm_lt16): Likewise.
320 (insert_rD_rS_even): Likewise.
321 (extract_rD_rS_even): Likewise.
322 (insert_off_lsp): Likewise.
323 (extract_off_lsp): Likewise.
324 (RD_EVEN): New operand.
327 (EVUIMM_LT16): New operand.
329 (EVUIMM_2_EX0): New operand.
331 (EVUIMM_4_EX0): New operand.
333 (EVUIMM_8_EX0): New operand.
335 (VX_OFF): New operand.
337 (VX_LSP_MASK): Likewise.
338 (VX_LSP_OFF_MASK): Likewise.
339 (PPC_OPCODE_LSP): Likewise.
340 (vle_opcodes): Add LSP opcodes.
341 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
343 2017-08-09 Jiong Wang <jiong.wang@arm.com>
345 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
346 register operands in CRC instructions.
347 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
350 2017-08-07 H.J. Lu <hongjiu.lu@intel.com>
352 * disassemble.c (disassembler): Mark big and mach with
355 2017-08-07 Maciej W. Rozycki <macro@imgtec.com>
357 * disassemble.c (disassembler): Remove arch/mach/endian
360 2017-07-25 Nick Clifton <nickc@redhat.com>
363 * arc-opc.c (insert_rhv2): Use lower case first letter in error
365 (insert_r0): Likewise.
366 (insert_r1): Likewise.
367 (insert_r2): Likewise.
368 (insert_r3): Likewise.
369 (insert_sp): Likewise.
370 (insert_gp): Likewise.
371 (insert_pcl): Likewise.
372 (insert_blink): Likewise.
373 (insert_ilink1): Likewise.
374 (insert_ilink2): Likewise.
375 (insert_ras): Likewise.
376 (insert_rbs): Likewise.
377 (insert_rcs): Likewise.
378 (insert_simm3s): Likewise.
379 (insert_rrange): Likewise.
380 (insert_r13el): Likewise.
381 (insert_fpel): Likewise.
382 (insert_blinkel): Likewise.
383 (insert_pclel): Likewise.
384 (insert_nps_bitop_size_2b): Likewise.
385 (insert_nps_imm_offset): Likewise.
386 (insert_nps_imm_entry): Likewise.
387 (insert_nps_size_16bit): Likewise.
388 (insert_nps_##NAME##_pos): Likewise.
389 (insert_nps_##NAME): Likewise.
390 (insert_nps_bitop_ins_ext): Likewise.
391 (insert_nps_##NAME): Likewise.
392 (insert_nps_min_hofs): Likewise.
393 (insert_nps_##NAME): Likewise.
394 (insert_nps_rbdouble_64): Likewise.
395 (insert_nps_misc_imm_offset): Likewise.
396 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
399 2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
400 Jiong Wang <jiong.wang@arm.com>
402 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
404 * aarch64-dis-2.c: Regenerated.
406 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
408 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
411 2017-07-20 Nick Clifton <nickc@redhat.com>
413 * po/de.po: Updated German translation.
415 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
417 * arc-regs.h (sec_stat): New aux register.
418 (aux_kernel_sp): Likewise.
419 (aux_sec_u_sp): Likewise.
420 (aux_sec_k_sp): Likewise.
421 (sec_vecbase_build): Likewise.
422 (nsc_table_top): Likewise.
423 (nsc_table_base): Likewise.
424 (ersec_stat): Likewise.
425 (aux_sec_except): Likewise.
427 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
429 * arc-opc.c (extract_uimm12_20): New function.
430 (UIMM12_20): New operand.
432 * arc-tbl.h (sjli): Add new instruction.
434 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
435 John Eric Martin <John.Martin@emmicro-us.com>
437 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
438 (UIMM3_23): Adjust accordingly.
439 * arc-regs.h: Add/correct jli_base register.
440 * arc-tbl.h (jli_s): Likewise.
442 2017-07-18 Nick Clifton <nickc@redhat.com>
445 * aarch64-opc.c: Fix spelling typos.
446 * i386-dis.c: Likewise.
448 2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
450 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
451 max_addr_offset and octets variables to size_t.
453 2017-07-12 Alan Modra <amodra@gmail.com>
455 * po/da.po: Update from translationproject.org/latest/opcodes/.
456 * po/de.po: Likewise.
457 * po/es.po: Likewise.
458 * po/fi.po: Likewise.
459 * po/fr.po: Likewise.
460 * po/id.po: Likewise.
461 * po/it.po: Likewise.
462 * po/nl.po: Likewise.
463 * po/pt_BR.po: Likewise.
464 * po/ro.po: Likewise.
465 * po/sv.po: Likewise.
466 * po/tr.po: Likewise.
467 * po/uk.po: Likewise.
468 * po/vi.po: Likewise.
469 * po/zh_CN.po: Likewise.
471 2017-07-11 Yao Qi <yao.qi@linaro.org>
472 Alan Modra <amodra@gmail.com>
474 * cgen.sh: Mark generated files read-only.
475 * epiphany-asm.c: Regenerate.
476 * epiphany-desc.c: Regenerate.
477 * epiphany-desc.h: Regenerate.
478 * epiphany-dis.c: Regenerate.
479 * epiphany-ibld.c: Regenerate.
480 * epiphany-opc.c: Regenerate.
481 * epiphany-opc.h: Regenerate.
482 * fr30-asm.c: Regenerate.
483 * fr30-desc.c: Regenerate.
484 * fr30-desc.h: Regenerate.
485 * fr30-dis.c: Regenerate.
486 * fr30-ibld.c: Regenerate.
487 * fr30-opc.c: Regenerate.
488 * fr30-opc.h: Regenerate.
489 * frv-asm.c: Regenerate.
490 * frv-desc.c: Regenerate.
491 * frv-desc.h: Regenerate.
492 * frv-dis.c: Regenerate.
493 * frv-ibld.c: Regenerate.
494 * frv-opc.c: Regenerate.
495 * frv-opc.h: Regenerate.
496 * ip2k-asm.c: Regenerate.
497 * ip2k-desc.c: Regenerate.
498 * ip2k-desc.h: Regenerate.
499 * ip2k-dis.c: Regenerate.
500 * ip2k-ibld.c: Regenerate.
501 * ip2k-opc.c: Regenerate.
502 * ip2k-opc.h: Regenerate.
503 * iq2000-asm.c: Regenerate.
504 * iq2000-desc.c: Regenerate.
505 * iq2000-desc.h: Regenerate.
506 * iq2000-dis.c: Regenerate.
507 * iq2000-ibld.c: Regenerate.
508 * iq2000-opc.c: Regenerate.
509 * iq2000-opc.h: Regenerate.
510 * lm32-asm.c: Regenerate.
511 * lm32-desc.c: Regenerate.
512 * lm32-desc.h: Regenerate.
513 * lm32-dis.c: Regenerate.
514 * lm32-ibld.c: Regenerate.
515 * lm32-opc.c: Regenerate.
516 * lm32-opc.h: Regenerate.
517 * lm32-opinst.c: Regenerate.
518 * m32c-asm.c: Regenerate.
519 * m32c-desc.c: Regenerate.
520 * m32c-desc.h: Regenerate.
521 * m32c-dis.c: Regenerate.
522 * m32c-ibld.c: Regenerate.
523 * m32c-opc.c: Regenerate.
524 * m32c-opc.h: Regenerate.
525 * m32r-asm.c: Regenerate.
526 * m32r-desc.c: Regenerate.
527 * m32r-desc.h: Regenerate.
528 * m32r-dis.c: Regenerate.
529 * m32r-ibld.c: Regenerate.
530 * m32r-opc.c: Regenerate.
531 * m32r-opc.h: Regenerate.
532 * m32r-opinst.c: Regenerate.
533 * mep-asm.c: Regenerate.
534 * mep-desc.c: Regenerate.
535 * mep-desc.h: Regenerate.
536 * mep-dis.c: Regenerate.
537 * mep-ibld.c: Regenerate.
538 * mep-opc.c: Regenerate.
539 * mep-opc.h: Regenerate.
540 * mt-asm.c: Regenerate.
541 * mt-desc.c: Regenerate.
542 * mt-desc.h: Regenerate.
543 * mt-dis.c: Regenerate.
544 * mt-ibld.c: Regenerate.
545 * mt-opc.c: Regenerate.
546 * mt-opc.h: Regenerate.
547 * or1k-asm.c: Regenerate.
548 * or1k-desc.c: Regenerate.
549 * or1k-desc.h: Regenerate.
550 * or1k-dis.c: Regenerate.
551 * or1k-ibld.c: Regenerate.
552 * or1k-opc.c: Regenerate.
553 * or1k-opc.h: Regenerate.
554 * or1k-opinst.c: Regenerate.
555 * xc16x-asm.c: Regenerate.
556 * xc16x-desc.c: Regenerate.
557 * xc16x-desc.h: Regenerate.
558 * xc16x-dis.c: Regenerate.
559 * xc16x-ibld.c: Regenerate.
560 * xc16x-opc.c: Regenerate.
561 * xc16x-opc.h: Regenerate.
562 * xstormy16-asm.c: Regenerate.
563 * xstormy16-desc.c: Regenerate.
564 * xstormy16-desc.h: Regenerate.
565 * xstormy16-dis.c: Regenerate.
566 * xstormy16-ibld.c: Regenerate.
567 * xstormy16-opc.c: Regenerate.
568 * xstormy16-opc.h: Regenerate.
570 2017-07-07 Alan Modra <amodra@gmail.com>
572 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
573 * m32c-dis.c: Regenerate.
574 * mep-dis.c: Regenerate.
576 2017-07-05 Borislav Petkov <bp@suse.de>
578 * i386-dis.c: Enable ModRM.reg /6 aliases.
580 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
582 * opcodes/arm-dis.c: Support MVFR2 in disassembly
585 2017-07-04 Tristan Gingold <gingold@adacore.com>
587 * configure: Regenerate.
589 2017-07-03 Tristan Gingold <gingold@adacore.com>
591 * po/opcodes.pot: Regenerate.
593 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
595 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
596 entries to the MSA ASE instruction block.
598 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
599 Maciej W. Rozycki <macro@imgtec.com>
601 * micromips-opc.c (XPA, XPAVZ): New macros.
602 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
605 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
606 Maciej W. Rozycki <macro@imgtec.com>
608 * micromips-opc.c (I36): New macro.
609 (micromips_opcodes): Add "eretnc".
611 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
612 Andrew Bennett <andrew.bennett@imgtec.com>
614 * mips-dis.c (mips_calculate_combination_ases): Handle the
616 (parse_mips_ase_option): New function.
617 (parse_mips_dis_option): Factor out ASE option handling to the
618 new function. Call `mips_calculate_combination_ases'.
619 * mips-opc.c (XPAVZ): New macro.
620 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
621 "mfhgc0", "mthc0" and "mthgc0".
623 2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
625 * mips-dis.c (mips_calculate_combination_ases): New function.
626 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
627 calculation to the new function.
628 (set_default_mips_dis_options): Call the new function.
630 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
632 * arc-dis.c (parse_disassembler_options): Use
633 FOR_EACH_DISASSEMBLER_OPTION.
635 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
637 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
638 disassembler option strings.
639 (parse_cpu_option): Likewise.
641 2017-06-28 Tamar Christina <tamar.christina@arm.com>
643 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
644 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
645 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
646 (aarch64_feature_dotprod, DOT_INSN): New.
648 * aarch64-dis-2.c: Regenerated.
650 2017-06-28 Jiong Wang <jiong.wang@arm.com>
652 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
654 2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
655 Matthew Fortune <matthew.fortune@imgtec.com>
656 Andrew Bennett <andrew.bennett@imgtec.com>
658 * mips-formats.h (INT_BIAS): New macro.
659 (INT_ADJ): Redefine in INT_BIAS terms.
660 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
661 (mips_print_save_restore): New function.
662 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
663 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
665 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
666 (print_mips16_insn_arg): Call `mips_print_save_restore' for
667 OP_SAVE_RESTORE_LIST handling, factored out from here.
668 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
669 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
670 (mips_builtin_opcodes): Add "restore" and "save" entries.
671 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
673 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
675 2017-06-23 Andrew Waterman <andrew@sifive.com>
677 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
678 alias; do not mark SLTI instruction as an alias.
680 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
682 * i386-dis.c (RM_0FAE_REG_5): Removed.
683 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
684 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
685 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
686 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
687 PREFIX_MOD_3_0F01_REG_5_RM_0.
688 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
689 PREFIX_MOD_3_0FAE_REG_5.
690 (mod_table): Update MOD_0FAE_REG_5.
691 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
692 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
693 * i386-tbl.h: Regenerated.
695 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
697 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
698 * i386-opc.tbl: Likewise.
699 * i386-tbl.h: Regenerated.
701 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
703 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
705 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
708 2017-06-19 Nick Clifton <nickc@redhat.com>
711 * score-dis.c (score_opcodes): Add sentinel.
713 2017-06-16 Alan Modra <amodra@gmail.com>
715 * rx-decode.c: Regenerate.
717 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
720 * i386-dis.c (OP_E_register): Check valid bnd register.
723 2017-06-15 Nick Clifton <nickc@redhat.com>
726 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
729 2017-06-15 Nick Clifton <nickc@redhat.com>
732 * rl78-decode.opc (OP_BUF_LEN): Define.
733 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
734 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
736 * rl78-decode.c: Regenerate.
738 2017-06-15 Nick Clifton <nickc@redhat.com>
741 * bfin-dis.c (gregs): Clip index to prevent overflow.
746 2017-06-14 Nick Clifton <nickc@redhat.com>
749 * score7-dis.c (score_opcodes): Add sentinel.
751 2017-06-14 Yao Qi <yao.qi@linaro.org>
753 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
754 * arm-dis.c: Likewise.
755 * ia64-dis.c: Likewise.
756 * mips-dis.c: Likewise.
757 * spu-dis.c: Likewise.
758 * disassemble.h (print_insn_aarch64): New declaration, moved from
760 (print_insn_big_arm, print_insn_big_mips): Likewise.
761 (print_insn_i386, print_insn_ia64): Likewise.
762 (print_insn_little_arm, print_insn_little_mips): Likewise.
764 2017-06-14 Nick Clifton <nickc@redhat.com>
767 * rx-decode.opc: Include libiberty.h
768 (GET_SCALE): New macro - validates access to SCALE array.
769 (GET_PSCALE): New macro - validates access to PSCALE array.
770 (DIs, SIs, S2Is, rx_disp): Use new macros.
771 * rx-decode.c: Regenerate.
773 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
775 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
777 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
779 * arc-dis.c (enforced_isa_mask): Declare.
780 (cpu_types): Likewise.
781 (parse_cpu_option): New function.
782 (parse_disassembler_options): Use it.
783 (print_insn_arc): Use enforced_isa_mask.
784 (print_arc_disassembler_options): Document new options.
786 2017-05-24 Yao Qi <yao.qi@linaro.org>
788 * alpha-dis.c: Include disassemble.h, don't include
790 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
791 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
792 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
793 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
794 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
795 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
796 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
797 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
798 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
799 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
800 * moxie-dis.c, msp430-dis.c, mt-dis.c:
801 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
802 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
803 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
804 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
805 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
806 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
807 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
808 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
809 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
810 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
811 * z80-dis.c, z8k-dis.c: Likewise.
812 * disassemble.h: New file.
814 2017-05-24 Yao Qi <yao.qi@linaro.org>
816 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
817 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
819 2017-05-24 Yao Qi <yao.qi@linaro.org>
821 * disassemble.c (disassembler): Add arguments a, big and mach.
824 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
826 * i386-dis.c (NOTRACK_Fixup): New.
828 (NOTRACK_PREFIX): Likewise.
829 (last_active_prefix): Likewise.
830 (reg_table): Use NOTRACK on indirect call and jmp.
831 (ckprefix): Set last_active_prefix.
832 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
833 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
834 * i386-opc.h (NoTrackPrefixOk): New.
835 (i386_opcode_modifier): Add notrackprefixok.
836 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
838 * i386-tbl.h: Regenerated.
840 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
842 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
844 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
846 (print_insn_sparc): Handle new operand types.
847 * sparc-opc.c (MASK_M8): Define.
849 (v6notlet): Likewise.
860 (v9andleon): Likewise.
863 (HWS2_VM8): Likewise.
864 (sparc_opcode_archs): Add entry for "m8".
865 (sparc_opcodes): Add OSA2017 and M8 instructions
866 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
868 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
869 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
870 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
871 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
872 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
873 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
874 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
875 ASI_CORE_SELECT_COMMIT_NHT.
877 2017-05-18 Alan Modra <amodra@gmail.com>
879 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
880 * aarch64-dis.c: Likewise.
881 * aarch64-gen.c: Likewise.
882 * aarch64-opc.c: Likewise.
884 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
885 Matthew Fortune <matthew.fortune@imgtec.com>
887 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
888 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
889 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
890 (print_insn_arg) <OP_REG28>: Add handler.
891 (validate_insn_args) <OP_REG28>: Handle.
892 (print_mips16_insn_arg): Handle MIPS16 instructions that require
893 32-bit encoding and 9-bit immediates.
894 (print_insn_mips16): Handle MIPS16 instructions that require
895 32-bit encoding and MFC0/MTC0 operand decoding.
896 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
897 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
898 (RD_C0, WR_C0, E2, E2MT): New macros.
899 (mips16_opcodes): Add entries for MIPS16e2 instructions:
900 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
901 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
902 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
903 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
904 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
905 instructions, "swl", "swr", "sync" and its "sync_acquire",
906 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
907 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
908 regular/extended entries for original MIPS16 ISA revision
909 instructions whose extended forms are subdecoded in the MIPS16e2
910 ISA revision: "li", "sll" and "srl".
912 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
914 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
915 reference in CP0 move operand decoding.
917 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
919 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
921 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
923 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
925 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
926 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
927 "sync_rmb" and "sync_wmb" as aliases.
928 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
929 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
931 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
933 * arc-dis.c (parse_option): Update quarkse_em option..
934 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
936 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
938 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
940 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
942 2017-05-01 Michael Clark <michaeljclark@mac.com>
944 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
947 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
949 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
950 and branches and not synthetic data instructions.
952 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
954 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
956 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
958 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
959 * arc-opc.c (insert_r13el): New function.
961 * arc-tbl.h: Add new enter/leave variants.
963 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
965 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
967 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
969 * mips-dis.c (print_mips_disassembler_options): Add
972 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
974 * mips16-opc.c (AL): New macro.
975 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
976 of "ld" and "lw" as aliases.
978 2017-04-24 Tamar Christina <tamar.christina@arm.com>
980 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
983 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
984 Alan Modra <amodra@gmail.com>
986 * ppc-opc.c (ELEV): Define.
987 (vle_opcodes): Add se_rfgi and e_sc.
988 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
991 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
993 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
995 2017-04-21 Nick Clifton <nickc@redhat.com>
998 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1001 2017-04-13 Alan Modra <amodra@gmail.com>
1003 * epiphany-desc.c: Regenerate.
1004 * fr30-desc.c: Regenerate.
1005 * frv-desc.c: Regenerate.
1006 * ip2k-desc.c: Regenerate.
1007 * iq2000-desc.c: Regenerate.
1008 * lm32-desc.c: Regenerate.
1009 * m32c-desc.c: Regenerate.
1010 * m32r-desc.c: Regenerate.
1011 * mep-desc.c: Regenerate.
1012 * mt-desc.c: Regenerate.
1013 * or1k-desc.c: Regenerate.
1014 * xc16x-desc.c: Regenerate.
1015 * xstormy16-desc.c: Regenerate.
1017 2017-04-11 Alan Modra <amodra@gmail.com>
1019 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1020 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
1021 PPC_OPCODE_TMR for e6500.
1022 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1023 (PPCVEC3): Define as PPC_OPCODE_POWER9.
1024 (PPCVSX2): Define as PPC_OPCODE_POWER8.
1025 (PPCVSX3): Define as PPC_OPCODE_POWER9.
1026 (PPCHTM): Define as PPC_OPCODE_POWER8.
1027 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1029 2017-04-10 Alan Modra <amodra@gmail.com>
1031 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1032 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1033 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1034 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1036 2017-04-09 Pip Cet <pipcet@gmail.com>
1038 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1039 appropriate floating-point precision directly.
1041 2017-04-07 Alan Modra <amodra@gmail.com>
1043 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1044 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1045 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1046 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1047 vector instructions with E6500 not PPCVEC2.
1049 2017-04-06 Pip Cet <pipcet@gmail.com>
1051 * Makefile.am: Add wasm32-dis.c.
1052 * configure.ac: Add wasm32-dis.c to wasm32 target.
1053 * disassemble.c: Add wasm32 disassembler code.
1054 * wasm32-dis.c: New file.
1055 * Makefile.in: Regenerate.
1056 * configure: Regenerate.
1057 * po/POTFILES.in: Regenerate.
1058 * po/opcodes.pot: Regenerate.
1060 2017-04-05 Pedro Alves <palves@redhat.com>
1062 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1063 * arm-dis.c (parse_arm_disassembler_options): Constify.
1064 * ppc-dis.c (powerpc_init_dialect): Constify local.
1065 * vax-dis.c (parse_disassembler_options): Constify.
1067 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
1069 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1072 2017-03-30 Pip Cet <pipcet@gmail.com>
1074 * configure.ac: Add (empty) bfd_wasm32_arch target.
1075 * configure: Regenerate
1076 * po/opcodes.pot: Regenerate.
1078 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
1080 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1082 * opcodes/sparc-opc.c (asi_table): New ASIs.
1084 2017-03-29 Alan Modra <amodra@gmail.com>
1086 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
1088 (lookup_powerpc): Don't special case -1 dialect. Handle
1090 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1091 lookup_powerpc call, pass it on second.
1093 2017-03-27 Alan Modra <amodra@gmail.com>
1096 * ppc-dis.c (struct ppc_mopt): Comment.
1097 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1099 2017-03-27 Rinat Zelig <rinat@mellanox.com>
1101 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1102 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1103 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1104 (insert_nps_misc_imm_offset): New function.
1105 (extract_nps_misc imm_offset): New function.
1106 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1107 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1109 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1111 * s390-mkopc.c (main): Remove vx2 check.
1112 * s390-opc.txt: Remove vx2 instruction flags.
1114 2017-03-21 Rinat Zelig <rinat@mellanox.com>
1116 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1117 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1118 (insert_nps_imm_offset): New function.
1119 (extract_nps_imm_offset): New function.
1120 (insert_nps_imm_entry): New function.
1121 (extract_nps_imm_entry): New function.
1123 2017-03-17 Alan Modra <amodra@gmail.com>
1126 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1127 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
1128 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
1130 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1132 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1136 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1138 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1140 2017-03-13 Andrew Waterman <andrew@sifive.com>
1142 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1147 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1149 * i386-gen.c (opcode_modifiers): Replace S with Load.
1150 * i386-opc.h (S): Removed.
1152 (i386_opcode_modifier): Replace s with load.
1153 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1154 and {evex}. Replace S with Load.
1155 * i386-tbl.h: Regenerated.
1157 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1159 * i386-opc.tbl: Use CpuCET on rdsspq.
1160 * i386-tbl.h: Regenerated.
1162 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1164 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1165 <vsx>: Do not use PPC_OPCODE_VSX3;
1167 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1169 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1171 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
1173 * i386-dis.c (REG_0F1E_MOD_3): New enum.
1174 (MOD_0F1E_PREFIX_1): Likewise.
1175 (MOD_0F38F5_PREFIX_2): Likewise.
1176 (MOD_0F38F6_PREFIX_0): Likewise.
1177 (RM_0F1E_MOD_3_REG_7): Likewise.
1178 (PREFIX_MOD_0_0F01_REG_5): Likewise.
1179 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1180 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1181 (PREFIX_0F1E): Likewise.
1182 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1183 (PREFIX_0F38F5): Likewise.
1184 (dis386_twobyte): Use PREFIX_0F1E.
1185 (reg_table): Add REG_0F1E_MOD_3.
1186 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1187 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1188 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1189 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1190 (three_byte_table): Use PREFIX_0F38F5.
1191 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1192 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1193 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1194 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1195 PREFIX_MOD_3_0F01_REG_5_RM_2.
1196 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1197 (cpu_flags): Add CpuCET.
1198 * i386-opc.h (CpuCET): New enum.
1199 (CpuUnused): Commented out.
1200 (i386_cpu_flags): Add cpucet.
1201 * i386-opc.tbl: Add Intel CET instructions.
1202 * i386-init.h: Regenerated.
1203 * i386-tbl.h: Likewise.
1205 2017-03-06 Alan Modra <amodra@gmail.com>
1208 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1209 (extract_raq, extract_ras, extract_rbx): New functions.
1210 (powerpc_operands): Use opposite corresponding insert function.
1212 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1213 register restriction.
1215 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1217 * disassemble.c Include "safe-ctype.h".
1218 (disassemble_init_for_target): Handle s390 init.
1219 (remove_whitespace_and_extra_commas): New function.
1220 (disassembler_options_cmp): Likewise.
1221 * arm-dis.c: Include "libiberty.h".
1223 (regnames): Use long disassembler style names.
1224 Add force-thumb and no-force-thumb options.
1225 (NUM_ARM_REGNAMES): Rename from this...
1226 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1227 (get_arm_regname_num_options): Delete.
1228 (set_arm_regname_option): Likewise.
1229 (get_arm_regnames): Likewise.
1230 (parse_disassembler_options): Likewise.
1231 (parse_arm_disassembler_option): Rename from this...
1232 (parse_arm_disassembler_options): ...to this. Make static.
1233 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1234 (print_insn): Use parse_arm_disassembler_options.
1235 (disassembler_options_arm): New function.
1236 (print_arm_disassembler_options): Handle updated regnames.
1237 * ppc-dis.c: Include "libiberty.h".
1238 (ppc_opts): Add "32" and "64" entries.
1239 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1240 (powerpc_init_dialect): Add break to switch statement.
1241 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1242 (disassembler_options_powerpc): New function.
1243 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1244 Remove printing of "32" and "64".
1245 * s390-dis.c: Include "libiberty.h".
1246 (init_flag): Remove unneeded variable.
1247 (struct s390_options_t): New structure type.
1248 (options): New structure.
1249 (init_disasm): Rename from this...
1250 (disassemble_init_s390): ...to this. Add initializations for
1251 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1252 (print_insn_s390): Delete call to init_disasm.
1253 (disassembler_options_s390): New function.
1254 (print_s390_disassembler_options): Print using information from
1256 * po/opcodes.pot: Regenerate.
1258 2017-02-28 Jan Beulich <jbeulich@suse.com>
1260 * i386-dis.c (PCMPESTR_Fixup): New.
1261 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1262 (prefix_table): Use PCMPESTR_Fixup.
1263 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1265 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1266 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1267 Split 64-bit and non-64-bit variants.
1268 * opcodes/i386-tbl.h: Re-generate.
1270 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1272 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1273 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1274 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1275 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1276 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1277 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1278 (OP_SVE_V_HSD): New macros.
1279 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1280 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1281 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1282 (aarch64_opcode_table): Add new SVE instructions.
1283 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1284 for rotation operands. Add new SVE operands.
1285 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1286 (ins_sve_quad_index): Likewise.
1287 (ins_imm_rotate): Split into...
1288 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1289 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1290 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1292 (aarch64_ins_sve_addr_ri_s4): New function.
1293 (aarch64_ins_sve_quad_index): Likewise.
1294 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1295 * aarch64-asm-2.c: Regenerate.
1296 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1297 (ext_sve_quad_index): Likewise.
1298 (ext_imm_rotate): Split into...
1299 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1300 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1301 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1303 (aarch64_ext_sve_addr_ri_s4): New function.
1304 (aarch64_ext_sve_quad_index): Likewise.
1305 (aarch64_ext_sve_index): Allow quad indices.
1306 (do_misc_decoding): Likewise.
1307 * aarch64-dis-2.c: Regenerate.
1308 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1309 aarch64_field_kinds.
1310 (OPD_F_OD_MASK): Widen by one bit.
1311 (OPD_F_NO_ZR): Bump accordingly.
1312 (get_operand_field_width): New function.
1313 * aarch64-opc.c (fields): Add new SVE fields.
1314 (operand_general_constraint_met_p): Handle new SVE operands.
1315 (aarch64_print_operand): Likewise.
1316 * aarch64-opc-2.c: Regenerate.
1318 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1320 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1321 (aarch64_feature_compnum): ...this.
1322 (SIMD_V8_3): Replace with...
1324 (CNUM_INSN): New macro.
1325 (aarch64_opcode_table): Use it for the complex number instructions.
1327 2017-02-24 Jan Beulich <jbeulich@suse.com>
1329 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1331 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1333 Add support for associating SPARC ASIs with an architecture level.
1334 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1335 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1336 decoding of SPARC ASIs.
1338 2017-02-23 Jan Beulich <jbeulich@suse.com>
1340 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1341 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1343 2017-02-21 Jan Beulich <jbeulich@suse.com>
1345 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1346 1 (instead of to itself). Correct typo.
1348 2017-02-14 Andrew Waterman <andrew@sifive.com>
1350 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1353 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1355 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1356 (aarch64_sys_reg_supported_p): Handle them.
1358 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1360 * arc-opc.c (UIMM6_20R): Define.
1361 (SIMM12_20): Use above.
1362 (SIMM12_20R): Define.
1363 (SIMM3_5_S): Use above.
1364 (UIMM7_A32_11R_S): Define.
1365 (UIMM7_9_S): Use above.
1366 (UIMM3_13R_S): Define.
1367 (SIMM11_A32_7_S): Use above.
1369 (UIMM10_A32_8_S): Use above.
1370 (UIMM8_8R_S): Define.
1372 (arc_relax_opcodes): Use all above defines.
1374 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
1376 * arc-regs.h: Distinguish some of the registers different on
1377 ARC700 and HS38 cpus.
1379 2017-02-14 Alan Modra <amodra@gmail.com>
1382 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1383 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1385 2017-02-11 Stafford Horne <shorne@gmail.com>
1386 Alan Modra <amodra@gmail.com>
1388 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1389 Use insn_bytes_value and insn_int_value directly instead. Don't
1390 free allocated memory until function exit.
1392 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
1394 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1396 2017-02-03 Nick Clifton <nickc@redhat.com>
1399 * aarch64-opc.c (print_register_list): Ensure that the register
1400 list index will fir into the tb buffer.
1401 (print_register_offset_address): Likewise.
1402 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1404 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1407 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1408 instructions when the previous fetch packet ends with a 32-bit
1411 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1413 * pru-opc.c: Remove vague reference to a future GDB port.
1415 2017-01-20 Nick Clifton <nickc@redhat.com>
1417 * po/ga.po: Updated Irish translation.
1419 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1421 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1423 2017-01-13 Yao Qi <yao.qi@linaro.org>
1425 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1426 if FETCH_DATA returns 0.
1427 (m68k_scan_mask): Likewise.
1428 (print_insn_m68k): Update code to handle -1 return value.
1430 2017-01-13 Yao Qi <yao.qi@linaro.org>
1432 * m68k-dis.c (enum print_insn_arg_error): New.
1433 (NEXTBYTE): Replace -3 with
1434 PRINT_INSN_ARG_MEMORY_ERROR.
1435 (NEXTULONG): Likewise.
1436 (NEXTSINGLE): Likewise.
1437 (NEXTDOUBLE): Likewise.
1438 (NEXTDOUBLE): Likewise.
1439 (NEXTPACKED): Likewise.
1440 (FETCH_ARG): Likewise.
1441 (FETCH_DATA): Update comments.
1442 (print_insn_arg): Update comments. Replace magic numbers with
1444 (match_insn_m68k): Likewise.
1446 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1448 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1449 * i386-dis-evex.h (evex_table): Updated.
1450 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1451 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1452 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1453 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1454 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1455 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1456 * i386-init.h: Regenerate.
1457 * i386-tbl.h: Ditto.
1459 2017-01-12 Yao Qi <yao.qi@linaro.org>
1461 * msp430-dis.c (msp430_singleoperand): Return -1 if
1462 msp430dis_opcode_signed returns false.
1463 (msp430_doubleoperand): Likewise.
1464 (msp430_branchinstr): Return -1 if
1465 msp430dis_opcode_unsigned returns false.
1466 (msp430x_calla_instr): Likewise.
1467 (print_insn_msp430): Likewise.
1469 2017-01-05 Nick Clifton <nickc@redhat.com>
1472 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1473 could not be matched.
1474 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1477 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1479 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1480 (aarch64_opcode_table): Use RCPC_INSN.
1482 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
1484 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1486 * riscv-opcodes/all-opcodes: Likewise.
1488 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1490 * riscv-dis.c (print_insn_args): Add fall through comment.
1492 2017-01-03 Nick Clifton <nickc@redhat.com>
1494 * po/sr.po: New Serbian translation.
1495 * configure.ac (ALL_LINGUAS): Add sr.
1496 * configure: Regenerate.
1498 2017-01-02 Alan Modra <amodra@gmail.com>
1500 * epiphany-desc.h: Regenerate.
1501 * epiphany-opc.h: Regenerate.
1502 * fr30-desc.h: Regenerate.
1503 * fr30-opc.h: Regenerate.
1504 * frv-desc.h: Regenerate.
1505 * frv-opc.h: Regenerate.
1506 * ip2k-desc.h: Regenerate.
1507 * ip2k-opc.h: Regenerate.
1508 * iq2000-desc.h: Regenerate.
1509 * iq2000-opc.h: Regenerate.
1510 * lm32-desc.h: Regenerate.
1511 * lm32-opc.h: Regenerate.
1512 * m32c-desc.h: Regenerate.
1513 * m32c-opc.h: Regenerate.
1514 * m32r-desc.h: Regenerate.
1515 * m32r-opc.h: Regenerate.
1516 * mep-desc.h: Regenerate.
1517 * mep-opc.h: Regenerate.
1518 * mt-desc.h: Regenerate.
1519 * mt-opc.h: Regenerate.
1520 * or1k-desc.h: Regenerate.
1521 * or1k-opc.h: Regenerate.
1522 * xc16x-desc.h: Regenerate.
1523 * xc16x-opc.h: Regenerate.
1524 * xstormy16-desc.h: Regenerate.
1525 * xstormy16-opc.h: Regenerate.
1527 2017-01-02 Alan Modra <amodra@gmail.com>
1529 Update year range in copyright notice of all files.
1531 For older changes see ChangeLog-2016
1533 Copyright (C) 2017 Free Software Foundation, Inc.
1535 Copying and distribution of this file, with or without modification,
1536 are permitted in any medium without royalty provided the copyright
1537 notice and this notice are preserved.
1543 version-control: never