1 2018-11-12 Sudakshina Das <sudi.das@arm.com>
3 * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
4 for AARCH64_OPND_QLF_imm_tag.
5 (operand_general_constraint_met_p): Add case for
6 AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
7 (aarch64_print_operand): Likewise.
8 * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
9 (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
10 for both offset and pre/post indexed versions.
11 (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
12 * aarch64-asm-2.c: Regenerated.
13 * aarch64-dis-2.c: Regenerated.
14 * aarch64-opc-2.c: Regenerated.
16 2018-11-12 Sudakshina Das <sudi.das@arm.com>
18 * aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp.
19 * aarch64-asm-2.c: Regenerated.
20 * aarch64-dis-2.c: Regenerated.
21 * aarch64-opc-2.c: Regenerated.
23 2018-11-12 Sudakshina Das <sudi.das@arm.com>
25 * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
26 (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
27 * aarch64-opc.c (fields): Add entry for imm4_3.
28 (operand_general_constraint_met_p): Add cases for
29 AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
30 (aarch64_print_operand): Likewise.
31 * aarch64-tbl.h (QL_ADDG): New.
32 (aarch64_opcode_table): Add addg, subg, irg and gmi.
33 (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
34 * aarch64-asm.c (aarch64_ins_imm): Add case for
35 operand_need_shift_by_four.
36 * aarch64-asm-2.c: Regenerated.
37 * aarch64-dis-2.c: Regenerated.
38 * aarch64-opc-2.c: Regenerated.
40 2018-11-12 Sudakshina Das <sudi.das@arm.com>
42 * aarch64-tbl.h (aarch64_feature_memtag): New.
43 (MEMTAG, MEMTAG_INSN): New.
45 2018-11-06 Sudakshina Das <sudi.das@arm.com>
47 * arm-dis.c (select_arm_features): Update bfd_mach_arm_8
48 with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML.
50 2018-11-06 Alan Modra <amodra@gmail.com>
52 * ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls),
53 (insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0),
54 (insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16),
55 (insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd):
56 Don't return zero on error, insert mask bits instead.
57 (insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete.
58 (insert_sh6, extract_sh6): Delete dead code.
59 (insert_sprbat, insert_sprg): Use unsigned comparisions.
60 (powerpc_operands <OIMM>): Set shift count rather than using
62 <SE_SDH, SE_SDW>: Likewise. Don't use insert/extract functions.
64 2018-11-06 Jan Beulich <jbeulich@suse.com>
66 * i386-dis-evex.h (evex_table): Use K suffix instead of %LW for
67 vpbroadcast{d,q} with GPR operand.
69 2018-11-06 Jan Beulich <jbeulich@suse.com>
71 * i386-dis.c (EVEX_W_0F6E_P_2, EVEX_W_0F7E_P_2): Delete.
72 * i386-dis-evex.h (evex_table): Move vmov[dq} with GPR operand
73 cases up one level in the hierarchy.
75 2018-11-06 Jan Beulich <jbeulich@suse.com>
77 * i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0,
78 MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0.
79 (MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold
80 into MOD_VEX_0F93_P_3_LEN_0.
81 (vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR
82 operand cases up one level in the hierarchy.
84 2018-11-06 Jan Beulich <jbeulich@suse.com>
86 * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
87 VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
88 EVEX_W_0F3A22_P_2): Delete.
89 (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
90 entries up one level in the hierarchy.
91 (OP_E_memory): Handle dq_mode when determining Disp8 shift
93 * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
94 entries up one level in the hierarchy.
95 * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
96 VexWIG for AVX flavors.
97 * i386-tbl.h: Re-generate.
99 2018-11-06 Jan Beulich <jbeulich@suse.com>
101 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
102 vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
103 vcvtusi2ss, kmovd): Drop VexW=1.
104 * i386-tbl.h: Re-generate.
106 2018-11-06 Jan Beulich <jbeulich@suse.com>
108 * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
109 EVex512, EVexLIG, EVexDYN): New.
110 (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
111 insns): Use Vex128 instead of Vex=3 (aka VexLIG).
112 (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
113 of EVex=4 (aka EVexLIG).
114 * i386-tbl.h: Re-generate.
116 2018-11-06 Jan Beulich <jbeulich@suse.com>
118 * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
119 (vpmaxub): Re-order attributes on AVX512BW flavor.
120 * i386-tbl.h: Re-generate.
122 2018-11-06 Jan Beulich <jbeulich@suse.com>
124 * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
125 vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
126 Vex=1 on AVX / AVX2 flavors.
127 (vpmaxub): Re-order attributes on AVX512BW flavor.
128 * i386-tbl.h: Re-generate.
130 2018-11-06 Jan Beulich <jbeulich@suse.com>
132 * i386-opc.tbl (VexW0, VexW1): New.
133 (vphadd*, vphsub*): Use VexW0 on XOP variants.
134 * i386-tbl.h: Re-generate.
136 2018-10-22 John Darrington <john@darrington.wattle.id.au>
138 * s12z-dis.c (decode_possible_symbol): Add fallback case.
139 (rel_15_7): Likewise.
141 2018-10-19 Tamar Christina <tamar.christina@arm.com>
143 * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
144 (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
145 (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
147 2018-10-16 Matthew Malcomson <matthew.malcomson@arm.com>
149 * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
150 corresponding to AARCH64_OPND_QLF_S_4B qualifier.
152 2018-10-10 Jan Beulich <jbeulich@suse.com>
154 * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
156 * i386-opc.h (Size16, Size32, Size64): Delete.
158 (SIZE16, SIZE32, SIZE64): Define.
159 (struct i386_opcode_modifier): Drop size16, size32, and size64.
161 * i386-opc.tbl (Size16, Size32, Size64): Define.
162 * i386-tbl.h: Re-generate.
164 2018-10-09 Sudakshina Das <sudi.das@arm.com>
166 * aarch64-opc.c (operand_general_constraint_met_p): Add
167 SSBS in the check for one-bit immediate.
168 (aarch64_sys_regs): New entry for SSBS.
169 (aarch64_sys_reg_supported_p): New check for above.
170 (aarch64_pstatefields): New entry for SSBS.
171 (aarch64_pstatefield_supported_p): New check for above.
173 2018-10-09 Sudakshina Das <sudi.das@arm.com>
175 * aarch64-opc.c (aarch64_sys_regs): New entries for
176 scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
177 (aarch64_sys_reg_supported_p): New checks for above.
179 2018-10-09 Sudakshina Das <sudi.das@arm.com>
181 * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
182 (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
183 with the hint immediate.
184 * aarch64-opc.c (aarch64_hint_options): New entries for
185 c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
186 (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
187 while checking for HINT_OPD_F_NOPRINT flag.
188 * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
190 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
191 (aarch64_opcode_table): Add entry for BTI.
192 (AARCH64_OPERANDS): Add new description for BTI targets.
193 * aarch64-asm-2.c: Regenerate.
194 * aarch64-dis-2.c: Regenerate.
195 * aarch64-opc-2.c: Regenerate.
197 2018-10-09 Sudakshina Das <sudi.das@arm.com>
199 * aarch64-opc.c (aarch64_sys_regs): New entries for
201 (aarch64_sys_reg_supported_p): New check for above.
203 2018-10-09 Sudakshina Das <sudi.das@arm.com>
205 * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
206 (aarch64_sys_ins_reg_supported_p): New check for above.
208 2018-10-09 Sudakshina Das <sudi.das@arm.com>
210 * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
211 AARCH64_OPND_SYSREG_SR.
212 * aarch64-opc.c (aarch64_print_operand): Likewise.
213 (aarch64_sys_regs_sr): Define table.
214 (aarch64_sys_ins_reg_supported_p): Check for RCTX with
215 AARCH64_FEATURE_PREDRES.
216 * aarch64-tbl.h (aarch64_feature_predres): New.
217 (PREDRES, PREDRES_INSN): New.
218 (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
219 (AARCH64_OPERANDS): Add new description for SYSREG_SR.
220 * aarch64-asm-2.c: Regenerate.
221 * aarch64-dis-2.c: Regenerate.
222 * aarch64-opc-2.c: Regenerate.
224 2018-10-09 Sudakshina Das <sudi.das@arm.com>
226 * aarch64-tbl.h (aarch64_feature_sb): New.
228 (aarch64_opcode_table): Add entry for sb.
229 * aarch64-asm-2.c: Regenerate.
230 * aarch64-dis-2.c: Regenerate.
231 * aarch64-opc-2.c: Regenerate.
233 2018-10-09 Sudakshina Das <sudi.das@arm.com>
235 * aarch64-tbl.h (aarch64_feature_flagmanip): New.
236 (aarch64_feature_frintts): New.
237 (FLAGMANIP, FRINTTS): New.
238 (aarch64_opcode_table): Add entries for xaflag, axflag
239 and frint[32,64][x,z] instructions.
240 * aarch64-asm-2.c: Regenerate.
241 * aarch64-dis-2.c: Regenerate.
242 * aarch64-opc-2.c: Regenerate.
244 2018-10-09 Sudakshina Das <sudi.das@arm.com>
246 * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
247 (ARMV8_5, V8_5_INSN): New.
249 2018-10-08 Tamar Christina <tamar.christina@arm.com>
251 * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
253 2018-10-05 H.J. Lu <hongjiu.lu@intel.com>
255 * i386-dis.c (rm_table): Add enclv.
256 * i386-opc.tbl: Add enclv.
257 * i386-tbl.h: Regenerated.
259 2018-10-05 Sudakshina Das <sudi.das@arm.com>
261 * arm-dis.c (arm_opcodes): Add sb.
262 (thumb32_opcodes): Likewise.
264 2018-10-05 Richard Henderson <rth@twiddle.net>
265 Stafford Horne <shorne@gmail.com>
267 * or1k-desc.c: Regenerate.
268 * or1k-desc.h: Regenerate.
269 * or1k-opc.c: Regenerate.
270 * or1k-opc.h: Regenerate.
271 * or1k-opinst.c: Regenerate.
273 2018-10-05 Richard Henderson <rth@twiddle.net>
275 * or1k-asm.c: Regenerated.
276 * or1k-desc.c: Regenerated.
277 * or1k-desc.h: Regenerated.
278 * or1k-dis.c: Regenerated.
279 * or1k-ibld.c: Regenerated.
280 * or1k-opc.c: Regenerated.
281 * or1k-opc.h: Regenerated.
282 * or1k-opinst.c: Regenerated.
284 2018-10-05 Richard Henderson <rth@twiddle.net>
286 * or1k-asm.c: Regenerate.
288 2018-10-03 Tamar Christina <tamar.christina@arm.com>
290 * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
291 * aarch64-dis.c (print_operands): Refactor to take notes.
292 (print_verifier_notes): New.
293 (print_aarch64_insn): Apply constraint verifier.
294 (print_insn_aarch64_word): Update call to print_aarch64_insn.
295 * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
297 2018-10-03 Tamar Christina <tamar.christina@arm.com>
299 * aarch64-opc.c (init_insn_block): New.
300 (verify_constraints, aarch64_is_destructive_by_operands): New.
301 * aarch64-opc.h (verify_constraints): New.
303 2018-10-03 Tamar Christina <tamar.christina@arm.com>
305 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
306 * aarch64-opc.c (verify_ldpsw): Update arguments.
308 2018-10-03 Tamar Christina <tamar.christina@arm.com>
310 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
311 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
313 2018-10-03 Tamar Christina <tamar.christina@arm.com>
315 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
316 * aarch64-dis.c (insn_sequence): New.
318 2018-10-03 Tamar Christina <tamar.christina@arm.com>
320 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
321 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
322 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
323 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
326 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
328 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
330 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
331 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
332 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
333 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
334 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
335 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
336 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
338 2018-10-02 Palmer Dabbelt <palmer@sifive.com>
340 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
342 2018-09-23 Sandra Loosemore <sandra@codesourcery.com>
344 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
345 are used when extracting signed fields and converting them to
346 potentially 64-bit types.
348 2018-09-21 Simon Marchi <simon.marchi@ericsson.com>
350 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
351 * Makefile.in: Re-generate.
352 * aclocal.m4: Re-generate.
353 * configure: Re-generate.
354 * configure.ac: Remove check for -Wno-missing-field-initializers.
355 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
356 (csky_v2_opcodes): Likewise.
358 2018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
360 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
362 2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
364 * nds32-asm.c (operand_fields): Remove the unused fields.
365 (nds32_opcodes): Remove the unused instructions.
366 * nds32-dis.c (nds32_ex9_info): Removed.
367 (nds32_parse_opcode): Updated.
368 (print_insn_nds32): Likewise.
369 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
370 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
371 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
372 build_opcode_hash_table): New functions.
373 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
374 nds32_opcode_table): New.
375 (hw_ktabs): Declare it to a pointer rather than an array.
376 (build_hash_table): Removed.
377 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
378 SYN_ROPT and upadte HW_GPR and HW_INT.
379 * nds32-dis.c (keywords): Remove const.
380 (match_field): New function.
381 (nds32_parse_opcode): Updated.
382 * disassemble.c (disassemble_init_for_target):
383 Add disassemble_init_nds32.
384 * nds32-dis.c (eum map_type): New.
385 (nds32_private_data): Likewise.
386 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
387 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
388 (print_insn_nds32): Updated.
389 * nds32-asm.c (parse_aext_reg): Add new parameter.
390 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
393 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
394 (operand_fields): Add new fields.
395 (nds32_opcodes): Add new instructions.
396 (keyword_aridxi_mx): New keyword.
397 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
399 (ALU2_1, ALU2_2, ALU2_3): New macros.
400 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
402 2018-09-17 Kito Cheng <kito@andestech.com>
404 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
406 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
409 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
410 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
411 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
412 (EVEX_LEN_0F7E_P_1): Likewise.
413 (EVEX_LEN_0F7E_P_2): Likewise.
414 (EVEX_LEN_0FD6_P_2): Likewise.
415 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
416 (EVEX_LEN_TABLE): Likewise.
417 (EVEX_LEN_0F6E_P_2): New enum.
418 (EVEX_LEN_0F7E_P_1): Likewise.
419 (EVEX_LEN_0F7E_P_2): Likewise.
420 (EVEX_LEN_0FD6_P_2): Likewise.
421 (evex_len_table): New.
422 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
423 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
424 * i386-tbl.h: Regenerated.
426 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
429 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
430 VEX_LEN_0F7E_P_2 entries.
431 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
432 * i386-tbl.h: Regenerated.
434 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
436 * i386-dis.c (VZERO_Fixup): Removed.
438 (VEX_LEN_0F10_P_1): Likewise.
439 (VEX_LEN_0F10_P_3): Likewise.
440 (VEX_LEN_0F11_P_1): Likewise.
441 (VEX_LEN_0F11_P_3): Likewise.
442 (VEX_LEN_0F2E_P_0): Likewise.
443 (VEX_LEN_0F2E_P_2): Likewise.
444 (VEX_LEN_0F2F_P_0): Likewise.
445 (VEX_LEN_0F2F_P_2): Likewise.
446 (VEX_LEN_0F51_P_1): Likewise.
447 (VEX_LEN_0F51_P_3): Likewise.
448 (VEX_LEN_0F52_P_1): Likewise.
449 (VEX_LEN_0F53_P_1): Likewise.
450 (VEX_LEN_0F58_P_1): Likewise.
451 (VEX_LEN_0F58_P_3): Likewise.
452 (VEX_LEN_0F59_P_1): Likewise.
453 (VEX_LEN_0F59_P_3): Likewise.
454 (VEX_LEN_0F5A_P_1): Likewise.
455 (VEX_LEN_0F5A_P_3): Likewise.
456 (VEX_LEN_0F5C_P_1): Likewise.
457 (VEX_LEN_0F5C_P_3): Likewise.
458 (VEX_LEN_0F5D_P_1): Likewise.
459 (VEX_LEN_0F5D_P_3): Likewise.
460 (VEX_LEN_0F5E_P_1): Likewise.
461 (VEX_LEN_0F5E_P_3): Likewise.
462 (VEX_LEN_0F5F_P_1): Likewise.
463 (VEX_LEN_0F5F_P_3): Likewise.
464 (VEX_LEN_0FC2_P_1): Likewise.
465 (VEX_LEN_0FC2_P_3): Likewise.
466 (VEX_LEN_0F3A0A_P_2): Likewise.
467 (VEX_LEN_0F3A0B_P_2): Likewise.
468 (VEX_W_0F10_P_0): Likewise.
469 (VEX_W_0F10_P_1): Likewise.
470 (VEX_W_0F10_P_2): Likewise.
471 (VEX_W_0F10_P_3): Likewise.
472 (VEX_W_0F11_P_0): Likewise.
473 (VEX_W_0F11_P_1): Likewise.
474 (VEX_W_0F11_P_2): Likewise.
475 (VEX_W_0F11_P_3): Likewise.
476 (VEX_W_0F12_P_0_M_0): Likewise.
477 (VEX_W_0F12_P_0_M_1): Likewise.
478 (VEX_W_0F12_P_1): Likewise.
479 (VEX_W_0F12_P_2): Likewise.
480 (VEX_W_0F12_P_3): Likewise.
481 (VEX_W_0F13_M_0): Likewise.
482 (VEX_W_0F14): Likewise.
483 (VEX_W_0F15): Likewise.
484 (VEX_W_0F16_P_0_M_0): Likewise.
485 (VEX_W_0F16_P_0_M_1): Likewise.
486 (VEX_W_0F16_P_1): Likewise.
487 (VEX_W_0F16_P_2): Likewise.
488 (VEX_W_0F17_M_0): Likewise.
489 (VEX_W_0F28): Likewise.
490 (VEX_W_0F29): Likewise.
491 (VEX_W_0F2B_M_0): Likewise.
492 (VEX_W_0F2E_P_0): Likewise.
493 (VEX_W_0F2E_P_2): Likewise.
494 (VEX_W_0F2F_P_0): Likewise.
495 (VEX_W_0F2F_P_2): Likewise.
496 (VEX_W_0F50_M_0): Likewise.
497 (VEX_W_0F51_P_0): Likewise.
498 (VEX_W_0F51_P_1): Likewise.
499 (VEX_W_0F51_P_2): Likewise.
500 (VEX_W_0F51_P_3): Likewise.
501 (VEX_W_0F52_P_0): Likewise.
502 (VEX_W_0F52_P_1): Likewise.
503 (VEX_W_0F53_P_0): Likewise.
504 (VEX_W_0F53_P_1): Likewise.
505 (VEX_W_0F58_P_0): Likewise.
506 (VEX_W_0F58_P_1): Likewise.
507 (VEX_W_0F58_P_2): Likewise.
508 (VEX_W_0F58_P_3): Likewise.
509 (VEX_W_0F59_P_0): Likewise.
510 (VEX_W_0F59_P_1): Likewise.
511 (VEX_W_0F59_P_2): Likewise.
512 (VEX_W_0F59_P_3): Likewise.
513 (VEX_W_0F5A_P_0): Likewise.
514 (VEX_W_0F5A_P_1): Likewise.
515 (VEX_W_0F5A_P_3): Likewise.
516 (VEX_W_0F5B_P_0): Likewise.
517 (VEX_W_0F5B_P_1): Likewise.
518 (VEX_W_0F5B_P_2): Likewise.
519 (VEX_W_0F5C_P_0): Likewise.
520 (VEX_W_0F5C_P_1): Likewise.
521 (VEX_W_0F5C_P_2): Likewise.
522 (VEX_W_0F5C_P_3): Likewise.
523 (VEX_W_0F5D_P_0): Likewise.
524 (VEX_W_0F5D_P_1): Likewise.
525 (VEX_W_0F5D_P_2): Likewise.
526 (VEX_W_0F5D_P_3): Likewise.
527 (VEX_W_0F5E_P_0): Likewise.
528 (VEX_W_0F5E_P_1): Likewise.
529 (VEX_W_0F5E_P_2): Likewise.
530 (VEX_W_0F5E_P_3): Likewise.
531 (VEX_W_0F5F_P_0): Likewise.
532 (VEX_W_0F5F_P_1): Likewise.
533 (VEX_W_0F5F_P_2): Likewise.
534 (VEX_W_0F5F_P_3): Likewise.
535 (VEX_W_0F60_P_2): Likewise.
536 (VEX_W_0F61_P_2): Likewise.
537 (VEX_W_0F62_P_2): Likewise.
538 (VEX_W_0F63_P_2): Likewise.
539 (VEX_W_0F64_P_2): Likewise.
540 (VEX_W_0F65_P_2): Likewise.
541 (VEX_W_0F66_P_2): Likewise.
542 (VEX_W_0F67_P_2): Likewise.
543 (VEX_W_0F68_P_2): Likewise.
544 (VEX_W_0F69_P_2): Likewise.
545 (VEX_W_0F6A_P_2): Likewise.
546 (VEX_W_0F6B_P_2): Likewise.
547 (VEX_W_0F6C_P_2): Likewise.
548 (VEX_W_0F6D_P_2): Likewise.
549 (VEX_W_0F6F_P_1): Likewise.
550 (VEX_W_0F6F_P_2): Likewise.
551 (VEX_W_0F70_P_1): Likewise.
552 (VEX_W_0F70_P_2): Likewise.
553 (VEX_W_0F70_P_3): Likewise.
554 (VEX_W_0F71_R_2_P_2): Likewise.
555 (VEX_W_0F71_R_4_P_2): Likewise.
556 (VEX_W_0F71_R_6_P_2): Likewise.
557 (VEX_W_0F72_R_2_P_2): Likewise.
558 (VEX_W_0F72_R_4_P_2): Likewise.
559 (VEX_W_0F72_R_6_P_2): Likewise.
560 (VEX_W_0F73_R_2_P_2): Likewise.
561 (VEX_W_0F73_R_3_P_2): Likewise.
562 (VEX_W_0F73_R_6_P_2): Likewise.
563 (VEX_W_0F73_R_7_P_2): Likewise.
564 (VEX_W_0F74_P_2): Likewise.
565 (VEX_W_0F75_P_2): Likewise.
566 (VEX_W_0F76_P_2): Likewise.
567 (VEX_W_0F77_P_0): Likewise.
568 (VEX_W_0F7C_P_2): Likewise.
569 (VEX_W_0F7C_P_3): Likewise.
570 (VEX_W_0F7D_P_2): Likewise.
571 (VEX_W_0F7D_P_3): Likewise.
572 (VEX_W_0F7E_P_1): Likewise.
573 (VEX_W_0F7F_P_1): Likewise.
574 (VEX_W_0F7F_P_2): Likewise.
575 (VEX_W_0FAE_R_2_M_0): Likewise.
576 (VEX_W_0FAE_R_3_M_0): Likewise.
577 (VEX_W_0FC2_P_0): Likewise.
578 (VEX_W_0FC2_P_1): Likewise.
579 (VEX_W_0FC2_P_2): Likewise.
580 (VEX_W_0FC2_P_3): Likewise.
581 (VEX_W_0FD0_P_2): Likewise.
582 (VEX_W_0FD0_P_3): Likewise.
583 (VEX_W_0FD1_P_2): Likewise.
584 (VEX_W_0FD2_P_2): Likewise.
585 (VEX_W_0FD3_P_2): Likewise.
586 (VEX_W_0FD4_P_2): Likewise.
587 (VEX_W_0FD5_P_2): Likewise.
588 (VEX_W_0FD6_P_2): Likewise.
589 (VEX_W_0FD7_P_2_M_1): Likewise.
590 (VEX_W_0FD8_P_2): Likewise.
591 (VEX_W_0FD9_P_2): Likewise.
592 (VEX_W_0FDA_P_2): Likewise.
593 (VEX_W_0FDB_P_2): Likewise.
594 (VEX_W_0FDC_P_2): Likewise.
595 (VEX_W_0FDD_P_2): Likewise.
596 (VEX_W_0FDE_P_2): Likewise.
597 (VEX_W_0FDF_P_2): Likewise.
598 (VEX_W_0FE0_P_2): Likewise.
599 (VEX_W_0FE1_P_2): Likewise.
600 (VEX_W_0FE2_P_2): Likewise.
601 (VEX_W_0FE3_P_2): Likewise.
602 (VEX_W_0FE4_P_2): Likewise.
603 (VEX_W_0FE5_P_2): Likewise.
604 (VEX_W_0FE6_P_1): Likewise.
605 (VEX_W_0FE6_P_2): Likewise.
606 (VEX_W_0FE6_P_3): Likewise.
607 (VEX_W_0FE7_P_2_M_0): Likewise.
608 (VEX_W_0FE8_P_2): Likewise.
609 (VEX_W_0FE9_P_2): Likewise.
610 (VEX_W_0FEA_P_2): Likewise.
611 (VEX_W_0FEB_P_2): Likewise.
612 (VEX_W_0FEC_P_2): Likewise.
613 (VEX_W_0FED_P_2): Likewise.
614 (VEX_W_0FEE_P_2): Likewise.
615 (VEX_W_0FEF_P_2): Likewise.
616 (VEX_W_0FF0_P_3_M_0): Likewise.
617 (VEX_W_0FF1_P_2): Likewise.
618 (VEX_W_0FF2_P_2): Likewise.
619 (VEX_W_0FF3_P_2): Likewise.
620 (VEX_W_0FF4_P_2): Likewise.
621 (VEX_W_0FF5_P_2): Likewise.
622 (VEX_W_0FF6_P_2): Likewise.
623 (VEX_W_0FF7_P_2): Likewise.
624 (VEX_W_0FF8_P_2): Likewise.
625 (VEX_W_0FF9_P_2): Likewise.
626 (VEX_W_0FFA_P_2): Likewise.
627 (VEX_W_0FFB_P_2): Likewise.
628 (VEX_W_0FFC_P_2): Likewise.
629 (VEX_W_0FFD_P_2): Likewise.
630 (VEX_W_0FFE_P_2): Likewise.
631 (VEX_W_0F3800_P_2): Likewise.
632 (VEX_W_0F3801_P_2): Likewise.
633 (VEX_W_0F3802_P_2): Likewise.
634 (VEX_W_0F3803_P_2): Likewise.
635 (VEX_W_0F3804_P_2): Likewise.
636 (VEX_W_0F3805_P_2): Likewise.
637 (VEX_W_0F3806_P_2): Likewise.
638 (VEX_W_0F3807_P_2): Likewise.
639 (VEX_W_0F3808_P_2): Likewise.
640 (VEX_W_0F3809_P_2): Likewise.
641 (VEX_W_0F380A_P_2): Likewise.
642 (VEX_W_0F380B_P_2): Likewise.
643 (VEX_W_0F3817_P_2): Likewise.
644 (VEX_W_0F381C_P_2): Likewise.
645 (VEX_W_0F381D_P_2): Likewise.
646 (VEX_W_0F381E_P_2): Likewise.
647 (VEX_W_0F3820_P_2): Likewise.
648 (VEX_W_0F3821_P_2): Likewise.
649 (VEX_W_0F3822_P_2): Likewise.
650 (VEX_W_0F3823_P_2): Likewise.
651 (VEX_W_0F3824_P_2): Likewise.
652 (VEX_W_0F3825_P_2): Likewise.
653 (VEX_W_0F3828_P_2): Likewise.
654 (VEX_W_0F3829_P_2): Likewise.
655 (VEX_W_0F382A_P_2_M_0): Likewise.
656 (VEX_W_0F382B_P_2): Likewise.
657 (VEX_W_0F3830_P_2): Likewise.
658 (VEX_W_0F3831_P_2): Likewise.
659 (VEX_W_0F3832_P_2): Likewise.
660 (VEX_W_0F3833_P_2): Likewise.
661 (VEX_W_0F3834_P_2): Likewise.
662 (VEX_W_0F3835_P_2): Likewise.
663 (VEX_W_0F3837_P_2): Likewise.
664 (VEX_W_0F3838_P_2): Likewise.
665 (VEX_W_0F3839_P_2): Likewise.
666 (VEX_W_0F383A_P_2): Likewise.
667 (VEX_W_0F383B_P_2): Likewise.
668 (VEX_W_0F383C_P_2): Likewise.
669 (VEX_W_0F383D_P_2): Likewise.
670 (VEX_W_0F383E_P_2): Likewise.
671 (VEX_W_0F383F_P_2): Likewise.
672 (VEX_W_0F3840_P_2): Likewise.
673 (VEX_W_0F3841_P_2): Likewise.
674 (VEX_W_0F38DB_P_2): Likewise.
675 (VEX_W_0F3A08_P_2): Likewise.
676 (VEX_W_0F3A09_P_2): Likewise.
677 (VEX_W_0F3A0A_P_2): Likewise.
678 (VEX_W_0F3A0B_P_2): Likewise.
679 (VEX_W_0F3A0C_P_2): Likewise.
680 (VEX_W_0F3A0D_P_2): Likewise.
681 (VEX_W_0F3A0E_P_2): Likewise.
682 (VEX_W_0F3A0F_P_2): Likewise.
683 (VEX_W_0F3A21_P_2): Likewise.
684 (VEX_W_0F3A40_P_2): Likewise.
685 (VEX_W_0F3A41_P_2): Likewise.
686 (VEX_W_0F3A42_P_2): Likewise.
687 (VEX_W_0F3A62_P_2): Likewise.
688 (VEX_W_0F3A63_P_2): Likewise.
689 (VEX_W_0F3ADF_P_2): Likewise.
690 (VEX_LEN_0F77_P_0): New.
691 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
692 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
693 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
694 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
695 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
696 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
697 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
698 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
699 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
700 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
701 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
702 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
703 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
704 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
705 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
706 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
707 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
708 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
709 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
710 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
711 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
712 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
713 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
714 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
715 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
716 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
717 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
718 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
719 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
720 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
721 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
722 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
723 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
724 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
725 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
726 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
727 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
728 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
729 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
730 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
731 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
732 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
733 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
734 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
735 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
736 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
737 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
738 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
739 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
740 (vex_table): Update VEX 0F28 and 0F29 entries.
741 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
742 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
743 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
744 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
745 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
746 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
747 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
748 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
749 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
750 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
751 VEX_LEN_0F3A0B_P_2 entries.
752 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
753 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
754 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
755 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
756 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
757 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
758 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
759 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
760 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
761 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
762 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
763 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
764 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
765 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
766 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
767 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
768 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
769 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
770 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
771 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
772 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
773 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
774 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
775 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
776 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
777 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
778 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
779 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
780 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
781 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
782 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
783 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
784 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
785 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
786 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
787 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
788 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
789 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
790 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
791 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
792 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
793 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
794 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
795 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
796 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
797 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
798 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
799 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
800 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
801 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
802 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
803 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
804 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
805 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
806 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
807 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
808 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
809 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
810 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
811 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
812 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
813 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
814 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
815 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
816 VEX_W_0F3ADF_P_2 entries.
817 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
818 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
819 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
821 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
823 * i386-opc.tbl (VexWIG): New.
824 Replace VexW=3 with VexWIG.
826 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
828 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
829 * i386-tbl.h: Regenerated.
831 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
834 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
835 VEX_LEN_0FD6_P_2 entries.
836 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
837 * i386-tbl.h: Regenerated.
839 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
842 * i386-opc.h (VEXWIG): New.
843 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
844 * i386-tbl.h: Regenerated.
846 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
849 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
850 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
851 * i386-dis.c (EXxEVexR64): New.
852 (evex_rounding_64_mode): Likewise.
853 (OP_Rounding): Handle evex_rounding_64_mode.
855 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
858 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
859 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
860 * i386-dis.c (Edqa): New.
861 (dqa_mode): Likewise.
862 (intel_operand_size): Handle dqa_mode as m_mode.
863 (OP_E_register): Handle dqa_mode as dq_mode.
864 (OP_E_memory): Set shift for dqa_mode based on address_mode.
866 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
868 * i386-dis.c (OP_E_memory): Reformat.
870 2018-09-14 Jan Beulich <jbeulich@suse.com>
872 * i386-opc.tbl (crc32): Fold byte and word forms.
873 * i386-tbl.h: Re-generate.
875 2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
877 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
878 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
879 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
880 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
881 * i386-tbl.h: Regenerated.
883 2018-09-13 Jan Beulich <jbeulich@suse.com>
885 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
887 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
888 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
889 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
890 * i386-tbl.h: Re-generate.
892 2018-09-13 Jan Beulich <jbeulich@suse.com>
894 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
896 * i386-tbl.h: Re-generate.
898 2018-09-13 Jan Beulich <jbeulich@suse.com>
900 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
902 * i386-tbl.h: Re-generate.
904 2018-09-13 Jan Beulich <jbeulich@suse.com>
906 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
908 * i386-tbl.h: Re-generate.
910 2018-09-13 Jan Beulich <jbeulich@suse.com>
912 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
914 * i386-tbl.h: Re-generate.
916 2018-09-13 Jan Beulich <jbeulich@suse.com>
918 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
920 * i386-tbl.h: Re-generate.
922 2018-09-13 Jan Beulich <jbeulich@suse.com>
924 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
926 * i386-tbl.h: Re-generate.
928 2018-09-13 Jan Beulich <jbeulich@suse.com>
930 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
931 * i386-tbl.h: Re-generate.
933 2018-09-13 Jan Beulich <jbeulich@suse.com>
935 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
936 * i386-tbl.h: Re-generate.
938 2018-09-13 Jan Beulich <jbeulich@suse.com>
940 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
942 * i386-tbl.h: Re-generate.
944 2018-09-13 Jan Beulich <jbeulich@suse.com>
946 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
948 * i386-tbl.h: Re-generate.
950 2018-09-13 Jan Beulich <jbeulich@suse.com>
952 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
953 * i386-tbl.h: Re-generate.
955 2018-09-13 Jan Beulich <jbeulich@suse.com>
957 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
958 * i386-tbl.h: Re-generate.
960 2018-09-13 Jan Beulich <jbeulich@suse.com>
962 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
963 * i386-tbl.h: Re-generate.
965 2018-09-13 Jan Beulich <jbeulich@suse.com>
967 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
969 * i386-tbl.h: Re-generate.
971 2018-09-13 Jan Beulich <jbeulich@suse.com>
973 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
975 * i386-tbl.h: Re-generate.
977 2018-09-13 Jan Beulich <jbeulich@suse.com>
979 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
981 * i386-tbl.h: Re-generate.
983 2018-09-13 Jan Beulich <jbeulich@suse.com>
985 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
986 * i386-tbl.h: Re-generate.
988 2018-09-13 Jan Beulich <jbeulich@suse.com>
990 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
991 * i386-tbl.h: Re-generate.
993 2018-09-13 Jan Beulich <jbeulich@suse.com>
995 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
996 * i386-tbl.h: Re-generate.
998 2018-09-13 Jan Beulich <jbeulich@suse.com>
1000 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
1001 (vpbroadcastw, rdpid): Drop NoRex64.
1002 * i386-tbl.h: Re-generate.
1004 2018-09-13 Jan Beulich <jbeulich@suse.com>
1006 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
1007 store templates, adding D.
1008 * i386-tbl.h: Re-generate.
1010 2018-09-13 Jan Beulich <jbeulich@suse.com>
1012 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
1013 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
1014 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
1015 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
1016 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
1017 Fold load and store templates where possible, adding D. Drop
1018 IgnoreSize where it was pointlessly present. Drop redundant
1020 * i386-tbl.h: Re-generate.
1022 2018-09-13 Jan Beulich <jbeulich@suse.com>
1024 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
1025 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
1026 (intel_operand_size): Handle v_bndmk_mode.
1027 (OP_E_memory): Likewise. Produce (bad) when also riprel.
1029 2018-09-08 John Darrington <john@darrington.wattle.id.au>
1031 * disassemble.c (ARCH_s12z): Define if ARCH_all.
1033 2018-08-31 Kito Cheng <kito@andestech.com>
1035 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
1036 compressed floating point instructions.
1038 2018-08-30 Kito Cheng <kito@andestech.com>
1040 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
1041 riscv_opcode.xlen_requirement.
1042 * riscv-opc.c (riscv_opcodes): Update for struct change.
1044 2018-08-29 Martin Aberg <maberg@gaisler.com>
1046 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
1047 psr (PWRPSR) instruction.
1049 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1051 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
1053 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1055 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
1057 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1059 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
1060 loongson3a as an alias of gs464 for compatibility.
1061 * mips-opc.c (mips_opcodes): Change Comments.
1063 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1065 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
1067 (print_mips_disassembler_options): Document -M loongson-ext.
1068 * mips-opc.c (LEXT2): New macro.
1069 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
1071 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1073 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
1075 (parse_mips_ase_option): Handle -M loongson-ext option.
1076 (print_mips_disassembler_options): Document -M loongson-ext.
1077 * mips-opc.c (IL3A): Delete.
1078 * mips-opc.c (LEXT): New macro.
1079 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
1082 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1084 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
1086 (parse_mips_ase_option): Handle -M loongson-cam option.
1087 (print_mips_disassembler_options): Document -M loongson-cam.
1088 * mips-opc.c (LCAM): New macro.
1089 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
1092 2018-08-21 Alan Modra <amodra@gmail.com>
1094 * ppc-dis.c (operand_value_powerpc): Init "invalid".
1095 (skip_optional_operands): Count optional operands, and update
1096 ppc_optional_operand_value call.
1097 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
1098 (extract_vlensi): Likewise.
1099 (extract_fxm): Return default value for missing optional operand.
1100 (extract_ls, extract_raq, extract_tbr): Likewise.
1101 (insert_sxl, extract_sxl): New functions.
1102 (insert_esync, extract_esync): Remove Power9 handling and simplify.
1103 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
1104 flag and extra entry.
1105 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
1108 2018-08-20 Alan Modra <amodra@gmail.com>
1110 * sh-opc.h (MASK): Simplify.
1112 2018-08-18 John Darrington <john@darrington.wattle.id.au>
1114 * s12z-dis.c (bm_decode): Deal with cases where the mode is
1115 BM_RESERVED0 or BM_RESERVED1
1116 (bm_rel_decode, bm_n_bytes): Ditto.
1118 2018-08-18 John Darrington <john@darrington.wattle.id.au>
1122 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
1124 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1125 address with the addr32 prefix and without base nor index
1128 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
1130 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1131 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1132 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1133 (cpu_flags): Add CpuCMOV and CpuFXSR.
1134 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1135 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
1136 * i386-init.h: Regenerated.
1137 * i386-tbl.h: Likewise.
1139 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
1141 * arc-regs.h: Update auxiliary registers.
1143 2018-08-06 Jan Beulich <jbeulich@suse.com>
1145 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1146 (RegIP, RegIZ): Define.
1147 * i386-reg.tbl: Adjust comments.
1148 (rip): Use Qword instead of BaseIndex. Use RegIP.
1149 (eip): Use Dword instead of BaseIndex. Use RegIP.
1150 (riz): Add Qword. Use RegIZ.
1151 (eiz): Add Dword. Use RegIZ.
1152 * i386-tbl.h: Re-generate.
1154 2018-08-03 Jan Beulich <jbeulich@suse.com>
1156 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1157 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1158 vpmovzxdq, vpmovzxwd): Remove NoRex64.
1159 * i386-tbl.h: Re-generate.
1161 2018-08-03 Jan Beulich <jbeulich@suse.com>
1163 * i386-gen.c (operand_types): Remove Mem field.
1164 * i386-opc.h (union i386_operand_type): Remove mem field.
1165 * i386-init.h, i386-tbl.h: Re-generate.
1167 2018-08-01 Alan Modra <amodra@gmail.com>
1169 * po/POTFILES.in: Regenerate.
1171 2018-07-31 Nick Clifton <nickc@redhat.com>
1173 * po/sv.po: Updated Swedish translation.
1175 2018-07-31 Jan Beulich <jbeulich@suse.com>
1177 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1178 * i386-init.h, i386-tbl.h: Re-generate.
1180 2018-07-31 Jan Beulich <jbeulich@suse.com>
1182 * i386-opc.h (ZEROING_MASKING) Rename to ...
1183 (DYNAMIC_MASKING): ... this. Adjust comment.
1184 * i386-opc.tbl (MaskingMorZ): Define.
1185 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1186 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1187 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1188 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1189 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1190 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1191 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1192 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1193 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1195 2018-07-31 Jan Beulich <jbeulich@suse.com>
1197 * i386-opc.tbl: Use element rather than vector size for AVX512*
1198 scatter/gather insns.
1199 * i386-tbl.h: Re-generate.
1201 2018-07-31 Jan Beulich <jbeulich@suse.com>
1203 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1204 (cpu_flags): Drop CpuVREX.
1205 * i386-opc.h (CpuVREX): Delete.
1206 (union i386_cpu_flags): Remove cpuvrex.
1207 * i386-init.h, i386-tbl.h: Re-generate.
1209 2018-07-30 Jim Wilson <jimw@sifive.com>
1211 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1213 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1215 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
1217 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1218 * Makefile.in: Regenerated.
1219 * configure.ac: Add C-SKY.
1220 * configure: Regenerated.
1221 * csky-dis.c: New file.
1222 * csky-opc.h: New file.
1223 * disassemble.c (ARCH_csky): Define.
1224 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1225 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1227 2018-07-27 Alan Modra <amodra@gmail.com>
1229 * ppc-opc.c (insert_sprbat): Correct function parameter and
1231 (extract_sprbat): Likewise, variable too.
1233 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
1234 Alan Modra <amodra@gmail.com>
1236 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1237 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1238 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1239 support disjointed BAT.
1240 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
1241 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1242 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1244 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
1245 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1247 * i386-gen.c (adjust_broadcast_modifier): New function.
1248 (process_i386_opcode_modifier): Add an argument for operands.
1249 Adjust the Broadcast value based on operands.
1250 (output_i386_opcode): Pass operand_types to
1251 process_i386_opcode_modifier.
1252 (process_i386_opcodes): Pass NULL as operands to
1253 process_i386_opcode_modifier.
1254 * i386-opc.h (BYTE_BROADCAST): New.
1255 (WORD_BROADCAST): Likewise.
1256 (DWORD_BROADCAST): Likewise.
1257 (QWORD_BROADCAST): Likewise.
1258 (i386_opcode_modifier): Expand broadcast to 3 bits.
1259 * i386-tbl.h: Regenerated.
1261 2018-07-24 Alan Modra <amodra@gmail.com>
1264 * or1k-desc.h: Regenerate.
1266 2018-07-24 Jan Beulich <jbeulich@suse.com>
1268 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1269 vcvtusi2ss, and vcvtusi2sd.
1270 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1271 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1272 * i386-tbl.h: Re-generate.
1274 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1276 * arc-opc.c (extract_w6): Fix extending the sign.
1278 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1280 * arc-tbl.h (vewt): Allow it for ARC EM family.
1282 2018-07-23 Alan Modra <amodra@gmail.com>
1285 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1286 opcode variants for mtspr/mfspr encodings.
1288 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
1289 Maciej W. Rozycki <macro@mips.com>
1291 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1292 loongson3a descriptors.
1293 (parse_mips_ase_option): Handle -M loongson-mmi option.
1294 (print_mips_disassembler_options): Document -M loongson-mmi.
1295 * mips-opc.c (LMMI): New macro.
1296 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1299 2018-07-19 Jan Beulich <jbeulich@suse.com>
1301 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1302 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1303 IgnoreSize and [XYZ]MMword where applicable.
1304 * i386-tbl.h: Re-generate.
1306 2018-07-19 Jan Beulich <jbeulich@suse.com>
1308 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1309 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1310 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1311 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1312 * i386-tbl.h: Re-generate.
1314 2018-07-19 Jan Beulich <jbeulich@suse.com>
1316 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1317 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1318 VPCLMULQDQ templates into their respective AVX512VL counterparts
1319 where possible, using Disp8ShiftVL and CheckRegSize instead of
1320 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1321 * i386-tbl.h: Re-generate.
1323 2018-07-19 Jan Beulich <jbeulich@suse.com>
1325 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1326 AVX512VL counterparts where possible, using Disp8ShiftVL and
1327 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1328 IgnoreSize) as appropriate.
1329 * i386-tbl.h: Re-generate.
1331 2018-07-19 Jan Beulich <jbeulich@suse.com>
1333 * i386-opc.tbl: Fold AVX512BW templates into their respective
1334 AVX512VL counterparts where possible, using Disp8ShiftVL and
1335 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1336 IgnoreSize) as appropriate.
1337 * i386-tbl.h: Re-generate.
1339 2018-07-19 Jan Beulich <jbeulich@suse.com>
1341 * i386-opc.tbl: Fold AVX512CD templates into their respective
1342 AVX512VL counterparts where possible, using Disp8ShiftVL and
1343 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1344 IgnoreSize) as appropriate.
1345 * i386-tbl.h: Re-generate.
1347 2018-07-19 Jan Beulich <jbeulich@suse.com>
1349 * i386-opc.h (DISP8_SHIFT_VL): New.
1350 * i386-opc.tbl (Disp8ShiftVL): Define.
1351 (various): Fold AVX512VL templates into their respective
1352 AVX512F counterparts where possible, using Disp8ShiftVL and
1353 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1354 IgnoreSize) as appropriate.
1355 * i386-tbl.h: Re-generate.
1357 2018-07-19 Jan Beulich <jbeulich@suse.com>
1359 * Makefile.am: Change dependencies and rule for
1360 $(srcdir)/i386-init.h.
1361 * Makefile.in: Re-generate.
1362 * i386-gen.c (process_i386_opcodes): New local variable
1363 "marker". Drop opening of input file. Recognize marker and line
1365 * i386-opc.tbl (OPCODE_I386_H): Define.
1366 (i386-opc.h): Include it.
1369 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1372 * i386-opc.h (Byte): Update comments.
1378 (Xmmword): Likewise.
1379 (Ymmword): Likewise.
1380 (Zmmword): Likewise.
1381 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1383 * i386-tbl.h: Regenerated.
1385 2018-07-12 Sudakshina Das <sudi.das@arm.com>
1387 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1388 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1389 * aarch64-asm-2.c: Regenerate.
1390 * aarch64-dis-2.c: Regenerate.
1391 * aarch64-opc-2.c: Regenerate.
1393 2018-07-12 Tamar Christina <tamar.christina@arm.com>
1396 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1397 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1398 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1399 sqdmulh, sqrdmulh): Use Em16.
1401 2018-07-11 Sudakshina Das <sudi.das@arm.com>
1403 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1404 csdb together with them.
1405 (thumb32_opcodes): Likewise.
1407 2018-07-11 Jan Beulich <jbeulich@suse.com>
1409 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1410 requiring 32-bit registers as operands 2 and 3. Improve
1412 (mwait, mwaitx): Fold templates. Improve comments.
1413 OPERAND_TYPE_INOUTPORTREG.
1414 * i386-tbl.h: Re-generate.
1416 2018-07-11 Jan Beulich <jbeulich@suse.com>
1418 * i386-gen.c (operand_type_init): Remove
1419 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1420 OPERAND_TYPE_INOUTPORTREG.
1421 * i386-init.h: Re-generate.
1423 2018-07-11 Jan Beulich <jbeulich@suse.com>
1425 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1426 (wrssq, wrussq): Add Qword.
1427 * i386-tbl.h: Re-generate.
1429 2018-07-11 Jan Beulich <jbeulich@suse.com>
1431 * i386-opc.h: Rename OTMax to OTNum.
1432 (OTNumOfUints): Adjust calculation.
1433 (OTUnused): Directly alias to OTNum.
1435 2018-07-09 Maciej W. Rozycki <macro@mips.com>
1437 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1439 (lea_reg_xys): Likewise.
1440 (print_insn_loop_primitive): Rename `reg' local variable to
1443 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1446 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1448 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1451 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1452 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1454 2018-07-02 Maciej W. Rozycki <macro@mips.com>
1457 * mips-dis.c (mips_option_arg_t): New enumeration.
1458 (mips_options): New variable.
1459 (disassembler_options_mips): New function.
1460 (print_mips_disassembler_options): Reimplement in terms of
1461 `disassembler_options_mips'.
1462 * arm-dis.c (disassembler_options_arm): Adapt to using the
1463 `disasm_options_and_args_t' structure.
1464 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1465 * s390-dis.c (disassembler_options_s390): Likewise.
1467 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1469 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1471 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1472 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1473 * testsuite/ld-arm/tls-longplt.d: Likewise.
1475 2018-06-29 Tamar Christina <tamar.christina@arm.com>
1478 * aarch64-asm-2.c: Regenerate.
1479 * aarch64-dis-2.c: Likewise.
1480 * aarch64-opc-2.c: Likewise.
1481 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1482 * aarch64-opc.c (operand_general_constraint_met_p,
1483 aarch64_print_operand): Likewise.
1484 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1485 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1487 (AARCH64_OPERANDS): Add Em2.
1489 2018-06-26 Nick Clifton <nickc@redhat.com>
1491 * po/uk.po: Updated Ukranian translation.
1492 * po/de.po: Updated German translation.
1493 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1495 2018-06-26 Nick Clifton <nickc@redhat.com>
1497 * nfp-dis.c: Fix spelling mistake.
1499 2018-06-24 Nick Clifton <nickc@redhat.com>
1501 * configure: Regenerate.
1502 * po/opcodes.pot: Regenerate.
1504 2018-06-24 Nick Clifton <nickc@redhat.com>
1506 2.31 branch created.
1508 2018-06-19 Tamar Christina <tamar.christina@arm.com>
1510 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1511 * aarch64-asm-2.c: Regenerate.
1512 * aarch64-dis-2.c: Likewise.
1514 2018-06-21 Maciej W. Rozycki <macro@mips.com>
1516 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1517 `-M ginv' option description.
1519 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1522 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1525 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1527 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1528 * configure.ac: Remove AC_PREREQ.
1529 * Makefile.in: Re-generate.
1530 * aclocal.m4: Re-generate.
1531 * configure: Re-generate.
1533 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1535 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1536 mips64r6 descriptors.
1537 (parse_mips_ase_option): Handle -Mginv option.
1538 (print_mips_disassembler_options): Document -Mginv.
1539 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1541 (mips_opcodes): Define ginvi and ginvt.
1543 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1544 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1546 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1547 * mips-opc.c (CRC, CRC64): New macros.
1548 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1549 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1552 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1555 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1556 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1558 2018-06-06 Alan Modra <amodra@gmail.com>
1560 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1561 setjmp. Move init for some other vars later too.
1563 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1565 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1566 (dis_private): Add new fields for property section tracking.
1567 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1568 (xtensa_instruction_fits): New functions.
1569 (fetch_data): Bump minimal fetch size to 4.
1570 (print_insn_xtensa): Make struct dis_private static.
1571 Load and prepare property table on section change.
1572 Don't disassemble literals. Don't disassemble instructions that
1573 cross property table boundaries.
1575 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1577 * configure: Regenerated.
1579 2018-06-01 Jan Beulich <jbeulich@suse.com>
1581 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1582 * i386-tbl.h: Re-generate.
1584 2018-06-01 Jan Beulich <jbeulich@suse.com>
1586 * i386-opc.tbl (sldt, str): Add NoRex64.
1587 * i386-tbl.h: Re-generate.
1589 2018-06-01 Jan Beulich <jbeulich@suse.com>
1591 * i386-opc.tbl (invpcid): Add Oword.
1592 * i386-tbl.h: Re-generate.
1594 2018-06-01 Alan Modra <amodra@gmail.com>
1596 * sysdep.h (_bfd_error_handler): Don't declare.
1597 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1598 * rl78-decode.opc: Likewise.
1599 * msp430-decode.c: Regenerate.
1600 * rl78-decode.c: Regenerate.
1602 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1604 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1605 * i386-init.h : Regenerated.
1607 2018-05-25 Alan Modra <amodra@gmail.com>
1609 * Makefile.in: Regenerate.
1610 * po/POTFILES.in: Regenerate.
1612 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1614 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1615 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1616 (insert_bab, extract_bab, insert_btab, extract_btab,
1617 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1618 (BAT, BBA VBA RBS XB6S): Delete macros.
1619 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1620 (BB, BD, RBX, XC6): Update for new macros.
1621 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1622 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1623 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1624 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1626 2018-05-18 John Darrington <john@darrington.wattle.id.au>
1628 * Makefile.am: Add support for s12z architecture.
1629 * configure.ac: Likewise.
1630 * disassemble.c: Likewise.
1631 * disassemble.h: Likewise.
1632 * Makefile.in: Regenerate.
1633 * configure: Regenerate.
1634 * s12z-dis.c: New file.
1637 2018-05-18 Alan Modra <amodra@gmail.com>
1639 * nfp-dis.c: Don't #include libbfd.h.
1640 (init_nfp3200_priv): Use bfd_get_section_contents.
1641 (nit_nfp6000_mecsr_sec): Likewise.
1643 2018-05-17 Nick Clifton <nickc@redhat.com>
1645 * po/zh_CN.po: Updated simplified Chinese translation.
1647 2018-05-16 Tamar Christina <tamar.christina@arm.com>
1650 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1651 * aarch64-dis-2.c: Regenerate.
1653 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1656 * aarch64-asm.c (opintl.h): Include.
1657 (aarch64_ins_sysreg): Enforce read/write constraints.
1658 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1659 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1660 (F_REG_READ, F_REG_WRITE): New.
1661 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1662 AARCH64_OPND_SYSREG.
1663 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1664 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1665 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1666 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1667 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1668 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1669 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1670 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1671 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1672 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1673 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1674 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1675 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1676 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1677 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1678 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1679 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1681 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1684 * aarch64-dis.c (no_notes: New.
1685 (parse_aarch64_dis_option): Support notes.
1686 (aarch64_decode_insn, print_operands): Likewise.
1687 (print_aarch64_disassembler_options): Document notes.
1688 * aarch64-opc.c (aarch64_print_operand): Support notes.
1690 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1693 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1694 and take error struct.
1695 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1696 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1697 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1698 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1699 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1700 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1701 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1702 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1703 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1704 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1705 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1706 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1707 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1708 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1709 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1710 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1711 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1712 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1713 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1714 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1715 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1716 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1717 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1718 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1719 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1720 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1721 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1722 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1723 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1724 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1725 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1726 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1727 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1728 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1729 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1730 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1731 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1732 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1733 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1734 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1735 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1736 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1737 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1738 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1739 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1740 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1741 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1742 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1743 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1744 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1745 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1746 (determine_disassembling_preference, aarch64_decode_insn,
1747 print_insn_aarch64_word, print_insn_data): Take errors struct.
1748 (print_insn_aarch64): Use errors.
1749 * aarch64-asm-2.c: Regenerate.
1750 * aarch64-dis-2.c: Regenerate.
1751 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1752 boolean in aarch64_insert_operan.
1753 (print_operand_extractor): Likewise.
1754 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1756 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
1758 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1760 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1762 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1764 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1766 * cr16-opc.c (cr16_instruction): Comment typo fix.
1767 * hppa-dis.c (print_insn_hppa): Likewise.
1769 2018-05-08 Jim Wilson <jimw@sifive.com>
1771 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1772 (match_c_slli64, match_srxi_as_c_srxi): New.
1773 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1774 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1775 <c.slli, c.srli, c.srai>: Use match_s_slli.
1776 <c.slli64, c.srli64, c.srai64>: New.
1778 2018-05-08 Alan Modra <amodra@gmail.com>
1780 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1781 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1782 partition opcode space for index lookup.
1784 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1786 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1787 <insn_length>: ...with this. Update usage.
1788 Remove duplicate call to *info->memory_error_func.
1790 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1791 H.J. Lu <hongjiu.lu@intel.com>
1793 * i386-dis.c (Gva): New.
1794 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1795 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1796 (prefix_table): New instructions (see prefix above).
1797 (mod_table): New instructions (see prefix above).
1798 (OP_G): Handle va_mode.
1799 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1800 CPU_MOVDIR64B_FLAGS.
1801 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1802 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1803 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1804 * i386-opc.tbl: Add movidir{i,64b}.
1805 * i386-init.h: Regenerated.
1806 * i386-tbl.h: Likewise.
1808 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1810 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1812 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1813 (AddrPrefixOpReg): This.
1814 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1815 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1817 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1819 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1820 (vle_num_opcodes): Likewise.
1821 (spe2_num_opcodes): Likewise.
1822 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1823 initialization loop.
1824 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1825 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1828 2018-05-01 Tamar Christina <tamar.christina@arm.com>
1830 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1832 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
1834 Makefile.am: Added nfp-dis.c.
1835 configure.ac: Added bfd_nfp_arch.
1836 disassemble.h: Added print_insn_nfp prototype.
1837 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1838 nfp-dis.c: New, for NFP support.
1839 po/POTFILES.in: Added nfp-dis.c to the list.
1840 Makefile.in: Regenerate.
1841 configure: Regenerate.
1843 2018-04-26 Jan Beulich <jbeulich@suse.com>
1845 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1846 templates into their base ones.
1847 * i386-tlb.h: Re-generate.
1849 2018-04-26 Jan Beulich <jbeulich@suse.com>
1851 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1852 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1853 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1854 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1855 * i386-init.h: Re-generate.
1857 2018-04-26 Jan Beulich <jbeulich@suse.com>
1859 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1860 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1861 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1862 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1864 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1866 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1868 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1869 cpuregzmm, and cpuregmask.
1870 * i386-init.h: Re-generate.
1871 * i386-tbl.h: Re-generate.
1873 2018-04-26 Jan Beulich <jbeulich@suse.com>
1875 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1876 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1877 * i386-init.h: Re-generate.
1879 2018-04-26 Jan Beulich <jbeulich@suse.com>
1881 * i386-gen.c (VexImmExt): Delete.
1882 * i386-opc.h (VexImmExt, veximmext): Delete.
1883 * i386-opc.tbl: Drop all VexImmExt uses.
1884 * i386-tlb.h: Re-generate.
1886 2018-04-25 Jan Beulich <jbeulich@suse.com>
1888 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1889 register-only forms.
1890 * i386-tlb.h: Re-generate.
1892 2018-04-25 Tamar Christina <tamar.christina@arm.com>
1894 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1896 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1898 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1900 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1901 (cpu_flags): Add CpuCLDEMOTE.
1902 * i386-init.h: Regenerate.
1903 * i386-opc.h (enum): Add CpuCLDEMOTE,
1904 (i386_cpu_flags): Add cpucldemote.
1905 * i386-opc.tbl: Add cldemote.
1906 * i386-tbl.h: Regenerate.
1908 2018-04-16 Alan Modra <amodra@gmail.com>
1910 * Makefile.am: Remove sh5 and sh64 support.
1911 * configure.ac: Likewise.
1912 * disassemble.c: Likewise.
1913 * disassemble.h: Likewise.
1914 * sh-dis.c: Likewise.
1915 * sh64-dis.c: Delete.
1916 * sh64-opc.c: Delete.
1917 * sh64-opc.h: Delete.
1918 * Makefile.in: Regenerate.
1919 * configure: Regenerate.
1920 * po/POTFILES.in: Regenerate.
1922 2018-04-16 Alan Modra <amodra@gmail.com>
1924 * Makefile.am: Remove w65 support.
1925 * configure.ac: Likewise.
1926 * disassemble.c: Likewise.
1927 * disassemble.h: Likewise.
1928 * w65-dis.c: Delete.
1929 * w65-opc.h: Delete.
1930 * Makefile.in: Regenerate.
1931 * configure: Regenerate.
1932 * po/POTFILES.in: Regenerate.
1934 2018-04-16 Alan Modra <amodra@gmail.com>
1936 * configure.ac: Remove we32k support.
1937 * configure: Regenerate.
1939 2018-04-16 Alan Modra <amodra@gmail.com>
1941 * Makefile.am: Remove m88k support.
1942 * configure.ac: Likewise.
1943 * disassemble.c: Likewise.
1944 * disassemble.h: Likewise.
1945 * m88k-dis.c: Delete.
1946 * Makefile.in: Regenerate.
1947 * configure: Regenerate.
1948 * po/POTFILES.in: Regenerate.
1950 2018-04-16 Alan Modra <amodra@gmail.com>
1952 * Makefile.am: Remove i370 support.
1953 * configure.ac: Likewise.
1954 * disassemble.c: Likewise.
1955 * disassemble.h: Likewise.
1956 * i370-dis.c: Delete.
1957 * i370-opc.c: Delete.
1958 * Makefile.in: Regenerate.
1959 * configure: Regenerate.
1960 * po/POTFILES.in: Regenerate.
1962 2018-04-16 Alan Modra <amodra@gmail.com>
1964 * Makefile.am: Remove h8500 support.
1965 * configure.ac: Likewise.
1966 * disassemble.c: Likewise.
1967 * disassemble.h: Likewise.
1968 * h8500-dis.c: Delete.
1969 * h8500-opc.h: Delete.
1970 * Makefile.in: Regenerate.
1971 * configure: Regenerate.
1972 * po/POTFILES.in: Regenerate.
1974 2018-04-16 Alan Modra <amodra@gmail.com>
1976 * configure.ac: Remove tahoe support.
1977 * configure: Regenerate.
1979 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1981 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1983 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1985 * i386-tbl.h: Regenerated.
1987 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1989 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1990 PREFIX_MOD_1_0FAE_REG_6.
1992 (OP_E_register): Use va_mode.
1993 * i386-dis-evex.h (prefix_table):
1994 New instructions (see prefixes above).
1995 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1996 (cpu_flags): Likewise.
1997 * i386-opc.h (enum): Likewise.
1998 (i386_cpu_flags): Likewise.
1999 * i386-opc.tbl: Add umonitor, umwait, tpause.
2000 * i386-init.h: Regenerate.
2001 * i386-tbl.h: Likewise.
2003 2018-04-11 Alan Modra <amodra@gmail.com>
2005 * opcodes/i860-dis.c: Delete.
2006 * opcodes/i960-dis.c: Delete.
2007 * Makefile.am: Remove i860 and i960 support.
2008 * configure.ac: Likewise.
2009 * disassemble.c: Likewise.
2010 * disassemble.h: Likewise.
2011 * Makefile.in: Regenerate.
2012 * configure: Regenerate.
2013 * po/POTFILES.in: Regenerate.
2015 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
2018 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
2020 (print_insn): Clear vex instead of vex.evex.
2022 2018-04-04 Nick Clifton <nickc@redhat.com>
2024 * po/es.po: Updated Spanish translation.
2026 2018-03-28 Jan Beulich <jbeulich@suse.com>
2028 * i386-gen.c (opcode_modifiers): Delete VecESize.
2029 * i386-opc.h (VecESize): Delete.
2030 (struct i386_opcode_modifier): Delete vecesize.
2031 * i386-opc.tbl: Drop VecESize.
2032 * i386-tlb.h: Re-generate.
2034 2018-03-28 Jan Beulich <jbeulich@suse.com>
2036 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
2037 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
2038 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
2039 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
2040 * i386-tlb.h: Re-generate.
2042 2018-03-28 Jan Beulich <jbeulich@suse.com>
2044 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
2046 * i386-tlb.h: Re-generate.
2048 2018-03-28 Jan Beulich <jbeulich@suse.com>
2050 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
2051 (vex_len_table): Drop Y for vcvt*2si.
2052 (putop): Replace plain 'Y' handling by abort().
2054 2018-03-28 Nick Clifton <nickc@redhat.com>
2057 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
2058 instructions with only a base address register.
2059 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
2060 handle AARHC64_OPND_SVE_ADDR_R.
2061 (aarch64_print_operand): Likewise.
2062 * aarch64-asm-2.c: Regenerate.
2063 * aarch64_dis-2.c: Regenerate.
2064 * aarch64-opc-2.c: Regenerate.
2066 2018-03-22 Jan Beulich <jbeulich@suse.com>
2068 * i386-opc.tbl: Drop VecESize from register only insn forms and
2069 memory forms not allowing broadcast.
2070 * i386-tlb.h: Re-generate.
2072 2018-03-22 Jan Beulich <jbeulich@suse.com>
2074 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
2075 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
2076 sha256*): Drop Disp<N>.
2078 2018-03-22 Jan Beulich <jbeulich@suse.com>
2080 * i386-dis.c (EbndS, bnd_swap_mode): New.
2081 (prefix_table): Use EbndS.
2082 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
2083 * i386-opc.tbl (bndmov): Move misplaced Load.
2084 * i386-tlb.h: Re-generate.
2086 2018-03-22 Jan Beulich <jbeulich@suse.com>
2088 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
2089 templates allowing memory operands and folded ones for register
2091 * i386-tlb.h: Re-generate.
2093 2018-03-22 Jan Beulich <jbeulich@suse.com>
2095 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
2096 256-bit templates. Drop redundant leftover Disp<N>.
2097 * i386-tlb.h: Re-generate.
2099 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
2101 * riscv-opc.c (riscv_insn_types): New.
2103 2018-03-13 Nick Clifton <nickc@redhat.com>
2105 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2107 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2109 * i386-opc.tbl: Add Optimize to clr.
2110 * i386-tbl.h: Regenerated.
2112 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2114 * i386-gen.c (opcode_modifiers): Remove OldGcc.
2115 * i386-opc.h (OldGcc): Removed.
2116 (i386_opcode_modifier): Remove oldgcc.
2117 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2118 instructions for old (<= 2.8.1) versions of gcc.
2119 * i386-tbl.h: Regenerated.
2121 2018-03-08 Jan Beulich <jbeulich@suse.com>
2123 * i386-opc.h (EVEXDYN): New.
2124 * i386-opc.tbl: Fold various AVX512VL templates.
2125 * i386-tlb.h: Re-generate.
2127 2018-03-08 Jan Beulich <jbeulich@suse.com>
2129 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2130 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2131 vpexpandd, vpexpandq): Fold AFX512VF templates.
2132 * i386-tlb.h: Re-generate.
2134 2018-03-08 Jan Beulich <jbeulich@suse.com>
2136 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2137 Fold 128- and 256-bit VEX-encoded templates.
2138 * i386-tlb.h: Re-generate.
2140 2018-03-08 Jan Beulich <jbeulich@suse.com>
2142 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2143 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2144 vpexpandd, vpexpandq): Fold AVX512F templates.
2145 * i386-tlb.h: Re-generate.
2147 2018-03-08 Jan Beulich <jbeulich@suse.com>
2149 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2150 64-bit templates. Drop Disp<N>.
2151 * i386-tlb.h: Re-generate.
2153 2018-03-08 Jan Beulich <jbeulich@suse.com>
2155 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2156 and 256-bit templates.
2157 * i386-tlb.h: Re-generate.
2159 2018-03-08 Jan Beulich <jbeulich@suse.com>
2161 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2162 * i386-tlb.h: Re-generate.
2164 2018-03-08 Jan Beulich <jbeulich@suse.com>
2166 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2168 * i386-tlb.h: Re-generate.
2170 2018-03-08 Jan Beulich <jbeulich@suse.com>
2172 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2173 * i386-tlb.h: Re-generate.
2175 2018-03-08 Jan Beulich <jbeulich@suse.com>
2177 * i386-gen.c (opcode_modifiers): Delete FloatD.
2178 * i386-opc.h (FloatD): Delete.
2179 (struct i386_opcode_modifier): Delete floatd.
2180 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2182 * i386-tlb.h: Re-generate.
2184 2018-03-08 Jan Beulich <jbeulich@suse.com>
2186 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2188 2018-03-08 Jan Beulich <jbeulich@suse.com>
2190 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2191 * i386-tlb.h: Re-generate.
2193 2018-03-08 Jan Beulich <jbeulich@suse.com>
2195 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2197 * i386-tlb.h: Re-generate.
2199 2018-03-07 Alan Modra <amodra@gmail.com>
2201 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2203 * disassemble.h (print_insn_rs6000): Delete.
2204 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2205 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2206 (print_insn_rs6000): Delete.
2208 2018-03-03 Alan Modra <amodra@gmail.com>
2210 * sysdep.h (opcodes_error_handler): Define.
2211 (_bfd_error_handler): Declare.
2212 * Makefile.am: Remove stray #.
2213 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
2215 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2216 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2217 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2218 opcodes_error_handler to print errors. Standardize error messages.
2219 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2220 and include opintl.h.
2221 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2222 * i386-gen.c: Standardize error messages.
2223 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2224 * Makefile.in: Regenerate.
2225 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2226 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2227 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2228 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2229 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2230 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2231 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2232 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2233 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2234 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2235 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2236 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2237 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2239 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
2241 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2242 vpsub[bwdq] instructions.
2243 * i386-tbl.h: Regenerated.
2245 2018-03-01 Alan Modra <amodra@gmail.com>
2247 * configure.ac (ALL_LINGUAS): Sort.
2248 * configure: Regenerate.
2250 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
2252 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2253 macro by assignements.
2255 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
2258 * i386-gen.c (opcode_modifiers): Add Optimize.
2259 * i386-opc.h (Optimize): New enum.
2260 (i386_opcode_modifier): Add optimize.
2261 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2262 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2263 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2264 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2265 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2267 * i386-tbl.h: Regenerated.
2269 2018-02-26 Alan Modra <amodra@gmail.com>
2271 * crx-dis.c (getregliststring): Allocate a large enough buffer
2272 to silence false positive gcc8 warning.
2274 2018-02-22 Shea Levy <shea@shealevy.com>
2276 * disassemble.c (ARCH_riscv): Define if ARCH_all.
2278 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
2280 * i386-opc.tbl: Add {rex},
2281 * i386-tbl.h: Regenerated.
2283 2018-02-20 Maciej W. Rozycki <macro@mips.com>
2285 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2286 (mips16_opcodes): Replace `M' with `m' for "restore".
2288 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
2290 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2292 2018-02-13 Maciej W. Rozycki <macro@mips.com>
2294 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2295 variable to `function_index'.
2297 2018-02-13 Nick Clifton <nickc@redhat.com>
2300 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2301 about truncation of printing.
2303 2018-02-12 Henry Wong <henry@stuffedcow.net>
2305 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2307 2018-02-05 Nick Clifton <nickc@redhat.com>
2309 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2311 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2313 * i386-dis.c (enum): Add pconfig.
2314 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2315 (cpu_flags): Add CpuPCONFIG.
2316 * i386-opc.h (enum): Add CpuPCONFIG.
2317 (i386_cpu_flags): Add cpupconfig.
2318 * i386-opc.tbl: Add PCONFIG instruction.
2319 * i386-init.h: Regenerate.
2320 * i386-tbl.h: Likewise.
2322 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2324 * i386-dis.c (enum): Add PREFIX_0F09.
2325 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2326 (cpu_flags): Add CpuWBNOINVD.
2327 * i386-opc.h (enum): Add CpuWBNOINVD.
2328 (i386_cpu_flags): Add cpuwbnoinvd.
2329 * i386-opc.tbl: Add WBNOINVD instruction.
2330 * i386-init.h: Regenerate.
2331 * i386-tbl.h: Likewise.
2333 2018-01-17 Jim Wilson <jimw@sifive.com>
2335 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2337 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2339 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2340 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2341 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2342 (cpu_flags): Add CpuIBT, CpuSHSTK.
2343 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2344 (i386_cpu_flags): Add cpuibt, cpushstk.
2345 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2346 * i386-init.h: Regenerate.
2347 * i386-tbl.h: Likewise.
2349 2018-01-16 Nick Clifton <nickc@redhat.com>
2351 * po/pt_BR.po: Updated Brazilian Portugese translation.
2352 * po/de.po: Updated German translation.
2354 2018-01-15 Jim Wilson <jimw@sifive.com>
2356 * riscv-opc.c (match_c_nop): New.
2357 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2359 2018-01-15 Nick Clifton <nickc@redhat.com>
2361 * po/uk.po: Updated Ukranian translation.
2363 2018-01-13 Nick Clifton <nickc@redhat.com>
2365 * po/opcodes.pot: Regenerated.
2367 2018-01-13 Nick Clifton <nickc@redhat.com>
2369 * configure: Regenerate.
2371 2018-01-13 Nick Clifton <nickc@redhat.com>
2373 2.30 branch created.
2375 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2377 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2378 * i386-tbl.h: Regenerate.
2380 2018-01-10 Jan Beulich <jbeulich@suse.com>
2382 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2383 * i386-tbl.h: Re-generate.
2385 2018-01-10 Jan Beulich <jbeulich@suse.com>
2387 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2388 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2389 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2390 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2391 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2392 Disp8MemShift of AVX512VL forms.
2393 * i386-tbl.h: Re-generate.
2395 2018-01-09 Jim Wilson <jimw@sifive.com>
2397 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2398 then the hi_addr value is zero.
2400 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2402 * arm-dis.c (arm_opcodes): Add csdb.
2403 (thumb32_opcodes): Add csdb.
2405 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2407 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2408 * aarch64-asm-2.c: Regenerate.
2409 * aarch64-dis-2.c: Regenerate.
2410 * aarch64-opc-2.c: Regenerate.
2412 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2415 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2416 Remove AVX512 vmovd with 64-bit operands.
2417 * i386-tbl.h: Regenerated.
2419 2018-01-05 Jim Wilson <jimw@sifive.com>
2421 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2424 2018-01-03 Alan Modra <amodra@gmail.com>
2426 Update year range in copyright notice of all files.
2428 2018-01-02 Jan Beulich <jbeulich@suse.com>
2430 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2431 and OPERAND_TYPE_REGZMM entries.
2433 For older changes see ChangeLog-2017
2435 Copyright (C) 2018 Free Software Foundation, Inc.
2437 Copying and distribution of this file, with or without modification,
2438 are permitted in any medium without royalty provided the copyright
2439 notice and this notice are preserved.
2445 version-control: never