1 2019-09-03 Nick Clifton <nickc@redhat.com>
4 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
5 greater than zero before indexing via (bufcnt -1).
7 2019-09-03 Nick Clifton <nickc@redhat.com>
10 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
11 (MAX_SPEC_REG_NAME_LEN): Define.
12 (struct mmix_dis_info): Use defined constants for array lengths.
13 (get_reg_name): New function.
14 (get_sprec_reg_name): New function.
15 (print_insn_mmix): Use new functions.
17 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
19 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
20 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
21 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
23 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
25 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
26 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
27 (aarch64_sys_reg_supported_p): Update checks for the above.
29 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
31 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
32 cases MVE_SQRSHRL and MVE_UQRSHLL.
33 (print_insn_mve): Add case for specifier 'k' to check
34 specific bit of the instruction.
36 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
39 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
40 encountering an unknown machine type.
41 (print_insn_arc): Handle arc_insn_length returning 0. In error
42 cases return -1 rather than calling abort.
44 2019-08-07 Jan Beulich <jbeulich@suse.com>
46 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
47 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
49 * i386-tbl.h: Re-generate.
51 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
53 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
56 2019-07-30 Mel Chen <mel.chen@sifive.com>
58 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
59 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
61 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
64 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
66 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
67 and MPY class instructions.
68 (parse_option): Add nps400 option.
69 (print_arc_disassembler_options): Add nps400 info.
71 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
73 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
76 * arc-opc.c (RAD_CHK): Add.
77 * arc-tbl.h: Regenerate.
79 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
81 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
82 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
84 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
86 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
87 instructions as UNPREDICTABLE.
89 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
91 * bpf-desc.c: Regenerated.
93 2019-07-17 Jan Beulich <jbeulich@suse.com>
95 * i386-gen.c (static_assert): Define.
97 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
98 (Opcode_Modifier_Num): ... this.
101 2019-07-16 Jan Beulich <jbeulich@suse.com>
103 * i386-gen.c (operand_types): Move RegMem ...
104 (opcode_modifiers): ... here.
105 * i386-opc.h (RegMem): Move to opcode modifer enum.
106 (union i386_operand_type): Move regmem field ...
107 (struct i386_opcode_modifier): ... here.
108 * i386-opc.tbl (RegMem): Define.
109 (mov, movq): Move RegMem on segment, control, debug, and test
111 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
112 to non-SSE2AVX flavor.
113 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
114 Move RegMem on register only flavors. Drop IgnoreSize from
115 legacy encoding flavors.
116 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
118 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
119 register only flavors.
120 (vmovd): Move RegMem and drop IgnoreSize on register only
121 flavor. Change opcode and operand order to store form.
122 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
124 2019-07-16 Jan Beulich <jbeulich@suse.com>
126 * i386-gen.c (operand_type_init, operand_types): Replace SReg
128 * i386-opc.h (SReg2, SReg3): Replace by ...
130 (union i386_operand_type): Replace sreg fields.
131 * i386-opc.tbl (mov, ): Use SReg.
132 (push, pop): Likewies. Drop i386 and x86-64 specific segment
134 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
135 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
137 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
139 * bpf-desc.c: Regenerate.
140 * bpf-opc.c: Likewise.
141 * bpf-opc.h: Likewise.
143 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
145 * bpf-desc.c: Regenerate.
146 * bpf-opc.c: Likewise.
148 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
150 * arm-dis.c (print_insn_coprocessor): Rename index to
153 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
155 * riscv-opc.c (riscv_insn_types): Add r4 type.
157 * riscv-opc.c (riscv_insn_types): Add b and j type.
159 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
160 format for sb type and correct s type.
162 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
164 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
165 SVE FMOV alias of FCPY.
167 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
169 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
170 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
172 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
174 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
175 registers in an instruction prefixed by MOVPRFX.
177 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
179 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
180 sve_size_13 icode to account for variant behaviour of
182 * aarch64-dis-2.c: Regenerate.
183 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
184 sve_size_13 icode to account for variant behaviour of
186 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
187 (OP_SVE_VVV_Q_D): Add new qualifier.
188 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
189 (struct aarch64_opcode): Split pmull{t,b} into those requiring
192 2019-07-01 Jan Beulich <jbeulich@suse.com>
194 * opcodes/i386-gen.c (operand_type_init): Remove
195 OPERAND_TYPE_VEC_IMM4 entry.
196 (operand_types): Remove Vec_Imm4.
197 * opcodes/i386-opc.h (Vec_Imm4): Delete.
198 (union i386_operand_type): Remove vec_imm4.
199 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
200 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
202 2019-07-01 Jan Beulich <jbeulich@suse.com>
204 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
205 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
206 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
207 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
208 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
209 monitorx, mwaitx): Drop ImmExt from operand-less forms.
210 * i386-tbl.h: Re-generate.
212 2019-07-01 Jan Beulich <jbeulich@suse.com>
214 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
216 * i386-tbl.h: Re-generate.
218 2019-07-01 Jan Beulich <jbeulich@suse.com>
220 * i386-opc.tbl (C): New.
221 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
222 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
223 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
224 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
225 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
226 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
227 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
228 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
229 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
230 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
231 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
232 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
233 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
234 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
235 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
236 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
237 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
238 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
239 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
240 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
241 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
242 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
243 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
244 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
245 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
246 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
248 * i386-tbl.h: Re-generate.
250 2019-07-01 Jan Beulich <jbeulich@suse.com>
252 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
254 * i386-tbl.h: Re-generate.
256 2019-07-01 Jan Beulich <jbeulich@suse.com>
258 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
259 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
260 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
261 * i386-tbl.h: Re-generate.
263 2019-07-01 Jan Beulich <jbeulich@suse.com>
265 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
266 Disp8MemShift from register only templates.
267 * i386-tbl.h: Re-generate.
269 2019-07-01 Jan Beulich <jbeulich@suse.com>
271 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
272 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
273 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
274 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
275 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
276 EVEX_W_0F11_P_3_M_1): Delete.
277 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
278 EVEX_W_0F11_P_3): New.
279 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
280 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
281 MOD_EVEX_0F11_PREFIX_3 table entries.
282 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
283 PREFIX_EVEX_0F11 table entries.
284 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
285 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
286 EVEX_W_0F11_P_3_M_{0,1} table entries.
288 2019-07-01 Jan Beulich <jbeulich@suse.com>
290 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
293 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
296 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
297 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
298 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
299 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
300 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
301 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
302 EVEX_LEN_0F38C7_R_6_P_2_W_1.
303 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
304 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
305 PREFIX_EVEX_0F38C6_REG_6 entries.
306 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
307 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
308 EVEX_W_0F38C7_R_6_P_2 entries.
309 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
310 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
311 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
312 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
313 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
314 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
315 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
317 2019-06-27 Jan Beulich <jbeulich@suse.com>
319 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
320 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
321 VEX_LEN_0F2D_P_3): Delete.
322 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
323 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
324 (prefix_table): ... here.
326 2019-06-27 Jan Beulich <jbeulich@suse.com>
328 * i386-dis.c (Iq): Delete.
330 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
332 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
333 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
334 (OP_E_memory): Also honor needindex when deciding whether an
335 address size prefix needs printing.
336 (OP_I): Remove handling of q_mode. Add handling of d_mode.
338 2019-06-26 Jim Wilson <jimw@sifive.com>
341 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
342 Set info->display_endian to info->endian_code.
344 2019-06-25 Jan Beulich <jbeulich@suse.com>
346 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
347 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
348 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
349 OPERAND_TYPE_ACC64 entries.
350 * i386-init.h: Re-generate.
352 2019-06-25 Jan Beulich <jbeulich@suse.com>
354 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
356 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
358 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
360 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
361 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
363 2019-06-25 Jan Beulich <jbeulich@suse.com>
365 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
368 2019-06-25 Jan Beulich <jbeulich@suse.com>
370 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
371 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
373 * i386-opc.tbl (movnti): Add IgnoreSize.
374 * i386-tbl.h: Re-generate.
376 2019-06-25 Jan Beulich <jbeulich@suse.com>
378 * i386-opc.tbl (and): Mark Imm8S form for optimization.
379 * i386-tbl.h: Re-generate.
381 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
383 * i386-dis-evex.h: Break into ...
384 * i386-dis-evex-len.h: New file.
385 * i386-dis-evex-mod.h: Likewise.
386 * i386-dis-evex-prefix.h: Likewise.
387 * i386-dis-evex-reg.h: Likewise.
388 * i386-dis-evex-w.h: Likewise.
389 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
390 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
393 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
396 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
397 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
399 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
400 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
401 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
402 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
403 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
404 EVEX_LEN_0F385B_P_2_W_1.
405 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
406 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
407 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
408 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
409 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
410 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
411 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
412 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
413 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
414 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
416 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
419 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
420 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
421 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
422 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
423 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
424 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
425 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
426 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
427 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
428 EVEX_LEN_0F3A43_P_2_W_1.
429 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
430 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
431 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
432 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
433 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
434 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
435 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
436 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
437 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
438 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
439 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
440 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
442 2019-06-14 Nick Clifton <nickc@redhat.com>
444 * po/fr.po; Updated French translation.
446 2019-06-13 Stafford Horne <shorne@gmail.com>
448 * or1k-asm.c: Regenerated.
449 * or1k-desc.c: Regenerated.
450 * or1k-desc.h: Regenerated.
451 * or1k-dis.c: Regenerated.
452 * or1k-ibld.c: Regenerated.
453 * or1k-opc.c: Regenerated.
454 * or1k-opc.h: Regenerated.
455 * or1k-opinst.c: Regenerated.
457 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
459 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
461 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
464 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
465 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
466 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
467 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
468 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
469 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
470 EVEX_LEN_0F3A1B_P_2_W_1.
471 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
472 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
473 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
474 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
475 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
476 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
477 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
478 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
480 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
483 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
484 EVEX.vvvv when disassembling VEX and EVEX instructions.
485 (OP_VEX): Set vex.register_specifier to 0 after readding
486 vex.register_specifier.
487 (OP_Vex_2src_1): Likewise.
488 (OP_Vex_2src_2): Likewise.
489 (OP_LWP_E): Likewise.
490 (OP_EX_Vex): Don't check vex.register_specifier.
491 (OP_XMM_Vex): Likewise.
493 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
494 Lili Cui <lili.cui@intel.com>
496 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
497 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
499 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
500 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
501 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
502 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
503 (i386_cpu_flags): Add cpuavx512_vp2intersect.
504 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
505 * i386-init.h: Regenerated.
506 * i386-tbl.h: Likewise.
508 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
509 Lili Cui <lili.cui@intel.com>
511 * doc/c-i386.texi: Document enqcmd.
512 * testsuite/gas/i386/enqcmd-intel.d: New file.
513 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
514 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
515 * testsuite/gas/i386/enqcmd.d: Likewise.
516 * testsuite/gas/i386/enqcmd.s: Likewise.
517 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
518 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
519 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
520 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
521 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
522 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
523 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
526 2019-06-04 Alan Hayward <alan.hayward@arm.com>
528 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
530 2019-06-03 Alan Modra <amodra@gmail.com>
532 * ppc-dis.c (prefix_opcd_indices): Correct size.
534 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
537 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
539 * i386-tbl.h: Regenerated.
541 2019-05-24 Alan Modra <amodra@gmail.com>
543 * po/POTFILES.in: Regenerate.
545 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
546 Alan Modra <amodra@gmail.com>
548 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
549 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
550 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
551 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
552 XTOP>): Define and add entries.
553 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
554 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
555 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
556 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
558 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
559 Alan Modra <amodra@gmail.com>
561 * ppc-dis.c (ppc_opts): Add "future" entry.
562 (PREFIX_OPCD_SEGS): Define.
563 (prefix_opcd_indices): New array.
564 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
565 (lookup_prefix): New function.
566 (print_insn_powerpc): Handle 64-bit prefix instructions.
567 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
568 (PMRR, POWERXX): Define.
569 (prefix_opcodes): New instruction table.
570 (prefix_num_opcodes): New constant.
572 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
574 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
575 * configure: Regenerated.
576 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
578 (HFILES): Add bpf-desc.h and bpf-opc.h.
579 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
580 bpf-ibld.c and bpf-opc.c.
582 * Makefile.in: Regenerated.
583 * disassemble.c (ARCH_bpf): Define.
584 (disassembler): Add case for bfd_arch_bpf.
585 (disassemble_init_for_target): Likewise.
586 (enum epbf_isa_attr): Define.
587 * disassemble.h: extern print_insn_bpf.
588 * bpf-asm.c: Generated.
589 * bpf-opc.h: Likewise.
590 * bpf-opc.c: Likewise.
591 * bpf-ibld.c: Likewise.
592 * bpf-dis.c: Likewise.
593 * bpf-desc.h: Likewise.
594 * bpf-desc.c: Likewise.
596 2019-05-21 Sudakshina Das <sudi.das@arm.com>
598 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
599 and VMSR with the new operands.
601 2019-05-21 Sudakshina Das <sudi.das@arm.com>
603 * arm-dis.c (enum mve_instructions): New enum
604 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
606 (mve_opcodes): New instructions as above.
607 (is_mve_encoding_conflict): Add cases for csinc, csinv,
609 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
611 2019-05-21 Sudakshina Das <sudi.das@arm.com>
613 * arm-dis.c (emun mve_instructions): Updated for new instructions.
614 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
615 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
616 uqshl, urshrl and urshr.
617 (is_mve_okay_in_it): Add new instructions to TRUE list.
618 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
619 (print_insn_mve): Updated to accept new %j,
620 %<bitfield>m and %<bitfield>n patterns.
622 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
624 * mips-opc.c (mips_builtin_opcodes): Change source register
627 2019-05-20 Nick Clifton <nickc@redhat.com>
629 * po/fr.po: Updated French translation.
631 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
632 Michael Collison <michael.collison@arm.com>
634 * arm-dis.c (thumb32_opcodes): Add new instructions.
635 (enum mve_instructions): Likewise.
636 (enum mve_undefined): Add new reasons.
637 (is_mve_encoding_conflict): Handle new instructions.
638 (is_mve_undefined): Likewise.
639 (is_mve_unpredictable): Likewise.
640 (print_mve_undefined): Likewise.
641 (print_mve_size): Likewise.
643 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
644 Michael Collison <michael.collison@arm.com>
646 * arm-dis.c (thumb32_opcodes): Add new instructions.
647 (enum mve_instructions): Likewise.
648 (is_mve_encoding_conflict): Handle new instructions.
649 (is_mve_undefined): Likewise.
650 (is_mve_unpredictable): Likewise.
651 (print_mve_size): Likewise.
653 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
654 Michael Collison <michael.collison@arm.com>
656 * arm-dis.c (thumb32_opcodes): Add new instructions.
657 (enum mve_instructions): Likewise.
658 (is_mve_encoding_conflict): Likewise.
659 (is_mve_unpredictable): Likewise.
660 (print_mve_size): Likewise.
662 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
663 Michael Collison <michael.collison@arm.com>
665 * arm-dis.c (thumb32_opcodes): Add new instructions.
666 (enum mve_instructions): Likewise.
667 (is_mve_encoding_conflict): Handle new instructions.
668 (is_mve_undefined): Likewise.
669 (is_mve_unpredictable): Likewise.
670 (print_mve_size): Likewise.
672 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
673 Michael Collison <michael.collison@arm.com>
675 * arm-dis.c (thumb32_opcodes): Add new instructions.
676 (enum mve_instructions): Likewise.
677 (is_mve_encoding_conflict): Handle new instructions.
678 (is_mve_undefined): Likewise.
679 (is_mve_unpredictable): Likewise.
680 (print_mve_size): Likewise.
681 (print_insn_mve): Likewise.
683 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
684 Michael Collison <michael.collison@arm.com>
686 * arm-dis.c (thumb32_opcodes): Add new instructions.
687 (print_insn_thumb32): Handle new instructions.
689 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
690 Michael Collison <michael.collison@arm.com>
692 * arm-dis.c (enum mve_instructions): Add new instructions.
693 (enum mve_undefined): Add new reasons.
694 (is_mve_encoding_conflict): Handle new instructions.
695 (is_mve_undefined): Likewise.
696 (is_mve_unpredictable): Likewise.
697 (print_mve_undefined): Likewise.
698 (print_mve_size): Likewise.
699 (print_mve_shift_n): Likewise.
700 (print_insn_mve): Likewise.
702 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
703 Michael Collison <michael.collison@arm.com>
705 * arm-dis.c (enum mve_instructions): Add new instructions.
706 (is_mve_encoding_conflict): Handle new instructions.
707 (is_mve_unpredictable): Likewise.
708 (print_mve_rotate): Likewise.
709 (print_mve_size): Likewise.
710 (print_insn_mve): Likewise.
712 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
713 Michael Collison <michael.collison@arm.com>
715 * arm-dis.c (enum mve_instructions): Add new instructions.
716 (is_mve_encoding_conflict): Handle new instructions.
717 (is_mve_unpredictable): Likewise.
718 (print_mve_size): Likewise.
719 (print_insn_mve): Likewise.
721 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
722 Michael Collison <michael.collison@arm.com>
724 * arm-dis.c (enum mve_instructions): Add new instructions.
725 (enum mve_undefined): Add new reasons.
726 (is_mve_encoding_conflict): Handle new instructions.
727 (is_mve_undefined): Likewise.
728 (is_mve_unpredictable): Likewise.
729 (print_mve_undefined): Likewise.
730 (print_mve_size): Likewise.
731 (print_insn_mve): Likewise.
733 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
734 Michael Collison <michael.collison@arm.com>
736 * arm-dis.c (enum mve_instructions): Add new instructions.
737 (is_mve_encoding_conflict): Handle new instructions.
738 (is_mve_undefined): Likewise.
739 (is_mve_unpredictable): Likewise.
740 (print_mve_size): Likewise.
741 (print_insn_mve): Likewise.
743 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
744 Michael Collison <michael.collison@arm.com>
746 * arm-dis.c (enum mve_instructions): Add new instructions.
747 (enum mve_unpredictable): Add new reasons.
748 (enum mve_undefined): Likewise.
749 (is_mve_okay_in_it): Handle new isntructions.
750 (is_mve_encoding_conflict): Likewise.
751 (is_mve_undefined): Likewise.
752 (is_mve_unpredictable): Likewise.
753 (print_mve_vmov_index): Likewise.
754 (print_simd_imm8): Likewise.
755 (print_mve_undefined): Likewise.
756 (print_mve_unpredictable): Likewise.
757 (print_mve_size): Likewise.
758 (print_insn_mve): Likewise.
760 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
761 Michael Collison <michael.collison@arm.com>
763 * arm-dis.c (enum mve_instructions): Add new instructions.
764 (enum mve_unpredictable): Add new reasons.
765 (enum mve_undefined): Likewise.
766 (is_mve_encoding_conflict): Handle new instructions.
767 (is_mve_undefined): Likewise.
768 (is_mve_unpredictable): Likewise.
769 (print_mve_undefined): Likewise.
770 (print_mve_unpredictable): Likewise.
771 (print_mve_rounding_mode): Likewise.
772 (print_mve_vcvt_size): Likewise.
773 (print_mve_size): Likewise.
774 (print_insn_mve): Likewise.
776 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
777 Michael Collison <michael.collison@arm.com>
779 * arm-dis.c (enum mve_instructions): Add new instructions.
780 (enum mve_unpredictable): Add new reasons.
781 (enum mve_undefined): Likewise.
782 (is_mve_undefined): Handle new instructions.
783 (is_mve_unpredictable): Likewise.
784 (print_mve_undefined): Likewise.
785 (print_mve_unpredictable): Likewise.
786 (print_mve_size): Likewise.
787 (print_insn_mve): Likewise.
789 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
790 Michael Collison <michael.collison@arm.com>
792 * arm-dis.c (enum mve_instructions): Add new instructions.
793 (enum mve_undefined): Add new reasons.
794 (insns): Add new instructions.
795 (is_mve_encoding_conflict):
796 (print_mve_vld_str_addr): New print function.
797 (is_mve_undefined): Handle new instructions.
798 (is_mve_unpredictable): Likewise.
799 (print_mve_undefined): Likewise.
800 (print_mve_size): Likewise.
801 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
802 (print_insn_mve): Handle new operands.
804 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
805 Michael Collison <michael.collison@arm.com>
807 * arm-dis.c (enum mve_instructions): Add new instructions.
808 (enum mve_unpredictable): Add new reasons.
809 (is_mve_encoding_conflict): Handle new instructions.
810 (is_mve_unpredictable): Likewise.
811 (mve_opcodes): Add new instructions.
812 (print_mve_unpredictable): Handle new reasons.
813 (print_mve_register_blocks): New print function.
814 (print_mve_size): Handle new instructions.
815 (print_insn_mve): Likewise.
817 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
818 Michael Collison <michael.collison@arm.com>
820 * arm-dis.c (enum mve_instructions): Add new instructions.
821 (enum mve_unpredictable): Add new reasons.
822 (enum mve_undefined): Likewise.
823 (is_mve_encoding_conflict): Handle new instructions.
824 (is_mve_undefined): Likewise.
825 (is_mve_unpredictable): Likewise.
826 (coprocessor_opcodes): Move NEON VDUP from here...
827 (neon_opcodes): ... to here.
828 (mve_opcodes): Add new instructions.
829 (print_mve_undefined): Handle new reasons.
830 (print_mve_unpredictable): Likewise.
831 (print_mve_size): Handle new instructions.
832 (print_insn_neon): Handle vdup.
833 (print_insn_mve): Handle new operands.
835 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
836 Michael Collison <michael.collison@arm.com>
838 * arm-dis.c (enum mve_instructions): Add new instructions.
839 (enum mve_unpredictable): Add new values.
840 (mve_opcodes): Add new instructions.
841 (vec_condnames): New array with vector conditions.
842 (mve_predicatenames): New array with predicate suffixes.
843 (mve_vec_sizename): New array with vector sizes.
844 (enum vpt_pred_state): New enum with vector predication states.
845 (struct vpt_block): New struct type for vpt blocks.
846 (vpt_block_state): Global struct to keep track of state.
847 (mve_extract_pred_mask): New helper function.
848 (num_instructions_vpt_block): Likewise.
849 (mark_outside_vpt_block): Likewise.
850 (mark_inside_vpt_block): Likewise.
851 (invert_next_predicate_state): Likewise.
852 (update_next_predicate_state): Likewise.
853 (update_vpt_block_state): Likewise.
854 (is_vpt_instruction): Likewise.
855 (is_mve_encoding_conflict): Add entries for new instructions.
856 (is_mve_unpredictable): Likewise.
857 (print_mve_unpredictable): Handle new cases.
858 (print_instruction_predicate): Likewise.
859 (print_mve_size): New function.
860 (print_vec_condition): New function.
861 (print_insn_mve): Handle vpt blocks and new print operands.
863 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
865 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
866 8, 14 and 15 for Armv8.1-M Mainline.
868 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
869 Michael Collison <michael.collison@arm.com>
871 * arm-dis.c (enum mve_instructions): New enum.
872 (enum mve_unpredictable): Likewise.
873 (enum mve_undefined): Likewise.
874 (struct mopcode32): New struct.
875 (is_mve_okay_in_it): New function.
876 (is_mve_architecture): Likewise.
877 (arm_decode_field): Likewise.
878 (arm_decode_field_multiple): Likewise.
879 (is_mve_encoding_conflict): Likewise.
880 (is_mve_undefined): Likewise.
881 (is_mve_unpredictable): Likewise.
882 (print_mve_undefined): Likewise.
883 (print_mve_unpredictable): Likewise.
884 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
885 (print_insn_mve): New function.
886 (print_insn_thumb32): Handle MVE architecture.
887 (select_arm_features): Force thumb for Armv8.1-m Mainline.
889 2019-05-10 Nick Clifton <nickc@redhat.com>
892 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
893 end of the table prematurely.
895 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
897 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
900 2019-05-11 Alan Modra <amodra@gmail.com>
902 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
903 when -Mraw is in effect.
905 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
907 * aarch64-dis-2.c: Regenerate.
908 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
909 (OP_SVE_BBB): New variant set.
910 (OP_SVE_DDDD): New variant set.
911 (OP_SVE_HHH): New variant set.
912 (OP_SVE_HHHU): New variant set.
913 (OP_SVE_SSS): New variant set.
914 (OP_SVE_SSSU): New variant set.
915 (OP_SVE_SHH): New variant set.
916 (OP_SVE_SBBU): New variant set.
917 (OP_SVE_DSS): New variant set.
918 (OP_SVE_DHHU): New variant set.
919 (OP_SVE_VMV_HSD_BHS): New variant set.
920 (OP_SVE_VVU_HSD_BHS): New variant set.
921 (OP_SVE_VVVU_SD_BH): New variant set.
922 (OP_SVE_VVVU_BHSD): New variant set.
923 (OP_SVE_VVV_QHD_DBS): New variant set.
924 (OP_SVE_VVV_HSD_BHS): New variant set.
925 (OP_SVE_VVV_HSD_BHS2): New variant set.
926 (OP_SVE_VVV_BHS_HSD): New variant set.
927 (OP_SVE_VV_BHS_HSD): New variant set.
928 (OP_SVE_VVV_SD): New variant set.
929 (OP_SVE_VVU_BHS_HSD): New variant set.
930 (OP_SVE_VZVV_SD): New variant set.
931 (OP_SVE_VZVV_BH): New variant set.
932 (OP_SVE_VZV_SD): New variant set.
933 (aarch64_opcode_table): Add sve2 instructions.
935 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
937 * aarch64-asm-2.c: Regenerated.
938 * aarch64-dis-2.c: Regenerated.
939 * aarch64-opc-2.c: Regenerated.
940 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
941 for SVE_SHLIMM_UNPRED_22.
942 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
943 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
946 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
948 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
949 sve_size_tsz_bhs iclass encode.
950 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
951 sve_size_tsz_bhs iclass decode.
953 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
955 * aarch64-asm-2.c: Regenerated.
956 * aarch64-dis-2.c: Regenerated.
957 * aarch64-opc-2.c: Regenerated.
958 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
959 for SVE_Zm4_11_INDEX.
960 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
961 (fields): Handle SVE_i2h field.
962 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
963 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
965 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
967 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
968 sve_shift_tsz_bhsd iclass encode.
969 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
970 sve_shift_tsz_bhsd iclass decode.
972 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
974 * aarch64-asm-2.c: Regenerated.
975 * aarch64-dis-2.c: Regenerated.
976 * aarch64-opc-2.c: Regenerated.
977 * aarch64-asm.c (aarch64_ins_sve_shrimm):
978 (aarch64_encode_variant_using_iclass): Handle
979 sve_shift_tsz_hsd iclass encode.
980 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
981 sve_shift_tsz_hsd iclass decode.
982 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
983 for SVE_SHRIMM_UNPRED_22.
984 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
985 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
988 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
990 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
991 sve_size_013 iclass encode.
992 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
993 sve_size_013 iclass decode.
995 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
997 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
998 sve_size_bh iclass encode.
999 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1000 sve_size_bh iclass decode.
1002 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1004 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1005 sve_size_sd2 iclass encode.
1006 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1007 sve_size_sd2 iclass decode.
1008 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1009 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1011 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1013 * aarch64-asm-2.c: Regenerated.
1014 * aarch64-dis-2.c: Regenerated.
1015 * aarch64-opc-2.c: Regenerated.
1016 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1018 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1019 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1021 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1023 * aarch64-asm-2.c: Regenerated.
1024 * aarch64-dis-2.c: Regenerated.
1025 * aarch64-opc-2.c: Regenerated.
1026 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1027 for SVE_Zm3_11_INDEX.
1028 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1029 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1030 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1032 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1034 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1036 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1037 sve_size_hsd2 iclass encode.
1038 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1039 sve_size_hsd2 iclass decode.
1040 * aarch64-opc.c (fields): Handle SVE_size field.
1041 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1043 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1045 * aarch64-asm-2.c: Regenerated.
1046 * aarch64-dis-2.c: Regenerated.
1047 * aarch64-opc-2.c: Regenerated.
1048 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1050 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1051 (fields): Handle SVE_rot3 field.
1052 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1053 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1055 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1057 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1060 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1063 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1064 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1065 aarch64_feature_sve2bitperm): New feature sets.
1066 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1067 for feature set addresses.
1068 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1069 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1071 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1072 Faraz Shahbazker <fshahbazker@wavecomp.com>
1074 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1075 argument and set ASE_EVA_R6 appropriately.
1076 (set_default_mips_dis_options): Pass ISA to above.
1077 (parse_mips_dis_option): Likewise.
1078 * mips-opc.c (EVAR6): New macro.
1079 (mips_builtin_opcodes): Add llwpe, scwpe.
1081 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1083 * aarch64-asm-2.c: Regenerated.
1084 * aarch64-dis-2.c: Regenerated.
1085 * aarch64-opc-2.c: Regenerated.
1086 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1087 AARCH64_OPND_TME_UIMM16.
1088 (aarch64_print_operand): Likewise.
1089 * aarch64-tbl.h (QL_IMM_NIL): New.
1092 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1094 2019-04-29 John Darrington <john@darrington.wattle.id.au>
1096 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1098 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1099 Faraz Shahbazker <fshahbazker@wavecomp.com>
1101 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1103 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1105 * s12z-opc.h: Add extern "C" bracketing to help
1106 users who wish to use this interface in c++ code.
1108 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1110 * s12z-opc.c (bm_decode): Handle bit map operations with the
1113 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1115 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1116 specifier. Add entries for VLDR and VSTR of system registers.
1117 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1118 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1119 of %J and %K format specifier.
1121 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1123 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1124 Add new entries for VSCCLRM instruction.
1125 (print_insn_coprocessor): Handle new %C format control code.
1127 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1129 * arm-dis.c (enum isa): New enum.
1130 (struct sopcode32): New structure.
1131 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1132 set isa field of all current entries to ANY.
1133 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1134 Only match an entry if its isa field allows the current mode.
1136 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1138 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1140 (print_insn_thumb32): Add logic to print %n CLRM register list.
1142 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1144 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1147 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1149 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1150 (print_insn_thumb32): Edit the switch case for %Z.
1152 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1154 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1156 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1158 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1160 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1162 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1164 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1166 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1167 Arm register with r13 and r15 unpredictable.
1168 (thumb32_opcodes): New instructions for bfx and bflx.
1170 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1172 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1174 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1176 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1178 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1180 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1182 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1184 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1186 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1188 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1189 "optr". ("operator" is a reserved word in c++).
1191 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1193 * aarch64-opc.c (aarch64_print_operand): Add case for
1195 (verify_constraints): Likewise.
1196 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1197 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1198 to accept Rt|SP as first operand.
1199 (AARCH64_OPERANDS): Add new Rt_SP.
1200 * aarch64-asm-2.c: Regenerated.
1201 * aarch64-dis-2.c: Regenerated.
1202 * aarch64-opc-2.c: Regenerated.
1204 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1206 * aarch64-asm-2.c: Regenerated.
1207 * aarch64-dis-2.c: Likewise.
1208 * aarch64-opc-2.c: Likewise.
1209 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1211 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1213 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1215 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1217 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1218 * i386-init.h: Regenerated.
1220 2019-04-07 Alan Modra <amodra@gmail.com>
1222 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1223 op_separator to control printing of spaces, comma and parens
1224 rather than need_comma, need_paren and spaces vars.
1226 2019-04-07 Alan Modra <amodra@gmail.com>
1229 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1230 (print_insn_neon, print_insn_arm): Likewise.
1232 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1234 * i386-dis-evex.h (evex_table): Updated to support BF16
1236 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1237 and EVEX_W_0F3872_P_3.
1238 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1239 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1240 * i386-opc.h (enum): Add CpuAVX512_BF16.
1241 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1242 * i386-opc.tbl: Add AVX512 BF16 instructions.
1243 * i386-init.h: Regenerated.
1244 * i386-tbl.h: Likewise.
1246 2019-04-05 Alan Modra <amodra@gmail.com>
1248 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1249 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1250 to favour printing of "-" branch hint when using the "y" bit.
1251 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1253 2019-04-05 Alan Modra <amodra@gmail.com>
1255 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1256 opcode until first operand is output.
1258 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1261 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1262 (valid_bo_post_v2): Add support for 'at' branch hints.
1263 (insert_bo): Only error on branch on ctr.
1264 (get_bo_hint_mask): New function.
1265 (insert_boe): Add new 'branch_taken' formal argument. Add support
1266 for inserting 'at' branch hints.
1267 (extract_boe): Add new 'branch_taken' formal argument. Add support
1268 for extracting 'at' branch hints.
1269 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1270 (BOE): Delete operand.
1271 (BOM, BOP): New operands.
1273 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1274 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1275 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1276 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1277 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1278 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1279 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1280 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1281 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1282 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1283 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1284 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1285 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1286 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1287 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1288 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1289 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1290 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1291 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1292 bttarl+>: New extended mnemonics.
1294 2019-03-28 Alan Modra <amodra@gmail.com>
1297 * ppc-opc.c (BTF): Define.
1298 (powerpc_opcodes): Use for mtfsb*.
1299 * ppc-dis.c (print_insn_powerpc): Print fields with both
1300 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1302 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1304 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1305 (mapping_symbol_for_insn): Implement new algorithm.
1306 (print_insn): Remove duplicate code.
1308 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1310 * aarch64-dis.c (print_insn_aarch64):
1313 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1315 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1318 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1320 * aarch64-dis.c (last_stop_offset): New.
1321 (print_insn_aarch64): Use stop_offset.
1323 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1326 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1328 * i386-init.h: Regenerated.
1330 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1333 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1334 vmovdqu16, vmovdqu32 and vmovdqu64.
1335 * i386-tbl.h: Regenerated.
1337 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1339 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1340 from vstrszb, vstrszh, and vstrszf.
1342 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1344 * s390-opc.txt: Add instruction descriptions.
1346 2019-02-08 Jim Wilson <jimw@sifive.com>
1348 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1351 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1353 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1355 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1358 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1359 * aarch64-opc.c (verify_elem_sd): New.
1360 (fields): Add FLD_sz entr.
1361 * aarch64-tbl.h (_SIMD_INSN): New.
1362 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1363 fmulx scalar and vector by element isns.
1365 2019-02-07 Nick Clifton <nickc@redhat.com>
1367 * po/sv.po: Updated Swedish translation.
1369 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1371 * s390-mkopc.c (main): Accept arch13 as cpu string.
1372 * s390-opc.c: Add new instruction formats and instruction opcode
1374 * s390-opc.txt: Add new arch13 instructions.
1376 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1378 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1379 (aarch64_opcode): Change encoding for stg, stzg
1381 * aarch64-asm-2.c: Regenerated.
1382 * aarch64-dis-2.c: Regenerated.
1383 * aarch64-opc-2.c: Regenerated.
1385 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1387 * aarch64-asm-2.c: Regenerated.
1388 * aarch64-dis-2.c: Likewise.
1389 * aarch64-opc-2.c: Likewise.
1390 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1392 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1393 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1395 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1396 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1397 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1398 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1399 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1400 case for ldstgv_indexed.
1401 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1402 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1403 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1404 * aarch64-asm-2.c: Regenerated.
1405 * aarch64-dis-2.c: Regenerated.
1406 * aarch64-opc-2.c: Regenerated.
1408 2019-01-23 Nick Clifton <nickc@redhat.com>
1410 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1412 2019-01-21 Nick Clifton <nickc@redhat.com>
1414 * po/de.po: Updated German translation.
1415 * po/uk.po: Updated Ukranian translation.
1417 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1418 * mips-dis.c (mips_arch_choices): Fix typo in
1419 gs464, gs464e and gs264e descriptors.
1421 2019-01-19 Nick Clifton <nickc@redhat.com>
1423 * configure: Regenerate.
1424 * po/opcodes.pot: Regenerate.
1426 2018-06-24 Nick Clifton <nickc@redhat.com>
1428 2.32 branch created.
1430 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1432 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1434 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1437 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1439 * configure: Regenerate.
1441 2019-01-07 Alan Modra <amodra@gmail.com>
1443 * configure: Regenerate.
1444 * po/POTFILES.in: Regenerate.
1446 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1448 * s12z-opc.c: New file.
1449 * s12z-opc.h: New file.
1450 * s12z-dis.c: Removed all code not directly related to display
1451 of instructions. Used the interface provided by the new files
1453 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1454 * Makefile.in: Regenerate.
1455 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1456 * configure: Regenerate.
1458 2019-01-01 Alan Modra <amodra@gmail.com>
1460 Update year range in copyright notice of all files.
1462 For older changes see ChangeLog-2018
1464 Copyright (C) 2019 Free Software Foundation, Inc.
1466 Copying and distribution of this file, with or without modification,
1467 are permitted in any medium without royalty provided the copyright
1468 notice and this notice are preserved.
1474 version-control: never