1 2018-09-21 Simon Marchi <simon.marchi@ericsson.com>
3 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
4 * Makefile.in: Re-generate.
5 * aclocal.m4: Re-generate.
6 * configure: Re-generate.
7 * configure.ac: Remove check for -Wno-missing-field-initializers.
8 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
9 (csky_v2_opcodes): Likewise.
11 2018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
13 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
15 2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
17 * nds32-asm.c (operand_fields): Remove the unused fields.
18 (nds32_opcodes): Remove the unused instructions.
19 * nds32-dis.c (nds32_ex9_info): Removed.
20 (nds32_parse_opcode): Updated.
21 (print_insn_nds32): Likewise.
22 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
23 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
24 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
25 build_opcode_hash_table): New functions.
26 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
27 nds32_opcode_table): New.
28 (hw_ktabs): Declare it to a pointer rather than an array.
29 (build_hash_table): Removed.
30 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
31 SYN_ROPT and upadte HW_GPR and HW_INT.
32 * nds32-dis.c (keywords): Remove const.
33 (match_field): New function.
34 (nds32_parse_opcode): Updated.
35 * disassemble.c (disassemble_init_for_target):
36 Add disassemble_init_nds32.
37 * nds32-dis.c (eum map_type): New.
38 (nds32_private_data): Likewise.
39 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
40 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
41 (print_insn_nds32): Updated.
42 * nds32-asm.c (parse_aext_reg): Add new parameter.
43 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
46 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
47 (operand_fields): Add new fields.
48 (nds32_opcodes): Add new instructions.
49 (keyword_aridxi_mx): New keyword.
50 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
52 (ALU2_1, ALU2_2, ALU2_3): New macros.
53 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
55 2018-09-17 Kito Cheng <kito@andestech.com>
57 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
59 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
62 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
63 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
64 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
65 (EVEX_LEN_0F7E_P_1): Likewise.
66 (EVEX_LEN_0F7E_P_2): Likewise.
67 (EVEX_LEN_0FD6_P_2): Likewise.
68 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
69 (EVEX_LEN_TABLE): Likewise.
70 (EVEX_LEN_0F6E_P_2): New enum.
71 (EVEX_LEN_0F7E_P_1): Likewise.
72 (EVEX_LEN_0F7E_P_2): Likewise.
73 (EVEX_LEN_0FD6_P_2): Likewise.
74 (evex_len_table): New.
75 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
76 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
77 * i386-tbl.h: Regenerated.
79 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
82 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
83 VEX_LEN_0F7E_P_2 entries.
84 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
85 * i386-tbl.h: Regenerated.
87 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
89 * i386-dis.c (VZERO_Fixup): Removed.
91 (VEX_LEN_0F10_P_1): Likewise.
92 (VEX_LEN_0F10_P_3): Likewise.
93 (VEX_LEN_0F11_P_1): Likewise.
94 (VEX_LEN_0F11_P_3): Likewise.
95 (VEX_LEN_0F2E_P_0): Likewise.
96 (VEX_LEN_0F2E_P_2): Likewise.
97 (VEX_LEN_0F2F_P_0): Likewise.
98 (VEX_LEN_0F2F_P_2): Likewise.
99 (VEX_LEN_0F51_P_1): Likewise.
100 (VEX_LEN_0F51_P_3): Likewise.
101 (VEX_LEN_0F52_P_1): Likewise.
102 (VEX_LEN_0F53_P_1): Likewise.
103 (VEX_LEN_0F58_P_1): Likewise.
104 (VEX_LEN_0F58_P_3): Likewise.
105 (VEX_LEN_0F59_P_1): Likewise.
106 (VEX_LEN_0F59_P_3): Likewise.
107 (VEX_LEN_0F5A_P_1): Likewise.
108 (VEX_LEN_0F5A_P_3): Likewise.
109 (VEX_LEN_0F5C_P_1): Likewise.
110 (VEX_LEN_0F5C_P_3): Likewise.
111 (VEX_LEN_0F5D_P_1): Likewise.
112 (VEX_LEN_0F5D_P_3): Likewise.
113 (VEX_LEN_0F5E_P_1): Likewise.
114 (VEX_LEN_0F5E_P_3): Likewise.
115 (VEX_LEN_0F5F_P_1): Likewise.
116 (VEX_LEN_0F5F_P_3): Likewise.
117 (VEX_LEN_0FC2_P_1): Likewise.
118 (VEX_LEN_0FC2_P_3): Likewise.
119 (VEX_LEN_0F3A0A_P_2): Likewise.
120 (VEX_LEN_0F3A0B_P_2): Likewise.
121 (VEX_W_0F10_P_0): Likewise.
122 (VEX_W_0F10_P_1): Likewise.
123 (VEX_W_0F10_P_2): Likewise.
124 (VEX_W_0F10_P_3): Likewise.
125 (VEX_W_0F11_P_0): Likewise.
126 (VEX_W_0F11_P_1): Likewise.
127 (VEX_W_0F11_P_2): Likewise.
128 (VEX_W_0F11_P_3): Likewise.
129 (VEX_W_0F12_P_0_M_0): Likewise.
130 (VEX_W_0F12_P_0_M_1): Likewise.
131 (VEX_W_0F12_P_1): Likewise.
132 (VEX_W_0F12_P_2): Likewise.
133 (VEX_W_0F12_P_3): Likewise.
134 (VEX_W_0F13_M_0): Likewise.
135 (VEX_W_0F14): Likewise.
136 (VEX_W_0F15): Likewise.
137 (VEX_W_0F16_P_0_M_0): Likewise.
138 (VEX_W_0F16_P_0_M_1): Likewise.
139 (VEX_W_0F16_P_1): Likewise.
140 (VEX_W_0F16_P_2): Likewise.
141 (VEX_W_0F17_M_0): Likewise.
142 (VEX_W_0F28): Likewise.
143 (VEX_W_0F29): Likewise.
144 (VEX_W_0F2B_M_0): Likewise.
145 (VEX_W_0F2E_P_0): Likewise.
146 (VEX_W_0F2E_P_2): Likewise.
147 (VEX_W_0F2F_P_0): Likewise.
148 (VEX_W_0F2F_P_2): Likewise.
149 (VEX_W_0F50_M_0): Likewise.
150 (VEX_W_0F51_P_0): Likewise.
151 (VEX_W_0F51_P_1): Likewise.
152 (VEX_W_0F51_P_2): Likewise.
153 (VEX_W_0F51_P_3): Likewise.
154 (VEX_W_0F52_P_0): Likewise.
155 (VEX_W_0F52_P_1): Likewise.
156 (VEX_W_0F53_P_0): Likewise.
157 (VEX_W_0F53_P_1): Likewise.
158 (VEX_W_0F58_P_0): Likewise.
159 (VEX_W_0F58_P_1): Likewise.
160 (VEX_W_0F58_P_2): Likewise.
161 (VEX_W_0F58_P_3): Likewise.
162 (VEX_W_0F59_P_0): Likewise.
163 (VEX_W_0F59_P_1): Likewise.
164 (VEX_W_0F59_P_2): Likewise.
165 (VEX_W_0F59_P_3): Likewise.
166 (VEX_W_0F5A_P_0): Likewise.
167 (VEX_W_0F5A_P_1): Likewise.
168 (VEX_W_0F5A_P_3): Likewise.
169 (VEX_W_0F5B_P_0): Likewise.
170 (VEX_W_0F5B_P_1): Likewise.
171 (VEX_W_0F5B_P_2): Likewise.
172 (VEX_W_0F5C_P_0): Likewise.
173 (VEX_W_0F5C_P_1): Likewise.
174 (VEX_W_0F5C_P_2): Likewise.
175 (VEX_W_0F5C_P_3): Likewise.
176 (VEX_W_0F5D_P_0): Likewise.
177 (VEX_W_0F5D_P_1): Likewise.
178 (VEX_W_0F5D_P_2): Likewise.
179 (VEX_W_0F5D_P_3): Likewise.
180 (VEX_W_0F5E_P_0): Likewise.
181 (VEX_W_0F5E_P_1): Likewise.
182 (VEX_W_0F5E_P_2): Likewise.
183 (VEX_W_0F5E_P_3): Likewise.
184 (VEX_W_0F5F_P_0): Likewise.
185 (VEX_W_0F5F_P_1): Likewise.
186 (VEX_W_0F5F_P_2): Likewise.
187 (VEX_W_0F5F_P_3): Likewise.
188 (VEX_W_0F60_P_2): Likewise.
189 (VEX_W_0F61_P_2): Likewise.
190 (VEX_W_0F62_P_2): Likewise.
191 (VEX_W_0F63_P_2): Likewise.
192 (VEX_W_0F64_P_2): Likewise.
193 (VEX_W_0F65_P_2): Likewise.
194 (VEX_W_0F66_P_2): Likewise.
195 (VEX_W_0F67_P_2): Likewise.
196 (VEX_W_0F68_P_2): Likewise.
197 (VEX_W_0F69_P_2): Likewise.
198 (VEX_W_0F6A_P_2): Likewise.
199 (VEX_W_0F6B_P_2): Likewise.
200 (VEX_W_0F6C_P_2): Likewise.
201 (VEX_W_0F6D_P_2): Likewise.
202 (VEX_W_0F6F_P_1): Likewise.
203 (VEX_W_0F6F_P_2): Likewise.
204 (VEX_W_0F70_P_1): Likewise.
205 (VEX_W_0F70_P_2): Likewise.
206 (VEX_W_0F70_P_3): Likewise.
207 (VEX_W_0F71_R_2_P_2): Likewise.
208 (VEX_W_0F71_R_4_P_2): Likewise.
209 (VEX_W_0F71_R_6_P_2): Likewise.
210 (VEX_W_0F72_R_2_P_2): Likewise.
211 (VEX_W_0F72_R_4_P_2): Likewise.
212 (VEX_W_0F72_R_6_P_2): Likewise.
213 (VEX_W_0F73_R_2_P_2): Likewise.
214 (VEX_W_0F73_R_3_P_2): Likewise.
215 (VEX_W_0F73_R_6_P_2): Likewise.
216 (VEX_W_0F73_R_7_P_2): Likewise.
217 (VEX_W_0F74_P_2): Likewise.
218 (VEX_W_0F75_P_2): Likewise.
219 (VEX_W_0F76_P_2): Likewise.
220 (VEX_W_0F77_P_0): Likewise.
221 (VEX_W_0F7C_P_2): Likewise.
222 (VEX_W_0F7C_P_3): Likewise.
223 (VEX_W_0F7D_P_2): Likewise.
224 (VEX_W_0F7D_P_3): Likewise.
225 (VEX_W_0F7E_P_1): Likewise.
226 (VEX_W_0F7F_P_1): Likewise.
227 (VEX_W_0F7F_P_2): Likewise.
228 (VEX_W_0FAE_R_2_M_0): Likewise.
229 (VEX_W_0FAE_R_3_M_0): Likewise.
230 (VEX_W_0FC2_P_0): Likewise.
231 (VEX_W_0FC2_P_1): Likewise.
232 (VEX_W_0FC2_P_2): Likewise.
233 (VEX_W_0FC2_P_3): Likewise.
234 (VEX_W_0FD0_P_2): Likewise.
235 (VEX_W_0FD0_P_3): Likewise.
236 (VEX_W_0FD1_P_2): Likewise.
237 (VEX_W_0FD2_P_2): Likewise.
238 (VEX_W_0FD3_P_2): Likewise.
239 (VEX_W_0FD4_P_2): Likewise.
240 (VEX_W_0FD5_P_2): Likewise.
241 (VEX_W_0FD6_P_2): Likewise.
242 (VEX_W_0FD7_P_2_M_1): Likewise.
243 (VEX_W_0FD8_P_2): Likewise.
244 (VEX_W_0FD9_P_2): Likewise.
245 (VEX_W_0FDA_P_2): Likewise.
246 (VEX_W_0FDB_P_2): Likewise.
247 (VEX_W_0FDC_P_2): Likewise.
248 (VEX_W_0FDD_P_2): Likewise.
249 (VEX_W_0FDE_P_2): Likewise.
250 (VEX_W_0FDF_P_2): Likewise.
251 (VEX_W_0FE0_P_2): Likewise.
252 (VEX_W_0FE1_P_2): Likewise.
253 (VEX_W_0FE2_P_2): Likewise.
254 (VEX_W_0FE3_P_2): Likewise.
255 (VEX_W_0FE4_P_2): Likewise.
256 (VEX_W_0FE5_P_2): Likewise.
257 (VEX_W_0FE6_P_1): Likewise.
258 (VEX_W_0FE6_P_2): Likewise.
259 (VEX_W_0FE6_P_3): Likewise.
260 (VEX_W_0FE7_P_2_M_0): Likewise.
261 (VEX_W_0FE8_P_2): Likewise.
262 (VEX_W_0FE9_P_2): Likewise.
263 (VEX_W_0FEA_P_2): Likewise.
264 (VEX_W_0FEB_P_2): Likewise.
265 (VEX_W_0FEC_P_2): Likewise.
266 (VEX_W_0FED_P_2): Likewise.
267 (VEX_W_0FEE_P_2): Likewise.
268 (VEX_W_0FEF_P_2): Likewise.
269 (VEX_W_0FF0_P_3_M_0): Likewise.
270 (VEX_W_0FF1_P_2): Likewise.
271 (VEX_W_0FF2_P_2): Likewise.
272 (VEX_W_0FF3_P_2): Likewise.
273 (VEX_W_0FF4_P_2): Likewise.
274 (VEX_W_0FF5_P_2): Likewise.
275 (VEX_W_0FF6_P_2): Likewise.
276 (VEX_W_0FF7_P_2): Likewise.
277 (VEX_W_0FF8_P_2): Likewise.
278 (VEX_W_0FF9_P_2): Likewise.
279 (VEX_W_0FFA_P_2): Likewise.
280 (VEX_W_0FFB_P_2): Likewise.
281 (VEX_W_0FFC_P_2): Likewise.
282 (VEX_W_0FFD_P_2): Likewise.
283 (VEX_W_0FFE_P_2): Likewise.
284 (VEX_W_0F3800_P_2): Likewise.
285 (VEX_W_0F3801_P_2): Likewise.
286 (VEX_W_0F3802_P_2): Likewise.
287 (VEX_W_0F3803_P_2): Likewise.
288 (VEX_W_0F3804_P_2): Likewise.
289 (VEX_W_0F3805_P_2): Likewise.
290 (VEX_W_0F3806_P_2): Likewise.
291 (VEX_W_0F3807_P_2): Likewise.
292 (VEX_W_0F3808_P_2): Likewise.
293 (VEX_W_0F3809_P_2): Likewise.
294 (VEX_W_0F380A_P_2): Likewise.
295 (VEX_W_0F380B_P_2): Likewise.
296 (VEX_W_0F3817_P_2): Likewise.
297 (VEX_W_0F381C_P_2): Likewise.
298 (VEX_W_0F381D_P_2): Likewise.
299 (VEX_W_0F381E_P_2): Likewise.
300 (VEX_W_0F3820_P_2): Likewise.
301 (VEX_W_0F3821_P_2): Likewise.
302 (VEX_W_0F3822_P_2): Likewise.
303 (VEX_W_0F3823_P_2): Likewise.
304 (VEX_W_0F3824_P_2): Likewise.
305 (VEX_W_0F3825_P_2): Likewise.
306 (VEX_W_0F3828_P_2): Likewise.
307 (VEX_W_0F3829_P_2): Likewise.
308 (VEX_W_0F382A_P_2_M_0): Likewise.
309 (VEX_W_0F382B_P_2): Likewise.
310 (VEX_W_0F3830_P_2): Likewise.
311 (VEX_W_0F3831_P_2): Likewise.
312 (VEX_W_0F3832_P_2): Likewise.
313 (VEX_W_0F3833_P_2): Likewise.
314 (VEX_W_0F3834_P_2): Likewise.
315 (VEX_W_0F3835_P_2): Likewise.
316 (VEX_W_0F3837_P_2): Likewise.
317 (VEX_W_0F3838_P_2): Likewise.
318 (VEX_W_0F3839_P_2): Likewise.
319 (VEX_W_0F383A_P_2): Likewise.
320 (VEX_W_0F383B_P_2): Likewise.
321 (VEX_W_0F383C_P_2): Likewise.
322 (VEX_W_0F383D_P_2): Likewise.
323 (VEX_W_0F383E_P_2): Likewise.
324 (VEX_W_0F383F_P_2): Likewise.
325 (VEX_W_0F3840_P_2): Likewise.
326 (VEX_W_0F3841_P_2): Likewise.
327 (VEX_W_0F38DB_P_2): Likewise.
328 (VEX_W_0F3A08_P_2): Likewise.
329 (VEX_W_0F3A09_P_2): Likewise.
330 (VEX_W_0F3A0A_P_2): Likewise.
331 (VEX_W_0F3A0B_P_2): Likewise.
332 (VEX_W_0F3A0C_P_2): Likewise.
333 (VEX_W_0F3A0D_P_2): Likewise.
334 (VEX_W_0F3A0E_P_2): Likewise.
335 (VEX_W_0F3A0F_P_2): Likewise.
336 (VEX_W_0F3A21_P_2): Likewise.
337 (VEX_W_0F3A40_P_2): Likewise.
338 (VEX_W_0F3A41_P_2): Likewise.
339 (VEX_W_0F3A42_P_2): Likewise.
340 (VEX_W_0F3A62_P_2): Likewise.
341 (VEX_W_0F3A63_P_2): Likewise.
342 (VEX_W_0F3ADF_P_2): Likewise.
343 (VEX_LEN_0F77_P_0): New.
344 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
345 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
346 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
347 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
348 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
349 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
350 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
351 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
352 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
353 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
354 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
355 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
356 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
357 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
358 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
359 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
360 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
361 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
362 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
363 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
364 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
365 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
366 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
367 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
368 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
369 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
370 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
371 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
372 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
373 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
374 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
375 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
376 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
377 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
378 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
379 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
380 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
381 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
382 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
383 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
384 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
385 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
386 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
387 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
388 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
389 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
390 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
391 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
392 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
393 (vex_table): Update VEX 0F28 and 0F29 entries.
394 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
395 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
396 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
397 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
398 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
399 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
400 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
401 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
402 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
403 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
404 VEX_LEN_0F3A0B_P_2 entries.
405 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
406 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
407 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
408 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
409 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
410 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
411 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
412 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
413 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
414 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
415 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
416 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
417 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
418 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
419 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
420 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
421 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
422 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
423 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
424 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
425 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
426 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
427 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
428 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
429 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
430 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
431 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
432 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
433 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
434 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
435 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
436 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
437 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
438 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
439 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
440 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
441 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
442 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
443 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
444 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
445 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
446 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
447 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
448 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
449 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
450 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
451 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
452 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
453 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
454 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
455 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
456 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
457 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
458 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
459 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
460 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
461 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
462 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
463 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
464 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
465 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
466 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
467 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
468 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
469 VEX_W_0F3ADF_P_2 entries.
470 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
471 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
472 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
474 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
476 * i386-opc.tbl (VexWIG): New.
477 Replace VexW=3 with VexWIG.
479 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
481 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
482 * i386-tbl.h: Regenerated.
484 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
487 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
488 VEX_LEN_0FD6_P_2 entries.
489 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
490 * i386-tbl.h: Regenerated.
492 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
495 * i386-opc.h (VEXWIG): New.
496 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
497 * i386-tbl.h: Regenerated.
499 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
502 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
503 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
504 * i386-dis.c (EXxEVexR64): New.
505 (evex_rounding_64_mode): Likewise.
506 (OP_Rounding): Handle evex_rounding_64_mode.
508 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
511 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
512 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
513 * i386-dis.c (Edqa): New.
514 (dqa_mode): Likewise.
515 (intel_operand_size): Handle dqa_mode as m_mode.
516 (OP_E_register): Handle dqa_mode as dq_mode.
517 (OP_E_memory): Set shift for dqa_mode based on address_mode.
519 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
521 * i386-dis.c (OP_E_memory): Reformat.
523 2018-09-14 Jan Beulich <jbeulich@suse.com>
525 * i386-opc.tbl (crc32): Fold byte and word forms.
526 * i386-tbl.h: Re-generate.
528 2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
530 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
531 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
532 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
533 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
534 * i386-tbl.h: Regenerated.
536 2018-09-13 Jan Beulich <jbeulich@suse.com>
538 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
540 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
541 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
542 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
543 * i386-tbl.h: Re-generate.
545 2018-09-13 Jan Beulich <jbeulich@suse.com>
547 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
549 * i386-tbl.h: Re-generate.
551 2018-09-13 Jan Beulich <jbeulich@suse.com>
553 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
555 * i386-tbl.h: Re-generate.
557 2018-09-13 Jan Beulich <jbeulich@suse.com>
559 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
561 * i386-tbl.h: Re-generate.
563 2018-09-13 Jan Beulich <jbeulich@suse.com>
565 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
567 * i386-tbl.h: Re-generate.
569 2018-09-13 Jan Beulich <jbeulich@suse.com>
571 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
573 * i386-tbl.h: Re-generate.
575 2018-09-13 Jan Beulich <jbeulich@suse.com>
577 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
579 * i386-tbl.h: Re-generate.
581 2018-09-13 Jan Beulich <jbeulich@suse.com>
583 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
584 * i386-tbl.h: Re-generate.
586 2018-09-13 Jan Beulich <jbeulich@suse.com>
588 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
589 * i386-tbl.h: Re-generate.
591 2018-09-13 Jan Beulich <jbeulich@suse.com>
593 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
595 * i386-tbl.h: Re-generate.
597 2018-09-13 Jan Beulich <jbeulich@suse.com>
599 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
601 * i386-tbl.h: Re-generate.
603 2018-09-13 Jan Beulich <jbeulich@suse.com>
605 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
606 * i386-tbl.h: Re-generate.
608 2018-09-13 Jan Beulich <jbeulich@suse.com>
610 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
611 * i386-tbl.h: Re-generate.
613 2018-09-13 Jan Beulich <jbeulich@suse.com>
615 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
616 * i386-tbl.h: Re-generate.
618 2018-09-13 Jan Beulich <jbeulich@suse.com>
620 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
622 * i386-tbl.h: Re-generate.
624 2018-09-13 Jan Beulich <jbeulich@suse.com>
626 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
628 * i386-tbl.h: Re-generate.
630 2018-09-13 Jan Beulich <jbeulich@suse.com>
632 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
634 * i386-tbl.h: Re-generate.
636 2018-09-13 Jan Beulich <jbeulich@suse.com>
638 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
639 * i386-tbl.h: Re-generate.
641 2018-09-13 Jan Beulich <jbeulich@suse.com>
643 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
644 * i386-tbl.h: Re-generate.
646 2018-09-13 Jan Beulich <jbeulich@suse.com>
648 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
649 * i386-tbl.h: Re-generate.
651 2018-09-13 Jan Beulich <jbeulich@suse.com>
653 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
654 (vpbroadcastw, rdpid): Drop NoRex64.
655 * i386-tbl.h: Re-generate.
657 2018-09-13 Jan Beulich <jbeulich@suse.com>
659 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
660 store templates, adding D.
661 * i386-tbl.h: Re-generate.
663 2018-09-13 Jan Beulich <jbeulich@suse.com>
665 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
666 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
667 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
668 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
669 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
670 Fold load and store templates where possible, adding D. Drop
671 IgnoreSize where it was pointlessly present. Drop redundant
673 * i386-tbl.h: Re-generate.
675 2018-09-13 Jan Beulich <jbeulich@suse.com>
677 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
678 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
679 (intel_operand_size): Handle v_bndmk_mode.
680 (OP_E_memory): Likewise. Produce (bad) when also riprel.
682 2018-09-08 John Darrington <john@darrington.wattle.id.au>
684 * disassemble.c (ARCH_s12z): Define if ARCH_all.
686 2018-08-31 Kito Cheng <kito@andestech.com>
688 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
689 compressed floating point instructions.
691 2018-08-30 Kito Cheng <kito@andestech.com>
693 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
694 riscv_opcode.xlen_requirement.
695 * riscv-opc.c (riscv_opcodes): Update for struct change.
697 2018-08-29 Martin Aberg <maberg@gaisler.com>
699 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
700 psr (PWRPSR) instruction.
702 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
704 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
706 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
708 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
710 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
712 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
713 loongson3a as an alias of gs464 for compatibility.
714 * mips-opc.c (mips_opcodes): Change Comments.
716 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
718 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
720 (print_mips_disassembler_options): Document -M loongson-ext.
721 * mips-opc.c (LEXT2): New macro.
722 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
724 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
726 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
728 (parse_mips_ase_option): Handle -M loongson-ext option.
729 (print_mips_disassembler_options): Document -M loongson-ext.
730 * mips-opc.c (IL3A): Delete.
731 * mips-opc.c (LEXT): New macro.
732 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
735 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
737 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
739 (parse_mips_ase_option): Handle -M loongson-cam option.
740 (print_mips_disassembler_options): Document -M loongson-cam.
741 * mips-opc.c (LCAM): New macro.
742 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
745 2018-08-21 Alan Modra <amodra@gmail.com>
747 * ppc-dis.c (operand_value_powerpc): Init "invalid".
748 (skip_optional_operands): Count optional operands, and update
749 ppc_optional_operand_value call.
750 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
751 (extract_vlensi): Likewise.
752 (extract_fxm): Return default value for missing optional operand.
753 (extract_ls, extract_raq, extract_tbr): Likewise.
754 (insert_sxl, extract_sxl): New functions.
755 (insert_esync, extract_esync): Remove Power9 handling and simplify.
756 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
757 flag and extra entry.
758 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
761 2018-08-20 Alan Modra <amodra@gmail.com>
763 * sh-opc.h (MASK): Simplify.
765 2018-08-18 John Darrington <john@darrington.wattle.id.au>
767 * s12z-dis.c (bm_decode): Deal with cases where the mode is
768 BM_RESERVED0 or BM_RESERVED1
769 (bm_rel_decode, bm_n_bytes): Ditto.
771 2018-08-18 John Darrington <john@darrington.wattle.id.au>
775 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
777 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
778 address with the addr32 prefix and without base nor index
781 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
783 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
784 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
785 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
786 (cpu_flags): Add CpuCMOV and CpuFXSR.
787 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
788 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
789 * i386-init.h: Regenerated.
790 * i386-tbl.h: Likewise.
792 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
794 * arc-regs.h: Update auxiliary registers.
796 2018-08-06 Jan Beulich <jbeulich@suse.com>
798 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
799 (RegIP, RegIZ): Define.
800 * i386-reg.tbl: Adjust comments.
801 (rip): Use Qword instead of BaseIndex. Use RegIP.
802 (eip): Use Dword instead of BaseIndex. Use RegIP.
803 (riz): Add Qword. Use RegIZ.
804 (eiz): Add Dword. Use RegIZ.
805 * i386-tbl.h: Re-generate.
807 2018-08-03 Jan Beulich <jbeulich@suse.com>
809 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
810 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
811 vpmovzxdq, vpmovzxwd): Remove NoRex64.
812 * i386-tbl.h: Re-generate.
814 2018-08-03 Jan Beulich <jbeulich@suse.com>
816 * i386-gen.c (operand_types): Remove Mem field.
817 * i386-opc.h (union i386_operand_type): Remove mem field.
818 * i386-init.h, i386-tbl.h: Re-generate.
820 2018-08-01 Alan Modra <amodra@gmail.com>
822 * po/POTFILES.in: Regenerate.
824 2018-07-31 Nick Clifton <nickc@redhat.com>
826 * po/sv.po: Updated Swedish translation.
828 2018-07-31 Jan Beulich <jbeulich@suse.com>
830 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
831 * i386-init.h, i386-tbl.h: Re-generate.
833 2018-07-31 Jan Beulich <jbeulich@suse.com>
835 * i386-opc.h (ZEROING_MASKING) Rename to ...
836 (DYNAMIC_MASKING): ... this. Adjust comment.
837 * i386-opc.tbl (MaskingMorZ): Define.
838 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
839 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
840 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
841 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
842 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
843 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
844 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
845 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
846 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
848 2018-07-31 Jan Beulich <jbeulich@suse.com>
850 * i386-opc.tbl: Use element rather than vector size for AVX512*
851 scatter/gather insns.
852 * i386-tbl.h: Re-generate.
854 2018-07-31 Jan Beulich <jbeulich@suse.com>
856 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
857 (cpu_flags): Drop CpuVREX.
858 * i386-opc.h (CpuVREX): Delete.
859 (union i386_cpu_flags): Remove cpuvrex.
860 * i386-init.h, i386-tbl.h: Re-generate.
862 2018-07-30 Jim Wilson <jimw@sifive.com>
864 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
866 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
868 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
870 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
871 * Makefile.in: Regenerated.
872 * configure.ac: Add C-SKY.
873 * configure: Regenerated.
874 * csky-dis.c: New file.
875 * csky-opc.h: New file.
876 * disassemble.c (ARCH_csky): Define.
877 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
878 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
880 2018-07-27 Alan Modra <amodra@gmail.com>
882 * ppc-opc.c (insert_sprbat): Correct function parameter and
884 (extract_sprbat): Likewise, variable too.
886 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
887 Alan Modra <amodra@gmail.com>
889 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
890 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
891 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
892 support disjointed BAT.
893 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
894 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
895 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
897 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
898 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
900 * i386-gen.c (adjust_broadcast_modifier): New function.
901 (process_i386_opcode_modifier): Add an argument for operands.
902 Adjust the Broadcast value based on operands.
903 (output_i386_opcode): Pass operand_types to
904 process_i386_opcode_modifier.
905 (process_i386_opcodes): Pass NULL as operands to
906 process_i386_opcode_modifier.
907 * i386-opc.h (BYTE_BROADCAST): New.
908 (WORD_BROADCAST): Likewise.
909 (DWORD_BROADCAST): Likewise.
910 (QWORD_BROADCAST): Likewise.
911 (i386_opcode_modifier): Expand broadcast to 3 bits.
912 * i386-tbl.h: Regenerated.
914 2018-07-24 Alan Modra <amodra@gmail.com>
917 * or1k-desc.h: Regenerate.
919 2018-07-24 Jan Beulich <jbeulich@suse.com>
921 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
922 vcvtusi2ss, and vcvtusi2sd.
923 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
924 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
925 * i386-tbl.h: Re-generate.
927 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
929 * arc-opc.c (extract_w6): Fix extending the sign.
931 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
933 * arc-tbl.h (vewt): Allow it for ARC EM family.
935 2018-07-23 Alan Modra <amodra@gmail.com>
938 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
939 opcode variants for mtspr/mfspr encodings.
941 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
942 Maciej W. Rozycki <macro@mips.com>
944 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
945 loongson3a descriptors.
946 (parse_mips_ase_option): Handle -M loongson-mmi option.
947 (print_mips_disassembler_options): Document -M loongson-mmi.
948 * mips-opc.c (LMMI): New macro.
949 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
952 2018-07-19 Jan Beulich <jbeulich@suse.com>
954 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
955 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
956 IgnoreSize and [XYZ]MMword where applicable.
957 * i386-tbl.h: Re-generate.
959 2018-07-19 Jan Beulich <jbeulich@suse.com>
961 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
962 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
963 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
964 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
965 * i386-tbl.h: Re-generate.
967 2018-07-19 Jan Beulich <jbeulich@suse.com>
969 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
970 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
971 VPCLMULQDQ templates into their respective AVX512VL counterparts
972 where possible, using Disp8ShiftVL and CheckRegSize instead of
973 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
974 * i386-tbl.h: Re-generate.
976 2018-07-19 Jan Beulich <jbeulich@suse.com>
978 * i386-opc.tbl: Fold AVX512DQ templates into their respective
979 AVX512VL counterparts where possible, using Disp8ShiftVL and
980 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
981 IgnoreSize) as appropriate.
982 * i386-tbl.h: Re-generate.
984 2018-07-19 Jan Beulich <jbeulich@suse.com>
986 * i386-opc.tbl: Fold AVX512BW templates into their respective
987 AVX512VL counterparts where possible, using Disp8ShiftVL and
988 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
989 IgnoreSize) as appropriate.
990 * i386-tbl.h: Re-generate.
992 2018-07-19 Jan Beulich <jbeulich@suse.com>
994 * i386-opc.tbl: Fold AVX512CD templates into their respective
995 AVX512VL counterparts where possible, using Disp8ShiftVL and
996 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
997 IgnoreSize) as appropriate.
998 * i386-tbl.h: Re-generate.
1000 2018-07-19 Jan Beulich <jbeulich@suse.com>
1002 * i386-opc.h (DISP8_SHIFT_VL): New.
1003 * i386-opc.tbl (Disp8ShiftVL): Define.
1004 (various): Fold AVX512VL templates into their respective
1005 AVX512F counterparts where possible, using Disp8ShiftVL and
1006 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1007 IgnoreSize) as appropriate.
1008 * i386-tbl.h: Re-generate.
1010 2018-07-19 Jan Beulich <jbeulich@suse.com>
1012 * Makefile.am: Change dependencies and rule for
1013 $(srcdir)/i386-init.h.
1014 * Makefile.in: Re-generate.
1015 * i386-gen.c (process_i386_opcodes): New local variable
1016 "marker". Drop opening of input file. Recognize marker and line
1018 * i386-opc.tbl (OPCODE_I386_H): Define.
1019 (i386-opc.h): Include it.
1022 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1025 * i386-opc.h (Byte): Update comments.
1031 (Xmmword): Likewise.
1032 (Ymmword): Likewise.
1033 (Zmmword): Likewise.
1034 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1036 * i386-tbl.h: Regenerated.
1038 2018-07-12 Sudakshina Das <sudi.das@arm.com>
1040 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1041 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1042 * aarch64-asm-2.c: Regenerate.
1043 * aarch64-dis-2.c: Regenerate.
1044 * aarch64-opc-2.c: Regenerate.
1046 2018-07-12 Tamar Christina <tamar.christina@arm.com>
1049 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1050 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1051 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1052 sqdmulh, sqrdmulh): Use Em16.
1054 2018-07-11 Sudakshina Das <sudi.das@arm.com>
1056 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1057 csdb together with them.
1058 (thumb32_opcodes): Likewise.
1060 2018-07-11 Jan Beulich <jbeulich@suse.com>
1062 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1063 requiring 32-bit registers as operands 2 and 3. Improve
1065 (mwait, mwaitx): Fold templates. Improve comments.
1066 OPERAND_TYPE_INOUTPORTREG.
1067 * i386-tbl.h: Re-generate.
1069 2018-07-11 Jan Beulich <jbeulich@suse.com>
1071 * i386-gen.c (operand_type_init): Remove
1072 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1073 OPERAND_TYPE_INOUTPORTREG.
1074 * i386-init.h: Re-generate.
1076 2018-07-11 Jan Beulich <jbeulich@suse.com>
1078 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1079 (wrssq, wrussq): Add Qword.
1080 * i386-tbl.h: Re-generate.
1082 2018-07-11 Jan Beulich <jbeulich@suse.com>
1084 * i386-opc.h: Rename OTMax to OTNum.
1085 (OTNumOfUints): Adjust calculation.
1086 (OTUnused): Directly alias to OTNum.
1088 2018-07-09 Maciej W. Rozycki <macro@mips.com>
1090 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1092 (lea_reg_xys): Likewise.
1093 (print_insn_loop_primitive): Rename `reg' local variable to
1096 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1099 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1101 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1104 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1105 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1107 2018-07-02 Maciej W. Rozycki <macro@mips.com>
1110 * mips-dis.c (mips_option_arg_t): New enumeration.
1111 (mips_options): New variable.
1112 (disassembler_options_mips): New function.
1113 (print_mips_disassembler_options): Reimplement in terms of
1114 `disassembler_options_mips'.
1115 * arm-dis.c (disassembler_options_arm): Adapt to using the
1116 `disasm_options_and_args_t' structure.
1117 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1118 * s390-dis.c (disassembler_options_s390): Likewise.
1120 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1122 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1124 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1125 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1126 * testsuite/ld-arm/tls-longplt.d: Likewise.
1128 2018-06-29 Tamar Christina <tamar.christina@arm.com>
1131 * aarch64-asm-2.c: Regenerate.
1132 * aarch64-dis-2.c: Likewise.
1133 * aarch64-opc-2.c: Likewise.
1134 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1135 * aarch64-opc.c (operand_general_constraint_met_p,
1136 aarch64_print_operand): Likewise.
1137 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1138 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1140 (AARCH64_OPERANDS): Add Em2.
1142 2018-06-26 Nick Clifton <nickc@redhat.com>
1144 * po/uk.po: Updated Ukranian translation.
1145 * po/de.po: Updated German translation.
1146 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1148 2018-06-26 Nick Clifton <nickc@redhat.com>
1150 * nfp-dis.c: Fix spelling mistake.
1152 2018-06-24 Nick Clifton <nickc@redhat.com>
1154 * configure: Regenerate.
1155 * po/opcodes.pot: Regenerate.
1157 2018-06-24 Nick Clifton <nickc@redhat.com>
1159 2.31 branch created.
1161 2018-06-19 Tamar Christina <tamar.christina@arm.com>
1163 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1164 * aarch64-asm-2.c: Regenerate.
1165 * aarch64-dis-2.c: Likewise.
1167 2018-06-21 Maciej W. Rozycki <macro@mips.com>
1169 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1170 `-M ginv' option description.
1172 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1175 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1178 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1180 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1181 * configure.ac: Remove AC_PREREQ.
1182 * Makefile.in: Re-generate.
1183 * aclocal.m4: Re-generate.
1184 * configure: Re-generate.
1186 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1188 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1189 mips64r6 descriptors.
1190 (parse_mips_ase_option): Handle -Mginv option.
1191 (print_mips_disassembler_options): Document -Mginv.
1192 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1194 (mips_opcodes): Define ginvi and ginvt.
1196 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1197 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1199 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1200 * mips-opc.c (CRC, CRC64): New macros.
1201 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1202 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1205 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1208 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1209 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1211 2018-06-06 Alan Modra <amodra@gmail.com>
1213 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1214 setjmp. Move init for some other vars later too.
1216 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1218 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1219 (dis_private): Add new fields for property section tracking.
1220 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1221 (xtensa_instruction_fits): New functions.
1222 (fetch_data): Bump minimal fetch size to 4.
1223 (print_insn_xtensa): Make struct dis_private static.
1224 Load and prepare property table on section change.
1225 Don't disassemble literals. Don't disassemble instructions that
1226 cross property table boundaries.
1228 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1230 * configure: Regenerated.
1232 2018-06-01 Jan Beulich <jbeulich@suse.com>
1234 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1235 * i386-tbl.h: Re-generate.
1237 2018-06-01 Jan Beulich <jbeulich@suse.com>
1239 * i386-opc.tbl (sldt, str): Add NoRex64.
1240 * i386-tbl.h: Re-generate.
1242 2018-06-01 Jan Beulich <jbeulich@suse.com>
1244 * i386-opc.tbl (invpcid): Add Oword.
1245 * i386-tbl.h: Re-generate.
1247 2018-06-01 Alan Modra <amodra@gmail.com>
1249 * sysdep.h (_bfd_error_handler): Don't declare.
1250 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1251 * rl78-decode.opc: Likewise.
1252 * msp430-decode.c: Regenerate.
1253 * rl78-decode.c: Regenerate.
1255 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1257 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1258 * i386-init.h : Regenerated.
1260 2018-05-25 Alan Modra <amodra@gmail.com>
1262 * Makefile.in: Regenerate.
1263 * po/POTFILES.in: Regenerate.
1265 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1267 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1268 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1269 (insert_bab, extract_bab, insert_btab, extract_btab,
1270 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1271 (BAT, BBA VBA RBS XB6S): Delete macros.
1272 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1273 (BB, BD, RBX, XC6): Update for new macros.
1274 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1275 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1276 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1277 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1279 2018-05-18 John Darrington <john@darrington.wattle.id.au>
1281 * Makefile.am: Add support for s12z architecture.
1282 * configure.ac: Likewise.
1283 * disassemble.c: Likewise.
1284 * disassemble.h: Likewise.
1285 * Makefile.in: Regenerate.
1286 * configure: Regenerate.
1287 * s12z-dis.c: New file.
1290 2018-05-18 Alan Modra <amodra@gmail.com>
1292 * nfp-dis.c: Don't #include libbfd.h.
1293 (init_nfp3200_priv): Use bfd_get_section_contents.
1294 (nit_nfp6000_mecsr_sec): Likewise.
1296 2018-05-17 Nick Clifton <nickc@redhat.com>
1298 * po/zh_CN.po: Updated simplified Chinese translation.
1300 2018-05-16 Tamar Christina <tamar.christina@arm.com>
1303 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1304 * aarch64-dis-2.c: Regenerate.
1306 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1309 * aarch64-asm.c (opintl.h): Include.
1310 (aarch64_ins_sysreg): Enforce read/write constraints.
1311 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1312 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1313 (F_REG_READ, F_REG_WRITE): New.
1314 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1315 AARCH64_OPND_SYSREG.
1316 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1317 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1318 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1319 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1320 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1321 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1322 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1323 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1324 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1325 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1326 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1327 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1328 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1329 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1330 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1331 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1332 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1334 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1337 * aarch64-dis.c (no_notes: New.
1338 (parse_aarch64_dis_option): Support notes.
1339 (aarch64_decode_insn, print_operands): Likewise.
1340 (print_aarch64_disassembler_options): Document notes.
1341 * aarch64-opc.c (aarch64_print_operand): Support notes.
1343 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1346 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1347 and take error struct.
1348 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1349 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1350 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1351 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1352 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1353 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1354 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1355 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1356 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1357 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1358 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1359 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1360 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1361 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1362 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1363 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1364 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1365 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1366 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1367 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1368 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1369 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1370 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1371 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1372 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1373 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1374 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1375 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1376 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1377 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1378 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1379 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1380 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1381 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1382 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1383 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1384 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1385 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1386 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1387 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1388 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1389 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1390 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1391 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1392 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1393 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1394 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1395 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1396 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1397 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1398 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1399 (determine_disassembling_preference, aarch64_decode_insn,
1400 print_insn_aarch64_word, print_insn_data): Take errors struct.
1401 (print_insn_aarch64): Use errors.
1402 * aarch64-asm-2.c: Regenerate.
1403 * aarch64-dis-2.c: Regenerate.
1404 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1405 boolean in aarch64_insert_operan.
1406 (print_operand_extractor): Likewise.
1407 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1409 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
1411 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1413 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1415 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1417 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1419 * cr16-opc.c (cr16_instruction): Comment typo fix.
1420 * hppa-dis.c (print_insn_hppa): Likewise.
1422 2018-05-08 Jim Wilson <jimw@sifive.com>
1424 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1425 (match_c_slli64, match_srxi_as_c_srxi): New.
1426 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1427 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1428 <c.slli, c.srli, c.srai>: Use match_s_slli.
1429 <c.slli64, c.srli64, c.srai64>: New.
1431 2018-05-08 Alan Modra <amodra@gmail.com>
1433 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1434 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1435 partition opcode space for index lookup.
1437 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1439 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1440 <insn_length>: ...with this. Update usage.
1441 Remove duplicate call to *info->memory_error_func.
1443 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1444 H.J. Lu <hongjiu.lu@intel.com>
1446 * i386-dis.c (Gva): New.
1447 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1448 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1449 (prefix_table): New instructions (see prefix above).
1450 (mod_table): New instructions (see prefix above).
1451 (OP_G): Handle va_mode.
1452 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1453 CPU_MOVDIR64B_FLAGS.
1454 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1455 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1456 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1457 * i386-opc.tbl: Add movidir{i,64b}.
1458 * i386-init.h: Regenerated.
1459 * i386-tbl.h: Likewise.
1461 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1463 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1465 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1466 (AddrPrefixOpReg): This.
1467 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1468 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1470 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1472 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1473 (vle_num_opcodes): Likewise.
1474 (spe2_num_opcodes): Likewise.
1475 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1476 initialization loop.
1477 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1478 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1481 2018-05-01 Tamar Christina <tamar.christina@arm.com>
1483 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1485 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
1487 Makefile.am: Added nfp-dis.c.
1488 configure.ac: Added bfd_nfp_arch.
1489 disassemble.h: Added print_insn_nfp prototype.
1490 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1491 nfp-dis.c: New, for NFP support.
1492 po/POTFILES.in: Added nfp-dis.c to the list.
1493 Makefile.in: Regenerate.
1494 configure: Regenerate.
1496 2018-04-26 Jan Beulich <jbeulich@suse.com>
1498 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1499 templates into their base ones.
1500 * i386-tlb.h: Re-generate.
1502 2018-04-26 Jan Beulich <jbeulich@suse.com>
1504 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1505 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1506 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1507 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1508 * i386-init.h: Re-generate.
1510 2018-04-26 Jan Beulich <jbeulich@suse.com>
1512 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1513 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1514 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1515 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1517 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1519 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1521 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1522 cpuregzmm, and cpuregmask.
1523 * i386-init.h: Re-generate.
1524 * i386-tbl.h: Re-generate.
1526 2018-04-26 Jan Beulich <jbeulich@suse.com>
1528 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1529 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1530 * i386-init.h: Re-generate.
1532 2018-04-26 Jan Beulich <jbeulich@suse.com>
1534 * i386-gen.c (VexImmExt): Delete.
1535 * i386-opc.h (VexImmExt, veximmext): Delete.
1536 * i386-opc.tbl: Drop all VexImmExt uses.
1537 * i386-tlb.h: Re-generate.
1539 2018-04-25 Jan Beulich <jbeulich@suse.com>
1541 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1542 register-only forms.
1543 * i386-tlb.h: Re-generate.
1545 2018-04-25 Tamar Christina <tamar.christina@arm.com>
1547 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1549 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1551 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1553 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1554 (cpu_flags): Add CpuCLDEMOTE.
1555 * i386-init.h: Regenerate.
1556 * i386-opc.h (enum): Add CpuCLDEMOTE,
1557 (i386_cpu_flags): Add cpucldemote.
1558 * i386-opc.tbl: Add cldemote.
1559 * i386-tbl.h: Regenerate.
1561 2018-04-16 Alan Modra <amodra@gmail.com>
1563 * Makefile.am: Remove sh5 and sh64 support.
1564 * configure.ac: Likewise.
1565 * disassemble.c: Likewise.
1566 * disassemble.h: Likewise.
1567 * sh-dis.c: Likewise.
1568 * sh64-dis.c: Delete.
1569 * sh64-opc.c: Delete.
1570 * sh64-opc.h: Delete.
1571 * Makefile.in: Regenerate.
1572 * configure: Regenerate.
1573 * po/POTFILES.in: Regenerate.
1575 2018-04-16 Alan Modra <amodra@gmail.com>
1577 * Makefile.am: Remove w65 support.
1578 * configure.ac: Likewise.
1579 * disassemble.c: Likewise.
1580 * disassemble.h: Likewise.
1581 * w65-dis.c: Delete.
1582 * w65-opc.h: Delete.
1583 * Makefile.in: Regenerate.
1584 * configure: Regenerate.
1585 * po/POTFILES.in: Regenerate.
1587 2018-04-16 Alan Modra <amodra@gmail.com>
1589 * configure.ac: Remove we32k support.
1590 * configure: Regenerate.
1592 2018-04-16 Alan Modra <amodra@gmail.com>
1594 * Makefile.am: Remove m88k support.
1595 * configure.ac: Likewise.
1596 * disassemble.c: Likewise.
1597 * disassemble.h: Likewise.
1598 * m88k-dis.c: Delete.
1599 * Makefile.in: Regenerate.
1600 * configure: Regenerate.
1601 * po/POTFILES.in: Regenerate.
1603 2018-04-16 Alan Modra <amodra@gmail.com>
1605 * Makefile.am: Remove i370 support.
1606 * configure.ac: Likewise.
1607 * disassemble.c: Likewise.
1608 * disassemble.h: Likewise.
1609 * i370-dis.c: Delete.
1610 * i370-opc.c: Delete.
1611 * Makefile.in: Regenerate.
1612 * configure: Regenerate.
1613 * po/POTFILES.in: Regenerate.
1615 2018-04-16 Alan Modra <amodra@gmail.com>
1617 * Makefile.am: Remove h8500 support.
1618 * configure.ac: Likewise.
1619 * disassemble.c: Likewise.
1620 * disassemble.h: Likewise.
1621 * h8500-dis.c: Delete.
1622 * h8500-opc.h: Delete.
1623 * Makefile.in: Regenerate.
1624 * configure: Regenerate.
1625 * po/POTFILES.in: Regenerate.
1627 2018-04-16 Alan Modra <amodra@gmail.com>
1629 * configure.ac: Remove tahoe support.
1630 * configure: Regenerate.
1632 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1634 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1636 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1638 * i386-tbl.h: Regenerated.
1640 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1642 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1643 PREFIX_MOD_1_0FAE_REG_6.
1645 (OP_E_register): Use va_mode.
1646 * i386-dis-evex.h (prefix_table):
1647 New instructions (see prefixes above).
1648 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1649 (cpu_flags): Likewise.
1650 * i386-opc.h (enum): Likewise.
1651 (i386_cpu_flags): Likewise.
1652 * i386-opc.tbl: Add umonitor, umwait, tpause.
1653 * i386-init.h: Regenerate.
1654 * i386-tbl.h: Likewise.
1656 2018-04-11 Alan Modra <amodra@gmail.com>
1658 * opcodes/i860-dis.c: Delete.
1659 * opcodes/i960-dis.c: Delete.
1660 * Makefile.am: Remove i860 and i960 support.
1661 * configure.ac: Likewise.
1662 * disassemble.c: Likewise.
1663 * disassemble.h: Likewise.
1664 * Makefile.in: Regenerate.
1665 * configure: Regenerate.
1666 * po/POTFILES.in: Regenerate.
1668 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1671 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1673 (print_insn): Clear vex instead of vex.evex.
1675 2018-04-04 Nick Clifton <nickc@redhat.com>
1677 * po/es.po: Updated Spanish translation.
1679 2018-03-28 Jan Beulich <jbeulich@suse.com>
1681 * i386-gen.c (opcode_modifiers): Delete VecESize.
1682 * i386-opc.h (VecESize): Delete.
1683 (struct i386_opcode_modifier): Delete vecesize.
1684 * i386-opc.tbl: Drop VecESize.
1685 * i386-tlb.h: Re-generate.
1687 2018-03-28 Jan Beulich <jbeulich@suse.com>
1689 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1690 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1691 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1692 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1693 * i386-tlb.h: Re-generate.
1695 2018-03-28 Jan Beulich <jbeulich@suse.com>
1697 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1699 * i386-tlb.h: Re-generate.
1701 2018-03-28 Jan Beulich <jbeulich@suse.com>
1703 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1704 (vex_len_table): Drop Y for vcvt*2si.
1705 (putop): Replace plain 'Y' handling by abort().
1707 2018-03-28 Nick Clifton <nickc@redhat.com>
1710 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1711 instructions with only a base address register.
1712 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1713 handle AARHC64_OPND_SVE_ADDR_R.
1714 (aarch64_print_operand): Likewise.
1715 * aarch64-asm-2.c: Regenerate.
1716 * aarch64_dis-2.c: Regenerate.
1717 * aarch64-opc-2.c: Regenerate.
1719 2018-03-22 Jan Beulich <jbeulich@suse.com>
1721 * i386-opc.tbl: Drop VecESize from register only insn forms and
1722 memory forms not allowing broadcast.
1723 * i386-tlb.h: Re-generate.
1725 2018-03-22 Jan Beulich <jbeulich@suse.com>
1727 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1728 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1729 sha256*): Drop Disp<N>.
1731 2018-03-22 Jan Beulich <jbeulich@suse.com>
1733 * i386-dis.c (EbndS, bnd_swap_mode): New.
1734 (prefix_table): Use EbndS.
1735 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1736 * i386-opc.tbl (bndmov): Move misplaced Load.
1737 * i386-tlb.h: Re-generate.
1739 2018-03-22 Jan Beulich <jbeulich@suse.com>
1741 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1742 templates allowing memory operands and folded ones for register
1744 * i386-tlb.h: Re-generate.
1746 2018-03-22 Jan Beulich <jbeulich@suse.com>
1748 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1749 256-bit templates. Drop redundant leftover Disp<N>.
1750 * i386-tlb.h: Re-generate.
1752 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1754 * riscv-opc.c (riscv_insn_types): New.
1756 2018-03-13 Nick Clifton <nickc@redhat.com>
1758 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1760 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1762 * i386-opc.tbl: Add Optimize to clr.
1763 * i386-tbl.h: Regenerated.
1765 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1767 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1768 * i386-opc.h (OldGcc): Removed.
1769 (i386_opcode_modifier): Remove oldgcc.
1770 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1771 instructions for old (<= 2.8.1) versions of gcc.
1772 * i386-tbl.h: Regenerated.
1774 2018-03-08 Jan Beulich <jbeulich@suse.com>
1776 * i386-opc.h (EVEXDYN): New.
1777 * i386-opc.tbl: Fold various AVX512VL templates.
1778 * i386-tlb.h: Re-generate.
1780 2018-03-08 Jan Beulich <jbeulich@suse.com>
1782 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1783 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1784 vpexpandd, vpexpandq): Fold AFX512VF templates.
1785 * i386-tlb.h: Re-generate.
1787 2018-03-08 Jan Beulich <jbeulich@suse.com>
1789 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1790 Fold 128- and 256-bit VEX-encoded templates.
1791 * i386-tlb.h: Re-generate.
1793 2018-03-08 Jan Beulich <jbeulich@suse.com>
1795 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1796 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1797 vpexpandd, vpexpandq): Fold AVX512F templates.
1798 * i386-tlb.h: Re-generate.
1800 2018-03-08 Jan Beulich <jbeulich@suse.com>
1802 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1803 64-bit templates. Drop Disp<N>.
1804 * i386-tlb.h: Re-generate.
1806 2018-03-08 Jan Beulich <jbeulich@suse.com>
1808 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1809 and 256-bit templates.
1810 * i386-tlb.h: Re-generate.
1812 2018-03-08 Jan Beulich <jbeulich@suse.com>
1814 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1815 * i386-tlb.h: Re-generate.
1817 2018-03-08 Jan Beulich <jbeulich@suse.com>
1819 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1821 * i386-tlb.h: Re-generate.
1823 2018-03-08 Jan Beulich <jbeulich@suse.com>
1825 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1826 * i386-tlb.h: Re-generate.
1828 2018-03-08 Jan Beulich <jbeulich@suse.com>
1830 * i386-gen.c (opcode_modifiers): Delete FloatD.
1831 * i386-opc.h (FloatD): Delete.
1832 (struct i386_opcode_modifier): Delete floatd.
1833 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1835 * i386-tlb.h: Re-generate.
1837 2018-03-08 Jan Beulich <jbeulich@suse.com>
1839 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1841 2018-03-08 Jan Beulich <jbeulich@suse.com>
1843 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1844 * i386-tlb.h: Re-generate.
1846 2018-03-08 Jan Beulich <jbeulich@suse.com>
1848 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1850 * i386-tlb.h: Re-generate.
1852 2018-03-07 Alan Modra <amodra@gmail.com>
1854 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1856 * disassemble.h (print_insn_rs6000): Delete.
1857 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1858 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1859 (print_insn_rs6000): Delete.
1861 2018-03-03 Alan Modra <amodra@gmail.com>
1863 * sysdep.h (opcodes_error_handler): Define.
1864 (_bfd_error_handler): Declare.
1865 * Makefile.am: Remove stray #.
1866 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1868 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1869 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1870 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1871 opcodes_error_handler to print errors. Standardize error messages.
1872 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1873 and include opintl.h.
1874 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1875 * i386-gen.c: Standardize error messages.
1876 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1877 * Makefile.in: Regenerate.
1878 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1879 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1880 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1881 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1882 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1883 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1884 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1885 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1886 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1887 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1888 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1889 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1890 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1892 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1894 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1895 vpsub[bwdq] instructions.
1896 * i386-tbl.h: Regenerated.
1898 2018-03-01 Alan Modra <amodra@gmail.com>
1900 * configure.ac (ALL_LINGUAS): Sort.
1901 * configure: Regenerate.
1903 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1905 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1906 macro by assignements.
1908 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1911 * i386-gen.c (opcode_modifiers): Add Optimize.
1912 * i386-opc.h (Optimize): New enum.
1913 (i386_opcode_modifier): Add optimize.
1914 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1915 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1916 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1917 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1918 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1920 * i386-tbl.h: Regenerated.
1922 2018-02-26 Alan Modra <amodra@gmail.com>
1924 * crx-dis.c (getregliststring): Allocate a large enough buffer
1925 to silence false positive gcc8 warning.
1927 2018-02-22 Shea Levy <shea@shealevy.com>
1929 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1931 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1933 * i386-opc.tbl: Add {rex},
1934 * i386-tbl.h: Regenerated.
1936 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1938 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1939 (mips16_opcodes): Replace `M' with `m' for "restore".
1941 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1943 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1945 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1947 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1948 variable to `function_index'.
1950 2018-02-13 Nick Clifton <nickc@redhat.com>
1953 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1954 about truncation of printing.
1956 2018-02-12 Henry Wong <henry@stuffedcow.net>
1958 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1960 2018-02-05 Nick Clifton <nickc@redhat.com>
1962 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1964 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1966 * i386-dis.c (enum): Add pconfig.
1967 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1968 (cpu_flags): Add CpuPCONFIG.
1969 * i386-opc.h (enum): Add CpuPCONFIG.
1970 (i386_cpu_flags): Add cpupconfig.
1971 * i386-opc.tbl: Add PCONFIG instruction.
1972 * i386-init.h: Regenerate.
1973 * i386-tbl.h: Likewise.
1975 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1977 * i386-dis.c (enum): Add PREFIX_0F09.
1978 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1979 (cpu_flags): Add CpuWBNOINVD.
1980 * i386-opc.h (enum): Add CpuWBNOINVD.
1981 (i386_cpu_flags): Add cpuwbnoinvd.
1982 * i386-opc.tbl: Add WBNOINVD instruction.
1983 * i386-init.h: Regenerate.
1984 * i386-tbl.h: Likewise.
1986 2018-01-17 Jim Wilson <jimw@sifive.com>
1988 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1990 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1992 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1993 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1994 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1995 (cpu_flags): Add CpuIBT, CpuSHSTK.
1996 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1997 (i386_cpu_flags): Add cpuibt, cpushstk.
1998 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1999 * i386-init.h: Regenerate.
2000 * i386-tbl.h: Likewise.
2002 2018-01-16 Nick Clifton <nickc@redhat.com>
2004 * po/pt_BR.po: Updated Brazilian Portugese translation.
2005 * po/de.po: Updated German translation.
2007 2018-01-15 Jim Wilson <jimw@sifive.com>
2009 * riscv-opc.c (match_c_nop): New.
2010 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2012 2018-01-15 Nick Clifton <nickc@redhat.com>
2014 * po/uk.po: Updated Ukranian translation.
2016 2018-01-13 Nick Clifton <nickc@redhat.com>
2018 * po/opcodes.pot: Regenerated.
2020 2018-01-13 Nick Clifton <nickc@redhat.com>
2022 * configure: Regenerate.
2024 2018-01-13 Nick Clifton <nickc@redhat.com>
2026 2.30 branch created.
2028 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2030 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2031 * i386-tbl.h: Regenerate.
2033 2018-01-10 Jan Beulich <jbeulich@suse.com>
2035 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2036 * i386-tbl.h: Re-generate.
2038 2018-01-10 Jan Beulich <jbeulich@suse.com>
2040 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2041 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2042 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2043 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2044 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2045 Disp8MemShift of AVX512VL forms.
2046 * i386-tbl.h: Re-generate.
2048 2018-01-09 Jim Wilson <jimw@sifive.com>
2050 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2051 then the hi_addr value is zero.
2053 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2055 * arm-dis.c (arm_opcodes): Add csdb.
2056 (thumb32_opcodes): Add csdb.
2058 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2060 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2061 * aarch64-asm-2.c: Regenerate.
2062 * aarch64-dis-2.c: Regenerate.
2063 * aarch64-opc-2.c: Regenerate.
2065 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2068 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2069 Remove AVX512 vmovd with 64-bit operands.
2070 * i386-tbl.h: Regenerated.
2072 2018-01-05 Jim Wilson <jimw@sifive.com>
2074 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2077 2018-01-03 Alan Modra <amodra@gmail.com>
2079 Update year range in copyright notice of all files.
2081 2018-01-02 Jan Beulich <jbeulich@suse.com>
2083 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2084 and OPERAND_TYPE_REGZMM entries.
2086 For older changes see ChangeLog-2017
2088 Copyright (C) 2018 Free Software Foundation, Inc.
2090 Copying and distribution of this file, with or without modification,
2091 are permitted in any medium without royalty provided the copyright
2092 notice and this notice are preserved.
2098 version-control: never
projects / external / binutils.git / blob