1 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
3 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
4 8, 14 and 15 for Armv8.1-M Mainline.
6 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
7 Michael Collison <michael.collison@arm.com>
9 * arm-dis.c (enum mve_instructions): New enum.
10 (enum mve_unpredictable): Likewise.
11 (enum mve_undefined): Likewise.
12 (struct mopcode32): New struct.
13 (is_mve_okay_in_it): New function.
14 (is_mve_architecture): Likewise.
15 (arm_decode_field): Likewise.
16 (arm_decode_field_multiple): Likewise.
17 (is_mve_encoding_conflict): Likewise.
18 (is_mve_undefined): Likewise.
19 (is_mve_unpredictable): Likewise.
20 (print_mve_undefined): Likewise.
21 (print_mve_unpredictable): Likewise.
22 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
23 (print_insn_mve): New function.
24 (print_insn_thumb32): Handle MVE architecture.
25 (select_arm_features): Force thumb for Armv8.1-m Mainline.
27 2019-05-10 Nick Clifton <nickc@redhat.com>
30 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
31 end of the table prematurely.
33 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
35 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
38 2019-05-11 Alan Modra <amodra@gmail.com>
40 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
41 when -Mraw is in effect.
43 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
45 * aarch64-dis-2.c: Regenerate.
46 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
47 (OP_SVE_BBB): New variant set.
48 (OP_SVE_DDDD): New variant set.
49 (OP_SVE_HHH): New variant set.
50 (OP_SVE_HHHU): New variant set.
51 (OP_SVE_SSS): New variant set.
52 (OP_SVE_SSSU): New variant set.
53 (OP_SVE_SHH): New variant set.
54 (OP_SVE_SBBU): New variant set.
55 (OP_SVE_DSS): New variant set.
56 (OP_SVE_DHHU): New variant set.
57 (OP_SVE_VMV_HSD_BHS): New variant set.
58 (OP_SVE_VVU_HSD_BHS): New variant set.
59 (OP_SVE_VVVU_SD_BH): New variant set.
60 (OP_SVE_VVVU_BHSD): New variant set.
61 (OP_SVE_VVV_QHD_DBS): New variant set.
62 (OP_SVE_VVV_HSD_BHS): New variant set.
63 (OP_SVE_VVV_HSD_BHS2): New variant set.
64 (OP_SVE_VVV_BHS_HSD): New variant set.
65 (OP_SVE_VV_BHS_HSD): New variant set.
66 (OP_SVE_VVV_SD): New variant set.
67 (OP_SVE_VVU_BHS_HSD): New variant set.
68 (OP_SVE_VZVV_SD): New variant set.
69 (OP_SVE_VZVV_BH): New variant set.
70 (OP_SVE_VZV_SD): New variant set.
71 (aarch64_opcode_table): Add sve2 instructions.
73 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
75 * aarch64-asm-2.c: Regenerated.
76 * aarch64-dis-2.c: Regenerated.
77 * aarch64-opc-2.c: Regenerated.
78 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
79 for SVE_SHLIMM_UNPRED_22.
80 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
81 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
84 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
86 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
87 sve_size_tsz_bhs iclass encode.
88 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
89 sve_size_tsz_bhs iclass decode.
91 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
93 * aarch64-asm-2.c: Regenerated.
94 * aarch64-dis-2.c: Regenerated.
95 * aarch64-opc-2.c: Regenerated.
96 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
98 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
99 (fields): Handle SVE_i2h field.
100 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
101 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
103 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
105 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
106 sve_shift_tsz_bhsd iclass encode.
107 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
108 sve_shift_tsz_bhsd iclass decode.
110 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
112 * aarch64-asm-2.c: Regenerated.
113 * aarch64-dis-2.c: Regenerated.
114 * aarch64-opc-2.c: Regenerated.
115 * aarch64-asm.c (aarch64_ins_sve_shrimm):
116 (aarch64_encode_variant_using_iclass): Handle
117 sve_shift_tsz_hsd iclass encode.
118 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
119 sve_shift_tsz_hsd iclass decode.
120 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
121 for SVE_SHRIMM_UNPRED_22.
122 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
123 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
126 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
128 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
129 sve_size_013 iclass encode.
130 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
131 sve_size_013 iclass decode.
133 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
135 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
136 sve_size_bh iclass encode.
137 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
138 sve_size_bh iclass decode.
140 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
142 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
143 sve_size_sd2 iclass encode.
144 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
145 sve_size_sd2 iclass decode.
146 * aarch64-opc.c (fields): Handle SVE_sz2 field.
147 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
149 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
151 * aarch64-asm-2.c: Regenerated.
152 * aarch64-dis-2.c: Regenerated.
153 * aarch64-opc-2.c: Regenerated.
154 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
156 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
157 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
159 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
161 * aarch64-asm-2.c: Regenerated.
162 * aarch64-dis-2.c: Regenerated.
163 * aarch64-opc-2.c: Regenerated.
164 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
165 for SVE_Zm3_11_INDEX.
166 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
167 (fields): Handle SVE_i3l and SVE_i3h2 fields.
168 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
170 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
172 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
174 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
175 sve_size_hsd2 iclass encode.
176 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
177 sve_size_hsd2 iclass decode.
178 * aarch64-opc.c (fields): Handle SVE_size field.
179 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
181 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
183 * aarch64-asm-2.c: Regenerated.
184 * aarch64-dis-2.c: Regenerated.
185 * aarch64-opc-2.c: Regenerated.
186 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
188 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
189 (fields): Handle SVE_rot3 field.
190 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
191 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
193 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
195 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
198 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
201 (aarch64_feature_sve2, aarch64_feature_sve2aes,
202 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
203 aarch64_feature_sve2bitperm): New feature sets.
204 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
205 for feature set addresses.
206 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
207 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
209 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
210 Faraz Shahbazker <fshahbazker@wavecomp.com>
212 * mips-dis.c (mips_calculate_combination_ases): Add ISA
213 argument and set ASE_EVA_R6 appropriately.
214 (set_default_mips_dis_options): Pass ISA to above.
215 (parse_mips_dis_option): Likewise.
216 * mips-opc.c (EVAR6): New macro.
217 (mips_builtin_opcodes): Add llwpe, scwpe.
219 2019-05-01 Sudakshina Das <sudi.das@arm.com>
221 * aarch64-asm-2.c: Regenerated.
222 * aarch64-dis-2.c: Regenerated.
223 * aarch64-opc-2.c: Regenerated.
224 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
225 AARCH64_OPND_TME_UIMM16.
226 (aarch64_print_operand): Likewise.
227 * aarch64-tbl.h (QL_IMM_NIL): New.
230 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
232 2019-04-29 John Darrington <john@darrington.wattle.id.au>
234 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
236 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
237 Faraz Shahbazker <fshahbazker@wavecomp.com>
239 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
241 2019-04-24 John Darrington <john@darrington.wattle.id.au>
243 * s12z-opc.h: Add extern "C" bracketing to help
244 users who wish to use this interface in c++ code.
246 2019-04-24 John Darrington <john@darrington.wattle.id.au>
248 * s12z-opc.c (bm_decode): Handle bit map operations with the
251 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
253 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
254 specifier. Add entries for VLDR and VSTR of system registers.
255 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
256 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
257 of %J and %K format specifier.
259 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
261 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
262 Add new entries for VSCCLRM instruction.
263 (print_insn_coprocessor): Handle new %C format control code.
265 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
267 * arm-dis.c (enum isa): New enum.
268 (struct sopcode32): New structure.
269 (coprocessor_opcodes): change type of entries to struct sopcode32 and
270 set isa field of all current entries to ANY.
271 (print_insn_coprocessor): Change type of insn to struct sopcode32.
272 Only match an entry if its isa field allows the current mode.
274 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
276 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
278 (print_insn_thumb32): Add logic to print %n CLRM register list.
280 2019-04-15 Sudakshina Das <sudi.das@arm.com>
282 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
285 2019-04-15 Sudakshina Das <sudi.das@arm.com>
287 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
288 (print_insn_thumb32): Edit the switch case for %Z.
290 2019-04-15 Sudakshina Das <sudi.das@arm.com>
292 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
294 2019-04-15 Sudakshina Das <sudi.das@arm.com>
296 * arm-dis.c (thumb32_opcodes): New instruction bfl.
298 2019-04-15 Sudakshina Das <sudi.das@arm.com>
300 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
302 2019-04-15 Sudakshina Das <sudi.das@arm.com>
304 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
305 Arm register with r13 and r15 unpredictable.
306 (thumb32_opcodes): New instructions for bfx and bflx.
308 2019-04-15 Sudakshina Das <sudi.das@arm.com>
310 * arm-dis.c (thumb32_opcodes): New instructions for bf.
312 2019-04-15 Sudakshina Das <sudi.das@arm.com>
314 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
316 2019-04-15 Sudakshina Das <sudi.das@arm.com>
318 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
320 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
322 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
324 2019-04-12 John Darrington <john@darrington.wattle.id.au>
326 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
327 "optr". ("operator" is a reserved word in c++).
329 2019-04-11 Sudakshina Das <sudi.das@arm.com>
331 * aarch64-opc.c (aarch64_print_operand): Add case for
333 (verify_constraints): Likewise.
334 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
335 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
336 to accept Rt|SP as first operand.
337 (AARCH64_OPERANDS): Add new Rt_SP.
338 * aarch64-asm-2.c: Regenerated.
339 * aarch64-dis-2.c: Regenerated.
340 * aarch64-opc-2.c: Regenerated.
342 2019-04-11 Sudakshina Das <sudi.das@arm.com>
344 * aarch64-asm-2.c: Regenerated.
345 * aarch64-dis-2.c: Likewise.
346 * aarch64-opc-2.c: Likewise.
347 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
349 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
351 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
353 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
355 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
356 * i386-init.h: Regenerated.
358 2019-04-07 Alan Modra <amodra@gmail.com>
360 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
361 op_separator to control printing of spaces, comma and parens
362 rather than need_comma, need_paren and spaces vars.
364 2019-04-07 Alan Modra <amodra@gmail.com>
367 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
368 (print_insn_neon, print_insn_arm): Likewise.
370 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
372 * i386-dis-evex.h (evex_table): Updated to support BF16
374 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
375 and EVEX_W_0F3872_P_3.
376 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
377 (cpu_flags): Add bitfield for CpuAVX512_BF16.
378 * i386-opc.h (enum): Add CpuAVX512_BF16.
379 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
380 * i386-opc.tbl: Add AVX512 BF16 instructions.
381 * i386-init.h: Regenerated.
382 * i386-tbl.h: Likewise.
384 2019-04-05 Alan Modra <amodra@gmail.com>
386 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
387 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
388 to favour printing of "-" branch hint when using the "y" bit.
389 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
391 2019-04-05 Alan Modra <amodra@gmail.com>
393 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
394 opcode until first operand is output.
396 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
399 * ppc-opc.c (valid_bo_pre_v2): Add comments.
400 (valid_bo_post_v2): Add support for 'at' branch hints.
401 (insert_bo): Only error on branch on ctr.
402 (get_bo_hint_mask): New function.
403 (insert_boe): Add new 'branch_taken' formal argument. Add support
404 for inserting 'at' branch hints.
405 (extract_boe): Add new 'branch_taken' formal argument. Add support
406 for extracting 'at' branch hints.
407 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
408 (BOE): Delete operand.
409 (BOM, BOP): New operands.
411 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
412 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
413 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
414 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
415 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
416 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
417 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
418 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
419 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
420 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
421 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
422 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
423 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
424 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
425 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
426 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
427 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
428 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
429 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
430 bttarl+>: New extended mnemonics.
432 2019-03-28 Alan Modra <amodra@gmail.com>
435 * ppc-opc.c (BTF): Define.
436 (powerpc_opcodes): Use for mtfsb*.
437 * ppc-dis.c (print_insn_powerpc): Print fields with both
438 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
440 2019-03-25 Tamar Christina <tamar.christina@arm.com>
442 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
443 (mapping_symbol_for_insn): Implement new algorithm.
444 (print_insn): Remove duplicate code.
446 2019-03-25 Tamar Christina <tamar.christina@arm.com>
448 * aarch64-dis.c (print_insn_aarch64):
451 2019-03-25 Tamar Christina <tamar.christina@arm.com>
453 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
456 2019-03-25 Tamar Christina <tamar.christina@arm.com>
458 * aarch64-dis.c (last_stop_offset): New.
459 (print_insn_aarch64): Use stop_offset.
461 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
464 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
466 * i386-init.h: Regenerated.
468 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
471 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
472 vmovdqu16, vmovdqu32 and vmovdqu64.
473 * i386-tbl.h: Regenerated.
475 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
477 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
478 from vstrszb, vstrszh, and vstrszf.
480 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
482 * s390-opc.txt: Add instruction descriptions.
484 2019-02-08 Jim Wilson <jimw@sifive.com>
486 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
489 2019-02-07 Tamar Christina <tamar.christina@arm.com>
491 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
493 2019-02-07 Tamar Christina <tamar.christina@arm.com>
496 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
497 * aarch64-opc.c (verify_elem_sd): New.
498 (fields): Add FLD_sz entr.
499 * aarch64-tbl.h (_SIMD_INSN): New.
500 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
501 fmulx scalar and vector by element isns.
503 2019-02-07 Nick Clifton <nickc@redhat.com>
505 * po/sv.po: Updated Swedish translation.
507 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
509 * s390-mkopc.c (main): Accept arch13 as cpu string.
510 * s390-opc.c: Add new instruction formats and instruction opcode
512 * s390-opc.txt: Add new arch13 instructions.
514 2019-01-25 Sudakshina Das <sudi.das@arm.com>
516 * aarch64-tbl.h (QL_LDST_AT): Update macro.
517 (aarch64_opcode): Change encoding for stg, stzg
519 * aarch64-asm-2.c: Regenerated.
520 * aarch64-dis-2.c: Regenerated.
521 * aarch64-opc-2.c: Regenerated.
523 2019-01-25 Sudakshina Das <sudi.das@arm.com>
525 * aarch64-asm-2.c: Regenerated.
526 * aarch64-dis-2.c: Likewise.
527 * aarch64-opc-2.c: Likewise.
528 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
530 2019-01-25 Sudakshina Das <sudi.das@arm.com>
531 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
533 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
534 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
535 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
536 * aarch64-dis.h (ext_addr_simple_2): Likewise.
537 * aarch64-opc.c (operand_general_constraint_met_p): Remove
538 case for ldstgv_indexed.
539 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
540 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
541 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
542 * aarch64-asm-2.c: Regenerated.
543 * aarch64-dis-2.c: Regenerated.
544 * aarch64-opc-2.c: Regenerated.
546 2019-01-23 Nick Clifton <nickc@redhat.com>
548 * po/pt_BR.po: Updated Brazilian Portuguese translation.
550 2019-01-21 Nick Clifton <nickc@redhat.com>
552 * po/de.po: Updated German translation.
553 * po/uk.po: Updated Ukranian translation.
555 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
556 * mips-dis.c (mips_arch_choices): Fix typo in
557 gs464, gs464e and gs264e descriptors.
559 2019-01-19 Nick Clifton <nickc@redhat.com>
561 * configure: Regenerate.
562 * po/opcodes.pot: Regenerate.
564 2018-06-24 Nick Clifton <nickc@redhat.com>
568 2019-01-09 John Darrington <john@darrington.wattle.id.au>
570 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
572 -dis.c (opr_emit_disassembly): Do not omit an index if it is
575 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
577 * configure: Regenerate.
579 2019-01-07 Alan Modra <amodra@gmail.com>
581 * configure: Regenerate.
582 * po/POTFILES.in: Regenerate.
584 2019-01-03 John Darrington <john@darrington.wattle.id.au>
586 * s12z-opc.c: New file.
587 * s12z-opc.h: New file.
588 * s12z-dis.c: Removed all code not directly related to display
589 of instructions. Used the interface provided by the new files
591 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
592 * Makefile.in: Regenerate.
593 * configure.ac (bfd_s12z_arch): Correct the dependencies.
594 * configure: Regenerate.
596 2019-01-01 Alan Modra <amodra@gmail.com>
598 Update year range in copyright notice of all files.
600 For older changes see ChangeLog-2018
602 Copyright (C) 2019 Free Software Foundation, Inc.
604 Copying and distribution of this file, with or without modification,
605 are permitted in any medium without royalty provided the copyright
606 notice and this notice are preserved.
612 version-control: never