1 2013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
3 * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
6 2013-08-05 Eric Botcazou <ebotcazou@adacore.com>
7 Konrad Eisele <konrad@gaisler.com>
9 * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
11 * sparc-opc.c (MASK_LEON): Define.
12 (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
13 (letandleon): New macro.
14 (v9andleon): Likewise.
15 (sparc_opc): Add leon.
16 (umac): Enable for letandleon.
18 (casa): Enable for v9andleon.
22 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
23 Richard Sandiford <rdsandiford@googlemail.com>
25 * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
26 OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
27 (print_vu0_channel): New function.
28 (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
29 (print_insn_args): Handle '#'.
30 (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
31 * mips-opc.c (mips_vu0_channel_mask): New constant.
32 (decode_mips_operand): Handle new VU0 operand types.
33 (VU0, VU0CH): New macros.
34 (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
35 for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
36 Use "+6" rather than "G" for QMFC2 and QMTC2.
38 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
40 * mips-formats.h (PCREL): Reorder parameters and update the definition
41 to match new mips_pcrel_operand layout.
42 (JUMP, JALX, BRANCH): Update accordingly.
43 * mips16-opc.c (decode_mips16_operand): Likewise.
45 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
47 * micromips-opc.c (WR_s): Delete.
49 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
51 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
53 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
54 (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
55 (mips_builtin_opcodes): Use the new position-based read-write flags
56 instead of field-based ones. Use UDI for "udi..." instructions.
57 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
59 (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
60 (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
61 (WR_SP, RD_16): New macros.
62 (RD_SP): Redefine as an INSN2_* flag.
63 (MOD_SP): Redefine in terms of RD_SP and WR_SP.
64 (mips16_opcodes): Use the new position-based read-write flags
65 instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
67 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
69 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
70 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
71 (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
72 (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
73 (micromips_opcodes): Use the new position-based read-write flags
74 instead of field-based ones.
75 * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
76 (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
79 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
81 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
82 (WR_SP): Replace with...
84 (mips16_opcodes): Update accordingly.
85 * mips-dis.c (print_insn_mips16): Likewise.
87 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
89 * mips16-opc.c (mips16_opcodes): Reformat.
91 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
93 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
94 for operands that are hard-coded to $0.
95 * micromips-opc.c (micromips_opcodes): Likewise.
97 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
99 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
100 for the single-operand forms of JALR and JALR.HB.
101 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
104 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
106 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
107 instructions. Fix them to use WR_MACC instead of WR_CC and
108 add missing RD_MACCs.
110 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
112 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
114 2013-07-29 Peter Bergner <bergner@vnet.ibm.com>
116 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
118 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
119 Alexander Ivchenko <alexander.ivchenko@intel.com>
120 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
121 Sergey Lega <sergey.s.lega@intel.com>
122 Anna Tikhonova <anna.tikhonova@intel.com>
123 Ilya Tocar <ilya.tocar@intel.com>
124 Andrey Turetskiy <andrey.turetskiy@intel.com>
125 Ilya Verbin <ilya.verbin@intel.com>
126 Kirill Yukhin <kirill.yukhin@intel.com>
127 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
129 * i386-dis-evex.h: New.
130 * i386-dis.c (OP_Rounding): New.
137 (EXEvexHalfBcstXmmq): New.
140 (EXEvexXNoBcst): New.
149 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
150 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
151 evex_rounding_mode, evex_sae_mode, mask_mode.
152 (USE_EVEX_TABLE): New.
155 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
157 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
158 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
159 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
160 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
161 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
162 MOD_EVEX_0F38C7_REG_6.
163 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
164 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
165 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
166 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
167 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
168 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
169 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
170 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
171 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
172 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
173 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
174 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
175 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
176 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
177 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
178 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
179 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
180 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
181 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
182 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
183 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
184 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
185 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
186 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
187 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
188 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
189 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
190 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
191 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
192 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
193 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
194 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
195 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
196 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
197 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
198 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
199 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
200 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
201 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
202 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
203 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
204 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
205 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
206 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
207 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
208 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
209 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
210 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
211 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
212 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
213 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
214 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
215 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
216 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
217 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
218 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
219 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
220 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
221 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
222 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
223 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
224 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
225 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
226 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
227 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
228 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
229 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
230 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
231 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
232 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
233 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
234 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
235 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
236 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
237 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
238 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
240 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
241 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
242 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
243 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
244 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
245 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
246 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
247 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
248 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
249 VEX_W_0F3A32_P_2_LEN_0.
250 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
251 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
252 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
253 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
254 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
255 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
256 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
257 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
258 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
259 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
260 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
261 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
262 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
263 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
264 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
265 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
266 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
267 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
268 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
269 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
270 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
271 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
272 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
273 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
274 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
275 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
276 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
277 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
278 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
279 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
280 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
281 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
282 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
283 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
284 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
285 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
286 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
287 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
288 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
289 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
290 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
291 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
292 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
293 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
294 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
295 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
296 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
297 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
298 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
299 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
300 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
301 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
302 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
303 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
304 (struct vex): Add fields evex, r, v, mask_register_specifier,
306 (intel_names_xmm): Add upper 16 registers.
307 (att_names_xmm): Ditto.
308 (intel_names_ymm): Ditto.
309 (att_names_ymm): Ditto.
311 (intel_names_zmm): Ditto.
312 (att_names_zmm): Ditto.
314 (intel_names_mask): Ditto.
315 (att_names_mask): Ditto.
316 (names_rounding): Ditto.
317 (names_broadcast): Ditto.
318 (x86_64_table): Add escape to evex-table.
319 (reg_table): Include reg_table evex-entries from
320 i386-dis-evex.h. Fix prefetchwt1 instruction.
321 (prefix_table): Add entries for new instructions.
323 (vex_len_table): Ditto.
324 (vex_w_table): Ditto.
326 (get_valid_dis386): Properly handle new instructions.
327 (print_insn): Handle zmm and mask registers, print mask operand.
328 (intel_operand_size): Support EVEX, new modes and sizes.
329 (OP_E_register): Handle new modes.
330 (OP_E_memory): Ditto.
335 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
336 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
337 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
338 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
339 CpuAVX512PF and CpuVREX.
340 (operand_type_init): Add OPERAND_TYPE_REGZMM,
341 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
342 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
343 StaticRounding, SAE, Disp8MemShift, NoDefMask.
344 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
345 * i386-init.h: Regenerate.
346 * i386-opc.h (CpuAVX512F): New.
351 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
352 cpuavx512pf and cpuvrex fields.
353 (VecSIB): Add VecSIB512.
358 (StaticRounding): New.
360 (Disp8MemShift): New.
362 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
363 staticrounding, sae, disp8memshift and nodefmask.
367 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
370 * i386-opc.tbl: Add AVX512 instructions.
371 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
372 registers, mask registers.
373 * i386-tbl.h: Regenerate.
375 2013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
378 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
379 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
381 2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
383 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
384 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
386 (prefix_table): Updated.
387 (three_byte_table): Likewise.
388 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
389 (cpu_flags): Add CpuSHA.
390 (i386_cpu_flags): Add cpusha.
391 * i386-init.h: Regenerate.
392 * i386-opc.h (CpuSHA): New.
393 (CpuUnused): Restored.
394 (i386_cpu_flags): Add cpusha.
395 * i386-opc.tbl: Add SHA instructions.
396 * i386-tbl.h: Regenerate.
398 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
399 Kirill Yukhin <kirill.yukhin@intel.com>
400 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
402 * i386-dis.c (BND_Fixup): New.
409 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
411 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
412 (dis tables): Replace XX with BND for near branch and call
414 (prefix_table): Add new entries.
415 (mod_table): Likewise.
417 (intel_names_bnd): New.
418 (att_names_bnd): New.
420 (prefix_name): Handle BND_PREFIX.
421 (print_insn): Initialize names_bnd.
422 (intel_operand_size): Handle new modes.
423 (OP_E_register): Likewise.
424 (OP_E_memory): Likewise.
426 * i386-gen.c (cpu_flag_init): Add CpuMPX.
427 (cpu_flags): Add CpuMPX.
428 (operand_type_init): Add RegBND.
429 (opcode_modifiers): Add BNDPrefixOk.
430 (operand_types): Add RegBND.
431 * i386-init.h: Regenerate.
432 * i386-opc.h (CpuMPX): New.
433 (CpuUnused): Comment out.
434 (i386_cpu_flags): Add cpumpx.
436 (i386_opcode_modifier): Add bndprefixok.
438 (i386_operand_type): Add regbnd.
439 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
440 Add MPX instructions and bnd prefix.
441 * i386-reg.tbl: Add bnd0-bnd3 registers.
442 * i386-tbl.h: Regenerate.
444 2013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
446 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
449 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
451 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
453 * Makefile.in: Regenerate.
454 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
455 all fields. Reformat.
457 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
459 * mips16-opc.c: Include mips-formats.h.
460 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
462 (decode_mips16_operand): New function.
463 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
464 (print_insn_arg): Handle OP_ENTRY_EXIT list.
465 Abort for OP_SAVE_RESTORE_LIST.
466 (print_mips16_insn_arg): Change interface. Use mips_operand
467 structures. Delete GET_OP_S. Move GET_OP definition to...
468 (print_insn_mips16): ...here. Call init_print_arg_state.
469 Update the call to print_mips16_insn_arg.
471 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
473 * mips-formats.h: New file.
474 * mips-opc.c: Include mips-formats.h.
475 (reg_0_map): New static array.
476 (decode_mips_operand): New function.
477 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
478 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
479 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
480 (int_c_map): New static arrays.
481 (decode_micromips_operand): New function.
482 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
483 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
484 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
485 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
486 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
487 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
488 (micromips_imm_b_map, micromips_imm_c_map): Delete.
489 (print_reg): New function.
490 (mips_print_arg_state): New structure.
491 (init_print_arg_state, print_insn_arg): New functions.
492 (print_insn_args): Change interface and use mips_operand structures.
493 Delete GET_OP_S. Move GET_OP definition to...
494 (print_insn_mips): ...here. Update the call to print_insn_args.
495 (print_insn_micromips): Use print_insn_args.
497 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
499 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
502 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
504 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
505 ADDA.S, MULA.S and SUBA.S.
507 2013-07-08 H.J. Lu <hongjiu.lu@intel.com>
510 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
511 * i386-tbl.h: Regenerated.
513 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
515 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
516 and SD A(B) macros up.
517 * micromips-opc.c (micromips_opcodes): Likewise.
519 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
521 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
524 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
526 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
527 MDMX-like instructions.
528 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
529 printing "Q" operands for INSN_5400 instructions.
531 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
533 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
535 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
538 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
540 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
542 * mips16-opc.c (mips16_opcodes): Likewise.
543 * micromips-opc.c (micromips_opcodes): Likewise.
544 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
545 (print_insn_mips16): Handle "+i".
546 (print_insn_micromips): Likewise. Conditionally preserve the
547 ISA bit for "a" but not for "+i".
549 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
551 * micromips-opc.c (WR_mhi): Rename to..
553 (micromips_opcodes): Update "movep" entry accordingly. Replace
555 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
556 (micromips_to_32_reg_h_map1): ...this.
557 (micromips_to_32_reg_i_map): Rename to...
558 (micromips_to_32_reg_h_map2): ...this.
559 (print_micromips_insn): Remove "mi" case. Print both registers
560 in the pair for "mh".
562 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
564 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
565 * micromips-opc.c (micromips_opcodes): Likewise.
566 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
567 and "+T" handling. Check for a "0" suffix when deciding whether to
568 use coprocessor 0 names. In that case, also check for ",H" selectors.
570 2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
572 * s390-opc.c (J12_12, J24_24): New macros.
573 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
574 (MASK_MII_UPI): Rename to MASK_MII_UPP.
575 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
577 2013-07-04 Alan Modra <amodra@gmail.com>
579 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
581 2013-06-26 Nick Clifton <nickc@redhat.com>
583 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
584 field when checking for type 2 nop.
585 * rx-decode.c: Regenerate.
587 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
589 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
592 2013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
594 * mips-dis.c (is_mips16_plt_tail): New function.
595 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
597 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
599 2013-06-21 DJ Delorie <dj@redhat.com>
601 * msp430-decode.opc: New.
602 * msp430-decode.c: New/generated.
603 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
604 (MAINTAINER_CLEANFILES): Likewise.
605 Add rule to build msp430-decode.c frommsp430decode.opc
606 using the opc2c program.
607 * Makefile.in: Regenerate.
608 * configure.in: Add msp430-decode.lo to msp430 architecture files.
609 * configure: Regenerate.
611 2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
613 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
614 (SYMTAB_AVAILABLE): Removed.
615 (#include "elf/aarch64.h): Ditto.
617 2013-06-17 Catherine Moore <clm@codesourcery.com>
618 Maciej W. Rozycki <macro@codesourcery.com>
619 Chao-Ying Fu <fu@mips.com>
621 * micromips-opc.c (EVA): Define.
623 (micromips_opcodes): Add EVA opcodes.
624 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
625 (print_insn_args): Handle EVA offsets.
626 (print_insn_micromips): Likewise.
627 * mips-opc.c (EVA): Define.
629 (mips_builtin_opcodes): Add EVA opcodes.
631 2013-06-17 Alan Modra <amodra@gmail.com>
633 * Makefile.am (mips-opc.lo): Add rules to create automatic
634 dependency files. Pass archdefs.
635 (micromips-opc.lo, mips16-opc.lo): Likewise.
636 * Makefile.in: Regenerate.
638 2013-06-14 DJ Delorie <dj@redhat.com>
640 * rx-decode.opc (rx_decode_opcode): Bit operations on
641 registers are 32-bit operations, not 8-bit operations.
642 * rx-decode.c: Regenerate.
644 2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
646 * micromips-opc.c (IVIRT): New define.
647 (IVIRT64): New define.
648 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
649 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
651 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
652 dmtgc0 to print cp0 names.
654 2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
656 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
659 2013-06-08 Catherine Moore <clm@codesourcery.com>
660 Richard Sandiford <rdsandiford@googlemail.com>
662 * micromips-opc.c (D32, D33, MC): Update definitions.
663 (micromips_opcodes): Initialize ase field.
664 * mips-dis.c (mips_arch_choice): Add ase field.
665 (mips_arch_choices): Initialize ase field.
666 (set_default_mips_dis_options): Declare and setup mips_ase.
667 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
668 MT32, MC): Update definitions.
669 (mips_builtin_opcodes): Initialize ase field.
671 2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
673 * s390-opc.txt (flogr): Require a register pair destination.
675 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
677 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
680 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
682 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
684 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
686 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
687 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
688 XLS_MASK, PPCVSX2): New defines.
689 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
690 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
691 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
692 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
693 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
694 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
695 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
696 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
697 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
698 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
699 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
700 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
701 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
702 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
703 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
704 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
705 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
706 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
707 <lxvx, stxvx>: New extended mnemonics.
709 2013-05-17 Alan Modra <amodra@gmail.com>
711 * ia64-raw.tbl: Replace non-ASCII char.
712 * ia64-waw.tbl: Likewise.
713 * ia64-asmtab.c: Regenerate.
715 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
717 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
718 * i386-init.h: Regenerated.
720 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
722 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
723 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
724 check from [0, 255] to [-128, 255].
726 2013-05-09 Andrew Pinski <apinski@cavium.com>
728 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
729 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
730 (parse_mips_dis_option): Handle the virt option.
731 (print_insn_args): Handle "+J".
732 (print_mips_disassembler_options): Print out message about virt64.
733 * mips-opc.c (IVIRT): New define.
734 (IVIRT64): New define.
735 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
736 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
737 Move rfe to the bottom as it conflicts with tlbgp.
739 2013-05-09 Alan Modra <amodra@gmail.com>
741 * ppc-opc.c (extract_vlesi): Properly sign extend.
742 (extract_vlensi): Likewise. Comment reason for setting invalid.
744 2013-05-02 Nick Clifton <nickc@redhat.com>
746 * msp430-dis.c: Add support for MSP430X instructions.
748 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
750 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
753 2013-04-17 Wei-chen Wang <cole945@gmail.com>
756 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
758 (hash_insns_list): Likewise.
760 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
762 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
765 2013-04-08 Jan Beulich <jbeulich@suse.com>
767 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
768 * i386-tbl.h: Re-generate.
770 2013-04-06 David S. Miller <davem@davemloft.net>
772 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
773 of an opcode, prefer the one with F_PREFERRED set.
774 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
775 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
776 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
777 mark existing mnenomics as aliases. Add "cc" suffix to edge
778 instructions generating condition codes, mark existing mnenomics
779 as aliases. Add "fp" prefix to VIS compare instructions, mark
780 existing mnenomics as aliases.
782 2013-04-03 Nick Clifton <nickc@redhat.com>
784 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
785 destination address by subtracting the operand from the current
787 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
788 a positive value in the insn.
789 (extract_u16_loop): Do not negate the returned value.
790 (D16_LOOP): Add V850_INVERSE_PCREL flag.
792 (ceilf.sw): Remove duplicate entry.
793 (cvtf.hs): New entry.
799 (maddf.s): Restrict to E3V5 architectures.
801 (nmaddf.s): Likewise.
802 (nmsubf.s): Likewise.
804 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
806 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
808 (print_insn): Pass sizeflag to get_sib.
810 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
813 * tic6x-dis.c: Add support for displaying 16-bit insns.
815 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
818 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
819 individual msb and lsb halves in src1 & src2 fields. Discard the
820 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
821 follow what Ti SDK does in that case as any value in the src1
822 field yields the same output with SDK disassembler.
824 2013-03-12 Michael Eager <eager@eagercon.com>
826 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
828 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
830 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
832 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
834 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
836 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
838 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
840 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
842 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
843 (thumb32_opcodes): Likewise.
844 (print_insn_thumb32): Handle 'S' control char.
846 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
848 * lm32-desc.c: Regenerate.
850 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
852 * i386-reg.tbl (riz): Add RegRex64.
853 * i386-tbl.h: Regenerated.
855 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
857 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
858 (aarch64_feature_crc): New static.
860 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
861 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
862 * aarch64-asm-2.c: Re-generate.
863 * aarch64-dis-2.c: Ditto.
864 * aarch64-opc-2.c: Ditto.
866 2013-02-27 Alan Modra <amodra@gmail.com>
868 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
869 * rl78-decode.c: Regenerate.
871 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
873 * rl78-decode.opc: Fix encoding of DIVWU insn.
874 * rl78-decode.c: Regenerate.
876 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
879 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
881 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
882 (cpu_flags): Add CpuSMAP.
884 * i386-opc.h (CpuSMAP): New.
885 (i386_cpu_flags): Add cpusmap.
887 * i386-opc.tbl: Add clac and stac.
889 * i386-init.h: Regenerated.
890 * i386-tbl.h: Likewise.
892 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
894 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
895 which also makes the disassembler output be in little
896 endian like it should be.
898 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
900 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
902 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
904 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
906 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
907 section disassembled.
909 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
911 * arm-dis.c: Update strht pattern.
913 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
915 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
916 single-float. Disable ll, lld, sc and scd for EE. Disable the
917 trunc.w.s macro for EE.
919 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
920 Andrew Jenner <andrew@codesourcery.com>
922 Based on patches from Altera Corporation.
924 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
926 * Makefile.in: Regenerated.
927 * configure.in: Add case for bfd_nios2_arch.
928 * configure: Regenerated.
929 * disassemble.c (ARCH_nios2): Define.
930 (disassembler): Add case for bfd_arch_nios2.
931 * nios2-dis.c: New file.
932 * nios2-opc.c: New file.
934 2013-02-04 Alan Modra <amodra@gmail.com>
936 * po/POTFILES.in: Regenerate.
937 * rl78-decode.c: Regenerate.
938 * rx-decode.c: Regenerate.
940 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
942 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
943 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
944 * aarch64-asm.c (convert_xtl_to_shll): New function.
945 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
946 calling convert_xtl_to_shll.
947 * aarch64-dis.c (convert_shll_to_xtl): New function.
948 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
949 calling convert_shll_to_xtl.
950 * aarch64-gen.c: Update copyright year.
951 * aarch64-asm-2.c: Re-generate.
952 * aarch64-dis-2.c: Re-generate.
953 * aarch64-opc-2.c: Re-generate.
955 2013-01-24 Nick Clifton <nickc@redhat.com>
957 * v850-dis.c: Add support for e3v5 architecture.
958 * v850-opc.c: Likewise.
960 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
962 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
963 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
964 * aarch64-opc.c (operand_general_constraint_met_p): For
965 AARCH64_MOD_LSL, move the range check on the shift amount before the
966 alignment check; change to call set_sft_amount_out_of_range_error
967 instead of set_imm_out_of_range_error.
968 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
969 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
970 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
973 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
975 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
977 * i386-init.h: Regenerated.
978 * i386-tbl.h: Likewise.
980 2013-01-15 Nick Clifton <nickc@redhat.com>
982 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
984 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
986 2013-01-14 Will Newton <will.newton@imgtec.com>
988 * metag-dis.c (REG_WIDTH): Increase to 64.
990 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
992 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
993 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
994 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
996 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
997 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
998 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
999 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1001 2013-01-10 Will Newton <will.newton@imgtec.com>
1003 * Makefile.am: Add Meta.
1004 * configure.in: Add Meta.
1005 * disassemble.c: Add Meta support.
1006 * metag-dis.c: New file.
1007 * Makefile.in: Regenerate.
1008 * configure: Regenerate.
1010 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1012 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1013 (match_opcode): Rename to cr16_match_opcode.
1015 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1017 * mips-dis.c: Add names for CP0 registers of r5900.
1018 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1019 instructions sq and lq.
1020 Add support for MIPS r5900 CPU.
1021 Add support for 128 bit MMI (Multimedia Instructions).
1022 Add support for EE instructions (Emotion Engine).
1023 Disable unsupported floating point instructions (64 bit and
1024 undefined compare operations).
1025 Enable instructions of MIPS ISA IV which are supported by r5900.
1026 Disable 64 bit co processor instructions.
1027 Disable 64 bit multiplication and division instructions.
1028 Disable instructions for co-processor 2 and 3, because these are
1029 not supported (preparation for later VU0 support (Vector Unit)).
1030 Disable cvt.w.s because this behaves like trunc.w.s and the
1031 correct execution can't be ensured on r5900.
1032 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1033 will confuse less developers and compilers.
1035 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1037 * aarch64-opc.c (aarch64_print_operand): Change to print
1038 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1040 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1041 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1044 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1046 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1047 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1049 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1051 * i386-gen.c (process_copyright): Update copyright year to 2013.
1053 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1055 * cr16-dis.c (match_opcode,make_instruction): Remove static
1057 (dwordU,wordU): Moved typedefs to opcode/cr16.h
1058 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1060 For older changes see ChangeLog-2012
1062 Copyright (C) 2013 Free Software Foundation, Inc.
1064 Copying and distribution of this file, with or without modification,
1065 are permitted in any medium without royalty provided the copyright
1066 notice and this notice are preserved.
1072 version-control: never