1 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
3 * ppc-opc.c (CELL): New define.
4 (powerpc_opcodes): Enable hrfid for Cell. Add ldbrx and stdbrx,
5 cell specific instructions. Add {st,l}x{r,l}{,l} cell specific
7 * ppc-dis.c (powerpc_dialect): Handle cell.
9 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
11 * i386-dis.c (dis386): Add support for the change in POPCNT opcode in
12 amdfam10 architecture.
14 (print_insn): Disallow REP prefix for POPCNT.
16 2006-10-20 Andrew Stubbs <andrew.stubbs@st.com>
18 * sh-dis.c (print_insn_sh): Remove 0x from output to prevent GDB
21 2006-10-18 Dave Brolley <brolley@redhat.com>
23 * configure.in (BFD_MACHINES): Add cgen-bitset.lo for bfd_sh_arch.
24 * configure: Regenerated.
26 2006-09-29 Alan Modra <amodra@bigpond.net.au>
28 * po/POTFILES.in: Regenerate.
30 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
31 Joseph Myers <joseph@codesourcery.com>
32 Ian Lance Taylor <ian@wasabisystems.com>
33 Ben Elliston <bje@wasabisystems.com>
35 * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
36 only be used with the default multiply-add operation, so if N is
37 set, don't bother printing X. Add new iwmmxt instructions.
38 (IWMMXT_INSN_COUNT): Update.
39 (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
41 (print_insn_coprocessor): Check for iWMMXt2. Handle format
44 2006-09-24 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
47 * i386-dis.c (prefix_user_table): Fix the second operand of
48 maskmovdqu instruction to allow only %xmm register instead of
49 both %xmm register and memory.
51 2006-09-23 H.J. Lu <hongjiu.lu@intel.com>
54 * i386-dis.c (OP_OFF64): Get 32bit offset if there is an
57 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
59 * score-dis.c: New file.
60 * score-opc.h: New file.
61 * Makefile.am: Add Score files.
62 * Makefile.in: Regenerate.
63 * configure.in: Add support for Score target.
64 * configure: Regenerate.
65 * disassemble.c: Add support for Score target.
67 2006-09-16 Nick Clifton <nickc@redhat.com>
68 Pedro Alves <pedro_alves@portugalmail.pt>
70 * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ
71 macros defined in bfd.h.
72 * cris-dis.c: Likewise.
73 * h8300-dis.c: Likewise.
74 * i386-dis.c: Likewise.
75 * ia64-gen.c: Likewise.
78 2006-09-04 Paul Brook <paul@codesourcery.com>
80 * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
82 2006-08-23 H.J. Lu <hongjiu.lu@intel.com>
84 * i386-dis.c (three_byte_table): Expand to 256 elements.
86 2006-08-04 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
89 * i386-dis.c (MXC,EMC): Define.
90 (OP_MXC): New function to handle cvt* (convert instructions) between
91 %xmm and %mm register correctly.
93 (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
94 instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
97 2006-07-29 Richard Sandiford <richard@codesourcery.com>
99 * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
102 2006-07-19 Paul Brook <paul@codesourcery.com>
104 * armd-dis.c (arm_opcodes): Fix rbit opcode.
106 2006-07-18 H.J. Lu <hongjiu.lu@intel.com>
108 * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
109 "sldt", "str" and "smsw".
111 2006-07-15 H.J. Lu <hongjiu.lu@intel.com>
114 * i386-dis.c (GRP11_C6): NEW.
115 (GRP11_C7): Likewise.
122 (GRPPADLCK1): Likewise.
123 (GRPPADLCK2): Likewise.
124 (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
126 (grps): Add entries for GRP11_C6 and GRP11_C7.
128 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
129 Michael Meissner <michael.meissner@amd.com>
131 * i386-dis.c (dis386): Add support for 4 operand instructions. Add
132 support for amdfam10 SSE4a/ABM instructions. Modify all
133 initializer macros to have additional arguments. Disallow REP
134 prefix for non-string instructions.
137 2006-07-05 Julian Brown <julian@codesourcery.com>
139 * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
141 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
143 * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
144 (twobyte_has_modrm): Set 1 for 0x1f.
146 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
148 * i386-dis.c (NOP_Fixup): Removed.
150 (NOP_Fixup2): Likewise.
151 (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
153 2006-06-12 Julian Brown <julian@codesourcery.com>
155 * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
158 2006-06-10 H.J. Lu <hongjiu.lu@intel.com>
160 * i386.c (GRP10): Renamed to ...
162 (GRP11): Renamed to ...
164 (GRP12): Renamed to ...
166 (GRP13): Renamed to ...
168 (GRP14): Renamed to ...
170 (dis386_twobyte): Updated.
173 2006-06-09 Nick Clifton <nickc@redhat.com>
175 * po/fi.po: Updated Finnish translation.
177 2006-06-07 Joseph S. Myers <joseph@codesourcery.com>
179 * po/Make-in (pdf, ps): New dummy targets.
181 2006-06-06 Paul Brook <paul@codesourcery.com>
183 * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
185 (neon_opcodes): Add conditional execution specifiers.
186 (thumb_opcodes): Ditto.
187 (thumb32_opcodes): Ditto.
188 (arm_conditional): Change 0xe to "al" and add "" to end.
189 (ifthen_state, ifthen_next_state, ifthen_address): New.
190 (IFTHEN_COND): Define.
191 (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
192 (print_insn_arm): Change %c to use new values of arm_conditional.
193 (print_insn_thumb16): Print thumb conditions. Add %I.
194 (print_insn_thumb32): Print thumb conditions.
195 (find_ifthen_state): New function.
196 (print_insn): Track IT block state.
198 2006-06-06 Ben Elliston <bje@au.ibm.com>
199 Anton Blanchard <anton@samba.org>
200 Peter Bergner <bergner@vnet.ibm.com>
202 * ppc-dis.c (powerpc_dialect): Handle power6 option.
203 (print_ppc_disassembler_options): Mention power6.
205 2006-06-06 Thiemo Seufer <ths@mips.com>
206 Chao-ying Fu <fu@mips.com>
208 * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
209 * mips-opc.c: Add DSP64 instructions.
211 2006-06-06 Alan Modra <amodra@bigpond.net.au>
213 * m68hc11-dis.c (print_insn): Warning fix.
215 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
217 * po/Make-in (top_builddir): Define.
219 2006-06-05 Alan Modra <amodra@bigpond.net.au>
221 * Makefile.am: Run "make dep-am".
222 * Makefile.in: Regenerate.
223 * config.in: Regenerate.
225 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
227 * Makefile.am (INCLUDES): Use @INCINTL@.
228 * acinclude.m4: Include new gettext macros.
229 * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
230 Remove local code for po/Makefile.
231 * Makefile.in, aclocal.m4, configure: Regenerated.
233 2006-05-30 Nick Clifton <nickc@redhat.com>
235 * po/es.po: Updated Spanish translation.
237 2006-05-25 Richard Sandiford <richard@codesourcery.com>
239 * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
240 and fmovem entries. Put register list entries before immediate
241 mask entries. Use "l" rather than "L" in the fmovem entries.
242 * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
244 (m68k_scan_mask): New function, split out from...
245 (print_insn_m68k): ...here. If no architecture has been set,
246 first try printing an m680x0 instruction, then try a Coldfire one.
248 2006-05-24 Nick Clifton <nickc@redhat.com>
250 * po/ga.po: Updated Irish translation.
252 2006-05-22 Nick Clifton <nickc@redhat.com>
254 * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
256 2006-05-22 Nick Clifton <nickc@redhat.com>
258 * po/nl.po: Updated translation.
260 2006-05-18 Alan Modra <amodra@bigpond.net.au>
262 * avr-dis.c: Formatting fix.
264 2006-05-14 Thiemo Seufer <ths@mips.com>
266 * mips16-opc.c (I1, I32, I64): New shortcut defines.
267 (mips16_opcodes): Change membership of instructions to their
270 2006-05-09 H.J. Lu <hongjiu.lu@intel.com>
272 * i386-dis.c (grps): Update sgdt/sidt for 64bit.
274 2006-05-05 Julian Brown <julian@codesourcery.com>
276 * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
279 2006-05-05 Thiemo Seufer <ths@mips.com>
280 David Ung <davidu@mips.com>
282 * mips-opc.c: Add macro for cache instruction.
284 2006-05-04 Thiemo Seufer <ths@mips.com>
285 Nigel Stephens <nigel@mips.com>
286 David Ung <davidu@mips.com>
288 * mips-dis.c (mips_arch_choices): Add smartmips instruction
289 decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
290 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
292 * mips-opc.c: fix random typos in comments.
293 (INSN_SMARTMIPS): New defines.
294 (mips_builtin_opcodes): Add paired single support for MIPS32R2.
295 Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
296 flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
297 FP_S and FP_D flags to denote single and double register
298 accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
299 Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
300 for MIPS32R2. Add SmartMIPS instructions. Add two-argument
301 variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
303 * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
305 2006-05-03 Thiemo Seufer <ths@mips.com>
307 * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
309 2006-05-02 Thiemo Seufer <ths@mips.com>
310 Nigel Stephens <nigel@mips.com>
311 David Ung <davidu@mips.com>
313 * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
314 (print_mips16_insn_arg): Force mips16 to odd addresses.
316 2006-04-30 Thiemo Seufer <ths@mips.com>
317 David Ung <davidu@mips.com>
319 * mips-opc.c (mips_builtin_opcodes): Add udi instructions
321 * mips-dis.c (print_insn_args): Adds udi argument handling.
323 2006-04-28 James E Wilson <wilson@specifix.com>
325 * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
328 2006-04-28 Thiemo Seufer <ths@mips.com>
329 David Ung <davidu@mips.com>
330 Nigel Stephens <nigel@mips.com>
332 * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
335 2006-04-28 Thiemo Seufer <ths@mips.com>
336 Nigel Stephens <nigel@mips.com>
337 David Ung <davidu@mips.com>
339 * mips-dis.c (print_insn_args): Add mips_opcode argument.
340 (print_insn_mips): Adjust print_insn_args call.
342 2006-04-28 Thiemo Seufer <ths@mips.com>
343 Nigel Stephens <nigel@mips.com>
345 * mips-dis.c (print_insn_args): Print $fcc only for FP
346 instructions, use $cc elsewise.
348 2006-04-28 Thiemo Seufer <ths@mips.com>
349 Nigel Stephens <nigel@mips.com>
351 * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
352 Map MIPS16 registers to O32 names.
353 (print_mips16_insn_arg): Use mips16_reg_names.
355 2006-04-26 Julian Brown <julian@codesourcery.com>
357 * arm-dis.c (print_insn_neon): Disassemble floating-point constant
360 2006-04-26 Nathan Sidwell <nathan@codesourcery.com>
361 Julian Brown <julian@codesourcery.com>
363 * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
364 %<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?].
365 Add unified load/store instruction names.
366 (neon_opcode_table): New.
367 (arm_opcodes): Expand meaning of %<bitfield>['`?].
368 (arm_decode_bitfield): New.
369 (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
370 Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
371 (print_insn_neon): New.
372 (print_insn_arm): Adjust print_insn_coprocessor call. Call
373 print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
374 (print_insn_thumb32): Likewise.
376 2006-04-19 Alan Modra <amodra@bigpond.net.au>
378 * Makefile.am: Run "make dep-am".
379 * Makefile.in: Regenerate.
381 2006-04-19 Alan Modra <amodra@bigpond.net.au>
383 * avr-dis.c (avr_operand): Warning fix.
385 * configure: Regenerate.
387 2006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
389 * po/POTFILES.in: Regenerated.
391 2006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de>
394 * avr-dis.c (avr_operand): Arrange for a comment to appear before
395 the symolic form of an address, so that the output of objdump -d
398 2006-04-10 DJ Delorie <dj@redhat.com>
400 * m32c-asm.c: Regenerate.
402 2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
404 * Makefile.am: Add install-html target.
405 * Makefile.in: Regenerate.
407 2006-04-06 Nick Clifton <nickc@redhat.com>
409 * po/vi/po: Updated Vietnamese translation.
411 2006-03-31 Paul Koning <ni1d@arrl.net>
413 * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
415 2006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
417 * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
418 logic to identify halfword shifts.
420 2006-03-16 Paul Brook <paul@codesourcery.com>
422 * arm-dis.c (arm_opcodes): Rename swi to svc.
423 (thumb_opcodes): Ditto.
425 2006-03-13 DJ Delorie <dj@redhat.com>
427 * m32c-asm.c: Regenerate.
428 * m32c-desc.c: Likewise.
429 * m32c-desc.h: Likewise.
430 * m32c-dis.c: Likewise.
431 * m32c-ibld.c: Likewise.
432 * m32c-opc.c: Likewise.
433 * m32c-opc.h: Likewise.
435 2006-03-10 DJ Delorie <dj@redhat.com>
437 * m32c-desc.c: Regenerate with mul.l, mulu.l.
438 * m32c-opc.c: Likewise.
439 * m32c-opc.h: Likewise.
442 2006-03-09 Nick Clifton <nickc@redhat.com>
444 * po/sv.po: Updated Swedish translation.
446 2006-03-07 H.J. Lu <hongjiu.lu@intel.com>
449 * i386-dis.c (REP_Fixup): New function.
450 (AL): Remove duplicate.
455 (indirDXr): Likewise.
458 (dis386): Updated entries of ins, outs, movs, lods and stos.
460 2006-03-05 Nick Clifton <nickc@redhat.com>
462 * cgen-ibld.in (insert_normal): Cope with attempts to insert a
463 signed 32-bit value into an unsigned 32-bit field when the host is
465 * fr30-ibld.c: Regenerate.
466 * frv-ibld.c: Regenerate.
467 * ip2k-ibld.c: Regenerate.
468 * iq2000-asm.c: Regenerate.
469 * iq2000-ibld.c: Regenerate.
470 * m32c-ibld.c: Regenerate.
471 * m32r-ibld.c: Regenerate.
472 * openrisc-ibld.c: Regenerate.
473 * xc16x-ibld.c: Regenerate.
474 * xstormy16-ibld.c: Regenerate.
476 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
478 * xc16x-asm.c: Regenerate.
479 * xc16x-dis.c: Regenerate.
481 2006-02-27 Carlos O'Donell <carlos@codesourcery.com>
483 * po/Make-in: Add html target.
485 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
487 * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
488 Intel Merom New Instructions.
489 (THREE_BYTE_0): Likewise.
490 (THREE_BYTE_1): Likewise.
491 (three_byte_table): Likewise.
492 (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
493 THREE_BYTE_1 for entry 0x3a.
494 (twobyte_has_modrm): Updated.
495 (twobyte_uses_SSE_prefix): Likewise.
496 (print_insn): Handle 3-byte opcodes used by Intel Merom New
499 2006-02-24 David S. Miller <davem@sunset.davemloft.net>
501 * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
502 (v9_hpriv_reg_names): New table.
503 (print_insn_sparc): Allow values up to 16 for '?' and '!'.
504 New cases '$' and '%' for read/write hyperprivileged register.
505 * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
506 window handling and rdhpr/wrhpr instructions.
508 2006-02-24 DJ Delorie <dj@redhat.com>
510 * m32c-desc.c: Regenerate with linker relaxation attributes.
511 * m32c-desc.h: Likewise.
512 * m32c-dis.c: Likewise.
513 * m32c-opc.c: Likewise.
515 2006-02-24 Paul Brook <paul@codesourcery.com>
517 * arm-dis.c (arm_opcodes): Add V7 instructions.
518 (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
519 (print_arm_address): New function.
520 (print_insn_arm): Use it. Add 'P' and 'U' cases.
521 (psr_name): New function.
522 (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
524 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
526 * ia64-opc-i.c (bXc): New.
528 (OpX2TaTbYaXcC): Likewise.
531 (ia64_opcodes_i): Add instructions for tf.
533 * ia64-opc.h (IMMU5b): New.
535 * ia64-asmtab.c: Regenerated.
537 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
539 * ia64-gen.c: Update copyright years.
540 * ia64-opc-b.c: Likewise.
542 2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
544 * ia64-gen.c (lookup_regindex): Handle ".vm".
545 (print_dependency_table): Handle '\"'.
547 * ia64-ic.tbl: Updated from SDM 2.2.
548 * ia64-raw.tbl: Likewise.
549 * ia64-waw.tbl: Likewise.
550 * ia64-asmtab.c: Regenerated.
552 * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
554 2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
555 Anil Paranjape <anilp1@kpitcummins.com>
556 Shilin Shakti <shilins@kpitcummins.com>
558 * xc16x-desc.h: New file
559 * xc16x-desc.c: New file
560 * xc16x-opc.h: New file
561 * xc16x-opc.c: New file
562 * xc16x-ibld.c: New file
563 * xc16x-asm.c: New file
564 * xc16x-dis.c: New file
565 * Makefile.am: Entries for xc16x
566 * Makefile.in: Regenerate
567 * cofigure.in: Add xc16x target information.
568 * configure: Regenerate.
569 * disassemble.c: Add xc16x target information.
571 2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
573 * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
576 2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
578 * i386-dis.c ('Z'): Add a new macro.
579 (dis386_twobyte): Use "movZ" for control register moves.
581 2006-02-10 Nick Clifton <nickc@redhat.com>
583 * iq2000-asm.c: Regenerate.
585 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
587 * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
589 2006-01-26 David Ung <davidu@mips.com>
591 * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
592 ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
593 floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
594 nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
595 rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
597 2006-01-18 Arnold Metselaar <arnoldm@sourceware.org>
599 * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
600 ld_d_r, pref_xd_cb): Use signed char to hold data to be
602 * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
603 buffer overflows when disassembling instructions like
605 * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
606 operand, if the offset is negative.
608 2006-01-17 Arnold Metselaar <arnoldm@sourceware.org>
610 * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
611 unsigned char to hold data to be disassembled.
613 2006-01-17 Andreas Schwab <schwab@suse.de>
616 * disassemble.c (disassemble_init_for_target): Set
617 disassembler_needs_relocs for bfd_arch_arm.
619 2006-01-16 Paul Brook <paul@codesourcery.com>
621 * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
622 f?add?, and f?sub? instructions.
624 2006-01-16 Nick Clifton <nickc@redhat.com>
626 * po/zh_CN.po: New Chinese (simplified) translation.
627 * configure.in (ALL_LINGUAS): Add "zh_CH".
628 * configure: Regenerate.
630 2006-01-05 Paul Brook <paul@codesourcery.com>
632 * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
634 2006-01-06 DJ Delorie <dj@redhat.com>
636 * m32c-desc.c: Regenerate.
637 * m32c-opc.c: Regenerate.
638 * m32c-opc.h: Regenerate.
640 2006-01-03 DJ Delorie <dj@redhat.com>
642 * cgen-ibld.in (extract_normal): Avoid memory range errors.
643 * m32c-ibld.c: Regenerated.
645 For older changes see ChangeLog-2005
651 version-control: never