1 2018-07-30 Jim Wilson <jimw@sifive.com>
3 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
5 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
7 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
9 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
10 * Makefile.in: Regenerated.
11 * configure.ac: Add C-SKY.
12 * configure: Regenerated.
13 * csky-dis.c: New file.
14 * csky-opc.h: New file.
15 * disassemble.c (ARCH_csky): Define.
16 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
17 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
19 2018-07-27 Alan Modra <amodra@gmail.com>
21 * ppc-opc.c (insert_sprbat): Correct function parameter and
23 (extract_sprbat): Likewise, variable too.
25 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
26 Alan Modra <amodra@gmail.com>
28 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
29 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
30 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
31 support disjointed BAT.
32 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
33 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
34 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
36 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
37 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
39 * i386-gen.c (adjust_broadcast_modifier): New function.
40 (process_i386_opcode_modifier): Add an argument for operands.
41 Adjust the Broadcast value based on operands.
42 (output_i386_opcode): Pass operand_types to
43 process_i386_opcode_modifier.
44 (process_i386_opcodes): Pass NULL as operands to
45 process_i386_opcode_modifier.
46 * i386-opc.h (BYTE_BROADCAST): New.
47 (WORD_BROADCAST): Likewise.
48 (DWORD_BROADCAST): Likewise.
49 (QWORD_BROADCAST): Likewise.
50 (i386_opcode_modifier): Expand broadcast to 3 bits.
51 * i386-tbl.h: Regenerated.
53 2018-07-24 Alan Modra <amodra@gmail.com>
56 * or1k-desc.h: Regenerate.
58 2018-07-24 Jan Beulich <jbeulich@suse.com>
60 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
61 vcvtusi2ss, and vcvtusi2sd.
62 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
63 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
64 * i386-tbl.h: Re-generate.
66 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
68 * arc-opc.c (extract_w6): Fix extending the sign.
70 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
72 * arc-tbl.h (vewt): Allow it for ARC EM family.
74 2018-07-23 Alan Modra <amodra@gmail.com>
77 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
78 opcode variants for mtspr/mfspr encodings.
80 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
81 Maciej W. Rozycki <macro@mips.com>
83 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
84 loongson3a descriptors.
85 (parse_mips_ase_option): Handle -M loongson-mmi option.
86 (print_mips_disassembler_options): Document -M loongson-mmi.
87 * mips-opc.c (LMMI): New macro.
88 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
91 2018-07-19 Jan Beulich <jbeulich@suse.com>
93 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
94 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
95 IgnoreSize and [XYZ]MMword where applicable.
96 * i386-tbl.h: Re-generate.
98 2018-07-19 Jan Beulich <jbeulich@suse.com>
100 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
101 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
102 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
103 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
104 * i386-tbl.h: Re-generate.
106 2018-07-19 Jan Beulich <jbeulich@suse.com>
108 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
109 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
110 VPCLMULQDQ templates into their respective AVX512VL counterparts
111 where possible, using Disp8ShiftVL and CheckRegSize instead of
112 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
113 * i386-tbl.h: Re-generate.
115 2018-07-19 Jan Beulich <jbeulich@suse.com>
117 * i386-opc.tbl: Fold AVX512DQ templates into their respective
118 AVX512VL counterparts where possible, using Disp8ShiftVL and
119 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
120 IgnoreSize) as appropriate.
121 * i386-tbl.h: Re-generate.
123 2018-07-19 Jan Beulich <jbeulich@suse.com>
125 * i386-opc.tbl: Fold AVX512BW templates into their respective
126 AVX512VL counterparts where possible, using Disp8ShiftVL and
127 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
128 IgnoreSize) as appropriate.
129 * i386-tbl.h: Re-generate.
131 2018-07-19 Jan Beulich <jbeulich@suse.com>
133 * i386-opc.tbl: Fold AVX512CD templates into their respective
134 AVX512VL counterparts where possible, using Disp8ShiftVL and
135 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
136 IgnoreSize) as appropriate.
137 * i386-tbl.h: Re-generate.
139 2018-07-19 Jan Beulich <jbeulich@suse.com>
141 * i386-opc.h (DISP8_SHIFT_VL): New.
142 * i386-opc.tbl (Disp8ShiftVL): Define.
143 (various): Fold AVX512VL templates into their respective
144 AVX512F counterparts where possible, using Disp8ShiftVL and
145 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
146 IgnoreSize) as appropriate.
147 * i386-tbl.h: Re-generate.
149 2018-07-19 Jan Beulich <jbeulich@suse.com>
151 * Makefile.am: Change dependencies and rule for
152 $(srcdir)/i386-init.h.
153 * Makefile.in: Re-generate.
154 * i386-gen.c (process_i386_opcodes): New local variable
155 "marker". Drop opening of input file. Recognize marker and line
157 * i386-opc.tbl (OPCODE_I386_H): Define.
158 (i386-opc.h): Include it.
161 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
164 * i386-opc.h (Byte): Update comments.
173 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
175 * i386-tbl.h: Regenerated.
177 2018-07-12 Sudakshina Das <sudi.das@arm.com>
179 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
180 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
181 * aarch64-asm-2.c: Regenerate.
182 * aarch64-dis-2.c: Regenerate.
183 * aarch64-opc-2.c: Regenerate.
185 2018-07-12 Tamar Christina <tamar.christina@arm.com>
188 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
189 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
190 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
191 sqdmulh, sqrdmulh): Use Em16.
193 2018-07-11 Sudakshina Das <sudi.das@arm.com>
195 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
196 csdb together with them.
197 (thumb32_opcodes): Likewise.
199 2018-07-11 Jan Beulich <jbeulich@suse.com>
201 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
202 requiring 32-bit registers as operands 2 and 3. Improve
204 (mwait, mwaitx): Fold templates. Improve comments.
205 OPERAND_TYPE_INOUTPORTREG.
206 * i386-tbl.h: Re-generate.
208 2018-07-11 Jan Beulich <jbeulich@suse.com>
210 * i386-gen.c (operand_type_init): Remove
211 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
212 OPERAND_TYPE_INOUTPORTREG.
213 * i386-init.h: Re-generate.
215 2018-07-11 Jan Beulich <jbeulich@suse.com>
217 * i386-opc.tbl (wrssd, wrussd): Add Dword.
218 (wrssq, wrussq): Add Qword.
219 * i386-tbl.h: Re-generate.
221 2018-07-11 Jan Beulich <jbeulich@suse.com>
223 * i386-opc.h: Rename OTMax to OTNum.
224 (OTNumOfUints): Adjust calculation.
225 (OTUnused): Directly alias to OTNum.
227 2018-07-09 Maciej W. Rozycki <macro@mips.com>
229 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
231 (lea_reg_xys): Likewise.
232 (print_insn_loop_primitive): Rename `reg' local variable to
235 2018-07-06 Tamar Christina <tamar.christina@arm.com>
238 * aarch64-tbl.h (ldarh): Fix disassembly mask.
240 2018-07-06 Tamar Christina <tamar.christina@arm.com>
243 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
244 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
246 2018-07-02 Maciej W. Rozycki <macro@mips.com>
249 * mips-dis.c (mips_option_arg_t): New enumeration.
250 (mips_options): New variable.
251 (disassembler_options_mips): New function.
252 (print_mips_disassembler_options): Reimplement in terms of
253 `disassembler_options_mips'.
254 * arm-dis.c (disassembler_options_arm): Adapt to using the
255 `disasm_options_and_args_t' structure.
256 * ppc-dis.c (disassembler_options_powerpc): Likewise.
257 * s390-dis.c (disassembler_options_s390): Likewise.
259 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
261 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
263 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
264 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
265 * testsuite/ld-arm/tls-longplt.d: Likewise.
267 2018-06-29 Tamar Christina <tamar.christina@arm.com>
270 * aarch64-asm-2.c: Regenerate.
271 * aarch64-dis-2.c: Likewise.
272 * aarch64-opc-2.c: Likewise.
273 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
274 * aarch64-opc.c (operand_general_constraint_met_p,
275 aarch64_print_operand): Likewise.
276 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
277 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
279 (AARCH64_OPERANDS): Add Em2.
281 2018-06-26 Nick Clifton <nickc@redhat.com>
283 * po/uk.po: Updated Ukranian translation.
284 * po/de.po: Updated German translation.
285 * po/pt_BR.po: Updated Brazilian Portuguese translation.
287 2018-06-26 Nick Clifton <nickc@redhat.com>
289 * nfp-dis.c: Fix spelling mistake.
291 2018-06-24 Nick Clifton <nickc@redhat.com>
293 * configure: Regenerate.
294 * po/opcodes.pot: Regenerate.
296 2018-06-24 Nick Clifton <nickc@redhat.com>
300 2018-06-19 Tamar Christina <tamar.christina@arm.com>
302 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
303 * aarch64-asm-2.c: Regenerate.
304 * aarch64-dis-2.c: Likewise.
306 2018-06-21 Maciej W. Rozycki <macro@mips.com>
308 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
309 `-M ginv' option description.
311 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
314 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
317 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
319 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
320 * configure.ac: Remove AC_PREREQ.
321 * Makefile.in: Re-generate.
322 * aclocal.m4: Re-generate.
323 * configure: Re-generate.
325 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
327 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
328 mips64r6 descriptors.
329 (parse_mips_ase_option): Handle -Mginv option.
330 (print_mips_disassembler_options): Document -Mginv.
331 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
333 (mips_opcodes): Define ginvi and ginvt.
335 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
336 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
338 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
339 * mips-opc.c (CRC, CRC64): New macros.
340 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
341 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
344 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
347 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
348 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
350 2018-06-06 Alan Modra <amodra@gmail.com>
352 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
353 setjmp. Move init for some other vars later too.
355 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
357 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
358 (dis_private): Add new fields for property section tracking.
359 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
360 (xtensa_instruction_fits): New functions.
361 (fetch_data): Bump minimal fetch size to 4.
362 (print_insn_xtensa): Make struct dis_private static.
363 Load and prepare property table on section change.
364 Don't disassemble literals. Don't disassemble instructions that
365 cross property table boundaries.
367 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
369 * configure: Regenerated.
371 2018-06-01 Jan Beulich <jbeulich@suse.com>
373 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
374 * i386-tbl.h: Re-generate.
376 2018-06-01 Jan Beulich <jbeulich@suse.com>
378 * i386-opc.tbl (sldt, str): Add NoRex64.
379 * i386-tbl.h: Re-generate.
381 2018-06-01 Jan Beulich <jbeulich@suse.com>
383 * i386-opc.tbl (invpcid): Add Oword.
384 * i386-tbl.h: Re-generate.
386 2018-06-01 Alan Modra <amodra@gmail.com>
388 * sysdep.h (_bfd_error_handler): Don't declare.
389 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
390 * rl78-decode.opc: Likewise.
391 * msp430-decode.c: Regenerate.
392 * rl78-decode.c: Regenerate.
394 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
396 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
397 * i386-init.h : Regenerated.
399 2018-05-25 Alan Modra <amodra@gmail.com>
401 * Makefile.in: Regenerate.
402 * po/POTFILES.in: Regenerate.
404 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
406 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
407 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
408 (insert_bab, extract_bab, insert_btab, extract_btab,
409 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
410 (BAT, BBA VBA RBS XB6S): Delete macros.
411 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
412 (BB, BD, RBX, XC6): Update for new macros.
413 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
414 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
415 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
416 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
418 2018-05-18 John Darrington <john@darrington.wattle.id.au>
420 * Makefile.am: Add support for s12z architecture.
421 * configure.ac: Likewise.
422 * disassemble.c: Likewise.
423 * disassemble.h: Likewise.
424 * Makefile.in: Regenerate.
425 * configure: Regenerate.
426 * s12z-dis.c: New file.
429 2018-05-18 Alan Modra <amodra@gmail.com>
431 * nfp-dis.c: Don't #include libbfd.h.
432 (init_nfp3200_priv): Use bfd_get_section_contents.
433 (nit_nfp6000_mecsr_sec): Likewise.
435 2018-05-17 Nick Clifton <nickc@redhat.com>
437 * po/zh_CN.po: Updated simplified Chinese translation.
439 2018-05-16 Tamar Christina <tamar.christina@arm.com>
442 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
443 * aarch64-dis-2.c: Regenerate.
445 2018-05-15 Tamar Christina <tamar.christina@arm.com>
448 * aarch64-asm.c (opintl.h): Include.
449 (aarch64_ins_sysreg): Enforce read/write constraints.
450 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
451 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
452 (F_REG_READ, F_REG_WRITE): New.
453 * aarch64-opc.c (aarch64_print_operand): Generate notes for
455 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
456 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
457 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
458 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
459 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
460 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
461 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
462 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
463 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
464 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
465 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
466 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
467 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
468 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
469 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
470 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
471 msr (F_SYS_WRITE), mrs (F_SYS_READ).
473 2018-05-15 Tamar Christina <tamar.christina@arm.com>
476 * aarch64-dis.c (no_notes: New.
477 (parse_aarch64_dis_option): Support notes.
478 (aarch64_decode_insn, print_operands): Likewise.
479 (print_aarch64_disassembler_options): Document notes.
480 * aarch64-opc.c (aarch64_print_operand): Support notes.
482 2018-05-15 Tamar Christina <tamar.christina@arm.com>
485 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
486 and take error struct.
487 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
488 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
489 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
490 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
491 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
492 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
493 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
494 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
495 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
496 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
497 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
498 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
499 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
500 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
501 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
502 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
503 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
504 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
505 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
506 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
507 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
508 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
509 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
510 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
511 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
512 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
513 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
514 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
515 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
516 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
517 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
518 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
519 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
520 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
521 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
522 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
523 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
524 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
525 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
526 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
527 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
528 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
529 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
530 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
531 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
532 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
533 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
534 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
535 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
536 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
537 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
538 (determine_disassembling_preference, aarch64_decode_insn,
539 print_insn_aarch64_word, print_insn_data): Take errors struct.
540 (print_insn_aarch64): Use errors.
541 * aarch64-asm-2.c: Regenerate.
542 * aarch64-dis-2.c: Regenerate.
543 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
544 boolean in aarch64_insert_operan.
545 (print_operand_extractor): Likewise.
546 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
548 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
550 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
552 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
554 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
556 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
558 * cr16-opc.c (cr16_instruction): Comment typo fix.
559 * hppa-dis.c (print_insn_hppa): Likewise.
561 2018-05-08 Jim Wilson <jimw@sifive.com>
563 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
564 (match_c_slli64, match_srxi_as_c_srxi): New.
565 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
566 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
567 <c.slli, c.srli, c.srai>: Use match_s_slli.
568 <c.slli64, c.srli64, c.srai64>: New.
570 2018-05-08 Alan Modra <amodra@gmail.com>
572 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
573 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
574 partition opcode space for index lookup.
576 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
578 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
579 <insn_length>: ...with this. Update usage.
580 Remove duplicate call to *info->memory_error_func.
582 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
583 H.J. Lu <hongjiu.lu@intel.com>
585 * i386-dis.c (Gva): New.
586 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
587 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
588 (prefix_table): New instructions (see prefix above).
589 (mod_table): New instructions (see prefix above).
590 (OP_G): Handle va_mode.
591 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
593 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
594 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
595 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
596 * i386-opc.tbl: Add movidir{i,64b}.
597 * i386-init.h: Regenerated.
598 * i386-tbl.h: Likewise.
600 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
602 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
604 * i386-opc.h (AddrPrefixOp0): Renamed to ...
605 (AddrPrefixOpReg): This.
606 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
607 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
609 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
611 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
612 (vle_num_opcodes): Likewise.
613 (spe2_num_opcodes): Likewise.
614 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
616 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
617 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
620 2018-05-01 Tamar Christina <tamar.christina@arm.com>
622 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
624 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
626 Makefile.am: Added nfp-dis.c.
627 configure.ac: Added bfd_nfp_arch.
628 disassemble.h: Added print_insn_nfp prototype.
629 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
630 nfp-dis.c: New, for NFP support.
631 po/POTFILES.in: Added nfp-dis.c to the list.
632 Makefile.in: Regenerate.
633 configure: Regenerate.
635 2018-04-26 Jan Beulich <jbeulich@suse.com>
637 * i386-opc.tbl: Fold various non-memory operand AVX512VL
638 templates into their base ones.
639 * i386-tlb.h: Re-generate.
641 2018-04-26 Jan Beulich <jbeulich@suse.com>
643 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
644 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
645 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
646 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
647 * i386-init.h: Re-generate.
649 2018-04-26 Jan Beulich <jbeulich@suse.com>
651 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
652 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
653 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
654 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
656 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
658 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
660 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
661 cpuregzmm, and cpuregmask.
662 * i386-init.h: Re-generate.
663 * i386-tbl.h: Re-generate.
665 2018-04-26 Jan Beulich <jbeulich@suse.com>
667 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
668 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
669 * i386-init.h: Re-generate.
671 2018-04-26 Jan Beulich <jbeulich@suse.com>
673 * i386-gen.c (VexImmExt): Delete.
674 * i386-opc.h (VexImmExt, veximmext): Delete.
675 * i386-opc.tbl: Drop all VexImmExt uses.
676 * i386-tlb.h: Re-generate.
678 2018-04-25 Jan Beulich <jbeulich@suse.com>
680 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
682 * i386-tlb.h: Re-generate.
684 2018-04-25 Tamar Christina <tamar.christina@arm.com>
686 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
688 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
690 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
692 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
693 (cpu_flags): Add CpuCLDEMOTE.
694 * i386-init.h: Regenerate.
695 * i386-opc.h (enum): Add CpuCLDEMOTE,
696 (i386_cpu_flags): Add cpucldemote.
697 * i386-opc.tbl: Add cldemote.
698 * i386-tbl.h: Regenerate.
700 2018-04-16 Alan Modra <amodra@gmail.com>
702 * Makefile.am: Remove sh5 and sh64 support.
703 * configure.ac: Likewise.
704 * disassemble.c: Likewise.
705 * disassemble.h: Likewise.
706 * sh-dis.c: Likewise.
707 * sh64-dis.c: Delete.
708 * sh64-opc.c: Delete.
709 * sh64-opc.h: Delete.
710 * Makefile.in: Regenerate.
711 * configure: Regenerate.
712 * po/POTFILES.in: Regenerate.
714 2018-04-16 Alan Modra <amodra@gmail.com>
716 * Makefile.am: Remove w65 support.
717 * configure.ac: Likewise.
718 * disassemble.c: Likewise.
719 * disassemble.h: Likewise.
722 * Makefile.in: Regenerate.
723 * configure: Regenerate.
724 * po/POTFILES.in: Regenerate.
726 2018-04-16 Alan Modra <amodra@gmail.com>
728 * configure.ac: Remove we32k support.
729 * configure: Regenerate.
731 2018-04-16 Alan Modra <amodra@gmail.com>
733 * Makefile.am: Remove m88k support.
734 * configure.ac: Likewise.
735 * disassemble.c: Likewise.
736 * disassemble.h: Likewise.
737 * m88k-dis.c: Delete.
738 * Makefile.in: Regenerate.
739 * configure: Regenerate.
740 * po/POTFILES.in: Regenerate.
742 2018-04-16 Alan Modra <amodra@gmail.com>
744 * Makefile.am: Remove i370 support.
745 * configure.ac: Likewise.
746 * disassemble.c: Likewise.
747 * disassemble.h: Likewise.
748 * i370-dis.c: Delete.
749 * i370-opc.c: Delete.
750 * Makefile.in: Regenerate.
751 * configure: Regenerate.
752 * po/POTFILES.in: Regenerate.
754 2018-04-16 Alan Modra <amodra@gmail.com>
756 * Makefile.am: Remove h8500 support.
757 * configure.ac: Likewise.
758 * disassemble.c: Likewise.
759 * disassemble.h: Likewise.
760 * h8500-dis.c: Delete.
761 * h8500-opc.h: Delete.
762 * Makefile.in: Regenerate.
763 * configure: Regenerate.
764 * po/POTFILES.in: Regenerate.
766 2018-04-16 Alan Modra <amodra@gmail.com>
768 * configure.ac: Remove tahoe support.
769 * configure: Regenerate.
771 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
773 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
775 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
777 * i386-tbl.h: Regenerated.
779 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
781 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
782 PREFIX_MOD_1_0FAE_REG_6.
784 (OP_E_register): Use va_mode.
785 * i386-dis-evex.h (prefix_table):
786 New instructions (see prefixes above).
787 * i386-gen.c (cpu_flag_init): Add WAITPKG.
788 (cpu_flags): Likewise.
789 * i386-opc.h (enum): Likewise.
790 (i386_cpu_flags): Likewise.
791 * i386-opc.tbl: Add umonitor, umwait, tpause.
792 * i386-init.h: Regenerate.
793 * i386-tbl.h: Likewise.
795 2018-04-11 Alan Modra <amodra@gmail.com>
797 * opcodes/i860-dis.c: Delete.
798 * opcodes/i960-dis.c: Delete.
799 * Makefile.am: Remove i860 and i960 support.
800 * configure.ac: Likewise.
801 * disassemble.c: Likewise.
802 * disassemble.h: Likewise.
803 * Makefile.in: Regenerate.
804 * configure: Regenerate.
805 * po/POTFILES.in: Regenerate.
807 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
810 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
812 (print_insn): Clear vex instead of vex.evex.
814 2018-04-04 Nick Clifton <nickc@redhat.com>
816 * po/es.po: Updated Spanish translation.
818 2018-03-28 Jan Beulich <jbeulich@suse.com>
820 * i386-gen.c (opcode_modifiers): Delete VecESize.
821 * i386-opc.h (VecESize): Delete.
822 (struct i386_opcode_modifier): Delete vecesize.
823 * i386-opc.tbl: Drop VecESize.
824 * i386-tlb.h: Re-generate.
826 2018-03-28 Jan Beulich <jbeulich@suse.com>
828 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
829 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
830 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
831 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
832 * i386-tlb.h: Re-generate.
834 2018-03-28 Jan Beulich <jbeulich@suse.com>
836 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
838 * i386-tlb.h: Re-generate.
840 2018-03-28 Jan Beulich <jbeulich@suse.com>
842 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
843 (vex_len_table): Drop Y for vcvt*2si.
844 (putop): Replace plain 'Y' handling by abort().
846 2018-03-28 Nick Clifton <nickc@redhat.com>
849 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
850 instructions with only a base address register.
851 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
852 handle AARHC64_OPND_SVE_ADDR_R.
853 (aarch64_print_operand): Likewise.
854 * aarch64-asm-2.c: Regenerate.
855 * aarch64_dis-2.c: Regenerate.
856 * aarch64-opc-2.c: Regenerate.
858 2018-03-22 Jan Beulich <jbeulich@suse.com>
860 * i386-opc.tbl: Drop VecESize from register only insn forms and
861 memory forms not allowing broadcast.
862 * i386-tlb.h: Re-generate.
864 2018-03-22 Jan Beulich <jbeulich@suse.com>
866 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
867 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
868 sha256*): Drop Disp<N>.
870 2018-03-22 Jan Beulich <jbeulich@suse.com>
872 * i386-dis.c (EbndS, bnd_swap_mode): New.
873 (prefix_table): Use EbndS.
874 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
875 * i386-opc.tbl (bndmov): Move misplaced Load.
876 * i386-tlb.h: Re-generate.
878 2018-03-22 Jan Beulich <jbeulich@suse.com>
880 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
881 templates allowing memory operands and folded ones for register
883 * i386-tlb.h: Re-generate.
885 2018-03-22 Jan Beulich <jbeulich@suse.com>
887 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
888 256-bit templates. Drop redundant leftover Disp<N>.
889 * i386-tlb.h: Re-generate.
891 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
893 * riscv-opc.c (riscv_insn_types): New.
895 2018-03-13 Nick Clifton <nickc@redhat.com>
897 * po/pt_BR.po: Updated Brazilian Portuguese translation.
899 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
901 * i386-opc.tbl: Add Optimize to clr.
902 * i386-tbl.h: Regenerated.
904 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
906 * i386-gen.c (opcode_modifiers): Remove OldGcc.
907 * i386-opc.h (OldGcc): Removed.
908 (i386_opcode_modifier): Remove oldgcc.
909 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
910 instructions for old (<= 2.8.1) versions of gcc.
911 * i386-tbl.h: Regenerated.
913 2018-03-08 Jan Beulich <jbeulich@suse.com>
915 * i386-opc.h (EVEXDYN): New.
916 * i386-opc.tbl: Fold various AVX512VL templates.
917 * i386-tlb.h: Re-generate.
919 2018-03-08 Jan Beulich <jbeulich@suse.com>
921 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
922 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
923 vpexpandd, vpexpandq): Fold AFX512VF templates.
924 * i386-tlb.h: Re-generate.
926 2018-03-08 Jan Beulich <jbeulich@suse.com>
928 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
929 Fold 128- and 256-bit VEX-encoded templates.
930 * i386-tlb.h: Re-generate.
932 2018-03-08 Jan Beulich <jbeulich@suse.com>
934 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
935 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
936 vpexpandd, vpexpandq): Fold AVX512F templates.
937 * i386-tlb.h: Re-generate.
939 2018-03-08 Jan Beulich <jbeulich@suse.com>
941 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
942 64-bit templates. Drop Disp<N>.
943 * i386-tlb.h: Re-generate.
945 2018-03-08 Jan Beulich <jbeulich@suse.com>
947 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
948 and 256-bit templates.
949 * i386-tlb.h: Re-generate.
951 2018-03-08 Jan Beulich <jbeulich@suse.com>
953 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
954 * i386-tlb.h: Re-generate.
956 2018-03-08 Jan Beulich <jbeulich@suse.com>
958 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
960 * i386-tlb.h: Re-generate.
962 2018-03-08 Jan Beulich <jbeulich@suse.com>
964 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
965 * i386-tlb.h: Re-generate.
967 2018-03-08 Jan Beulich <jbeulich@suse.com>
969 * i386-gen.c (opcode_modifiers): Delete FloatD.
970 * i386-opc.h (FloatD): Delete.
971 (struct i386_opcode_modifier): Delete floatd.
972 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
974 * i386-tlb.h: Re-generate.
976 2018-03-08 Jan Beulich <jbeulich@suse.com>
978 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
980 2018-03-08 Jan Beulich <jbeulich@suse.com>
982 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
983 * i386-tlb.h: Re-generate.
985 2018-03-08 Jan Beulich <jbeulich@suse.com>
987 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
989 * i386-tlb.h: Re-generate.
991 2018-03-07 Alan Modra <amodra@gmail.com>
993 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
995 * disassemble.h (print_insn_rs6000): Delete.
996 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
997 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
998 (print_insn_rs6000): Delete.
1000 2018-03-03 Alan Modra <amodra@gmail.com>
1002 * sysdep.h (opcodes_error_handler): Define.
1003 (_bfd_error_handler): Declare.
1004 * Makefile.am: Remove stray #.
1005 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1007 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1008 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1009 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1010 opcodes_error_handler to print errors. Standardize error messages.
1011 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1012 and include opintl.h.
1013 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1014 * i386-gen.c: Standardize error messages.
1015 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1016 * Makefile.in: Regenerate.
1017 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1018 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1019 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1020 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1021 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1022 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1023 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1024 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1025 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1026 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1027 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1028 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1029 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1031 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1033 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1034 vpsub[bwdq] instructions.
1035 * i386-tbl.h: Regenerated.
1037 2018-03-01 Alan Modra <amodra@gmail.com>
1039 * configure.ac (ALL_LINGUAS): Sort.
1040 * configure: Regenerate.
1042 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1044 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1045 macro by assignements.
1047 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1050 * i386-gen.c (opcode_modifiers): Add Optimize.
1051 * i386-opc.h (Optimize): New enum.
1052 (i386_opcode_modifier): Add optimize.
1053 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1054 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1055 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1056 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1057 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1059 * i386-tbl.h: Regenerated.
1061 2018-02-26 Alan Modra <amodra@gmail.com>
1063 * crx-dis.c (getregliststring): Allocate a large enough buffer
1064 to silence false positive gcc8 warning.
1066 2018-02-22 Shea Levy <shea@shealevy.com>
1068 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1070 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1072 * i386-opc.tbl: Add {rex},
1073 * i386-tbl.h: Regenerated.
1075 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1077 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1078 (mips16_opcodes): Replace `M' with `m' for "restore".
1080 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1082 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1084 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1086 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1087 variable to `function_index'.
1089 2018-02-13 Nick Clifton <nickc@redhat.com>
1092 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1093 about truncation of printing.
1095 2018-02-12 Henry Wong <henry@stuffedcow.net>
1097 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1099 2018-02-05 Nick Clifton <nickc@redhat.com>
1101 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1103 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1105 * i386-dis.c (enum): Add pconfig.
1106 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1107 (cpu_flags): Add CpuPCONFIG.
1108 * i386-opc.h (enum): Add CpuPCONFIG.
1109 (i386_cpu_flags): Add cpupconfig.
1110 * i386-opc.tbl: Add PCONFIG instruction.
1111 * i386-init.h: Regenerate.
1112 * i386-tbl.h: Likewise.
1114 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1116 * i386-dis.c (enum): Add PREFIX_0F09.
1117 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1118 (cpu_flags): Add CpuWBNOINVD.
1119 * i386-opc.h (enum): Add CpuWBNOINVD.
1120 (i386_cpu_flags): Add cpuwbnoinvd.
1121 * i386-opc.tbl: Add WBNOINVD instruction.
1122 * i386-init.h: Regenerate.
1123 * i386-tbl.h: Likewise.
1125 2018-01-17 Jim Wilson <jimw@sifive.com>
1127 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1129 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1131 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1132 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1133 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1134 (cpu_flags): Add CpuIBT, CpuSHSTK.
1135 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1136 (i386_cpu_flags): Add cpuibt, cpushstk.
1137 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1138 * i386-init.h: Regenerate.
1139 * i386-tbl.h: Likewise.
1141 2018-01-16 Nick Clifton <nickc@redhat.com>
1143 * po/pt_BR.po: Updated Brazilian Portugese translation.
1144 * po/de.po: Updated German translation.
1146 2018-01-15 Jim Wilson <jimw@sifive.com>
1148 * riscv-opc.c (match_c_nop): New.
1149 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1151 2018-01-15 Nick Clifton <nickc@redhat.com>
1153 * po/uk.po: Updated Ukranian translation.
1155 2018-01-13 Nick Clifton <nickc@redhat.com>
1157 * po/opcodes.pot: Regenerated.
1159 2018-01-13 Nick Clifton <nickc@redhat.com>
1161 * configure: Regenerate.
1163 2018-01-13 Nick Clifton <nickc@redhat.com>
1165 2.30 branch created.
1167 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1169 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1170 * i386-tbl.h: Regenerate.
1172 2018-01-10 Jan Beulich <jbeulich@suse.com>
1174 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1175 * i386-tbl.h: Re-generate.
1177 2018-01-10 Jan Beulich <jbeulich@suse.com>
1179 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1180 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1181 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1182 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1183 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1184 Disp8MemShift of AVX512VL forms.
1185 * i386-tbl.h: Re-generate.
1187 2018-01-09 Jim Wilson <jimw@sifive.com>
1189 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1190 then the hi_addr value is zero.
1192 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1194 * arm-dis.c (arm_opcodes): Add csdb.
1195 (thumb32_opcodes): Add csdb.
1197 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1199 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1200 * aarch64-asm-2.c: Regenerate.
1201 * aarch64-dis-2.c: Regenerate.
1202 * aarch64-opc-2.c: Regenerate.
1204 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1207 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1208 Remove AVX512 vmovd with 64-bit operands.
1209 * i386-tbl.h: Regenerated.
1211 2018-01-05 Jim Wilson <jimw@sifive.com>
1213 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1216 2018-01-03 Alan Modra <amodra@gmail.com>
1218 Update year range in copyright notice of all files.
1220 2018-01-02 Jan Beulich <jbeulich@suse.com>
1222 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1223 and OPERAND_TYPE_REGZMM entries.
1225 For older changes see ChangeLog-2017
1227 Copyright (C) 2018 Free Software Foundation, Inc.
1229 Copying and distribution of this file, with or without modification,
1230 are permitted in any medium without royalty provided the copyright
1231 notice and this notice are preserved.
1237 version-control: never