1 2019-06-13 Stafford Horne <shorne@gmail.com>
3 * or1k-asm.c: Regenerated.
4 * or1k-desc.c: Regenerated.
5 * or1k-desc.h: Regenerated.
6 * or1k-dis.c: Regenerated.
7 * or1k-ibld.c: Regenerated.
8 * or1k-opc.c: Regenerated.
9 * or1k-opc.h: Regenerated.
10 * or1k-opinst.c: Regenerated.
12 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
14 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
16 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
19 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
20 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
21 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
22 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
23 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
24 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
25 EVEX_LEN_0F3A1B_P_2_W_1.
26 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
27 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
28 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
29 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
30 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
31 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
32 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
33 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
35 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
38 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
39 EVEX.vvvv when disassembling VEX and EVEX instructions.
40 (OP_VEX): Set vex.register_specifier to 0 after readding
41 vex.register_specifier.
42 (OP_Vex_2src_1): Likewise.
43 (OP_Vex_2src_2): Likewise.
45 (OP_EX_Vex): Don't check vex.register_specifier.
46 (OP_XMM_Vex): Likewise.
48 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
49 Lili Cui <lili.cui@intel.com>
51 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
52 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
54 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
55 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
56 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
57 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
58 (i386_cpu_flags): Add cpuavx512_vp2intersect.
59 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
60 * i386-init.h: Regenerated.
61 * i386-tbl.h: Likewise.
63 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
64 Lili Cui <lili.cui@intel.com>
66 * doc/c-i386.texi: Document enqcmd.
67 * testsuite/gas/i386/enqcmd-intel.d: New file.
68 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
69 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
70 * testsuite/gas/i386/enqcmd.d: Likewise.
71 * testsuite/gas/i386/enqcmd.s: Likewise.
72 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
73 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
74 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
75 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
76 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
77 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
78 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
81 2019-06-04 Alan Hayward <alan.hayward@arm.com>
83 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
85 2019-06-03 Alan Modra <amodra@gmail.com>
87 * ppc-dis.c (prefix_opcd_indices): Correct size.
89 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
92 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
94 * i386-tbl.h: Regenerated.
96 2019-05-24 Alan Modra <amodra@gmail.com>
98 * po/POTFILES.in: Regenerate.
100 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
101 Alan Modra <amodra@gmail.com>
103 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
104 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
105 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
106 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
107 XTOP>): Define and add entries.
108 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
109 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
110 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
111 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
113 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
114 Alan Modra <amodra@gmail.com>
116 * ppc-dis.c (ppc_opts): Add "future" entry.
117 (PREFIX_OPCD_SEGS): Define.
118 (prefix_opcd_indices): New array.
119 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
120 (lookup_prefix): New function.
121 (print_insn_powerpc): Handle 64-bit prefix instructions.
122 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
123 (PMRR, POWERXX): Define.
124 (prefix_opcodes): New instruction table.
125 (prefix_num_opcodes): New constant.
127 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
129 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
130 * configure: Regenerated.
131 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
133 (HFILES): Add bpf-desc.h and bpf-opc.h.
134 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
135 bpf-ibld.c and bpf-opc.c.
137 * Makefile.in: Regenerated.
138 * disassemble.c (ARCH_bpf): Define.
139 (disassembler): Add case for bfd_arch_bpf.
140 (disassemble_init_for_target): Likewise.
141 (enum epbf_isa_attr): Define.
142 * disassemble.h: extern print_insn_bpf.
143 * bpf-asm.c: Generated.
144 * bpf-opc.h: Likewise.
145 * bpf-opc.c: Likewise.
146 * bpf-ibld.c: Likewise.
147 * bpf-dis.c: Likewise.
148 * bpf-desc.h: Likewise.
149 * bpf-desc.c: Likewise.
151 2019-05-21 Sudakshina Das <sudi.das@arm.com>
153 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
154 and VMSR with the new operands.
156 2019-05-21 Sudakshina Das <sudi.das@arm.com>
158 * arm-dis.c (enum mve_instructions): New enum
159 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
161 (mve_opcodes): New instructions as above.
162 (is_mve_encoding_conflict): Add cases for csinc, csinv,
164 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
166 2019-05-21 Sudakshina Das <sudi.das@arm.com>
168 * arm-dis.c (emun mve_instructions): Updated for new instructions.
169 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
170 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
171 uqshl, urshrl and urshr.
172 (is_mve_okay_in_it): Add new instructions to TRUE list.
173 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
174 (print_insn_mve): Updated to accept new %j,
175 %<bitfield>m and %<bitfield>n patterns.
177 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
179 * mips-opc.c (mips_builtin_opcodes): Change source register
182 2019-05-20 Nick Clifton <nickc@redhat.com>
184 * po/fr.po: Updated French translation.
186 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
187 Michael Collison <michael.collison@arm.com>
189 * arm-dis.c (thumb32_opcodes): Add new instructions.
190 (enum mve_instructions): Likewise.
191 (enum mve_undefined): Add new reasons.
192 (is_mve_encoding_conflict): Handle new instructions.
193 (is_mve_undefined): Likewise.
194 (is_mve_unpredictable): Likewise.
195 (print_mve_undefined): Likewise.
196 (print_mve_size): Likewise.
198 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
199 Michael Collison <michael.collison@arm.com>
201 * arm-dis.c (thumb32_opcodes): Add new instructions.
202 (enum mve_instructions): Likewise.
203 (is_mve_encoding_conflict): Handle new instructions.
204 (is_mve_undefined): Likewise.
205 (is_mve_unpredictable): Likewise.
206 (print_mve_size): Likewise.
208 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
209 Michael Collison <michael.collison@arm.com>
211 * arm-dis.c (thumb32_opcodes): Add new instructions.
212 (enum mve_instructions): Likewise.
213 (is_mve_encoding_conflict): Likewise.
214 (is_mve_unpredictable): Likewise.
215 (print_mve_size): Likewise.
217 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
218 Michael Collison <michael.collison@arm.com>
220 * arm-dis.c (thumb32_opcodes): Add new instructions.
221 (enum mve_instructions): Likewise.
222 (is_mve_encoding_conflict): Handle new instructions.
223 (is_mve_undefined): Likewise.
224 (is_mve_unpredictable): Likewise.
225 (print_mve_size): Likewise.
227 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
228 Michael Collison <michael.collison@arm.com>
230 * arm-dis.c (thumb32_opcodes): Add new instructions.
231 (enum mve_instructions): Likewise.
232 (is_mve_encoding_conflict): Handle new instructions.
233 (is_mve_undefined): Likewise.
234 (is_mve_unpredictable): Likewise.
235 (print_mve_size): Likewise.
236 (print_insn_mve): Likewise.
238 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
239 Michael Collison <michael.collison@arm.com>
241 * arm-dis.c (thumb32_opcodes): Add new instructions.
242 (print_insn_thumb32): Handle new instructions.
244 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
245 Michael Collison <michael.collison@arm.com>
247 * arm-dis.c (enum mve_instructions): Add new instructions.
248 (enum mve_undefined): Add new reasons.
249 (is_mve_encoding_conflict): Handle new instructions.
250 (is_mve_undefined): Likewise.
251 (is_mve_unpredictable): Likewise.
252 (print_mve_undefined): Likewise.
253 (print_mve_size): Likewise.
254 (print_mve_shift_n): Likewise.
255 (print_insn_mve): Likewise.
257 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
258 Michael Collison <michael.collison@arm.com>
260 * arm-dis.c (enum mve_instructions): Add new instructions.
261 (is_mve_encoding_conflict): Handle new instructions.
262 (is_mve_unpredictable): Likewise.
263 (print_mve_rotate): Likewise.
264 (print_mve_size): Likewise.
265 (print_insn_mve): Likewise.
267 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
268 Michael Collison <michael.collison@arm.com>
270 * arm-dis.c (enum mve_instructions): Add new instructions.
271 (is_mve_encoding_conflict): Handle new instructions.
272 (is_mve_unpredictable): Likewise.
273 (print_mve_size): Likewise.
274 (print_insn_mve): Likewise.
276 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
277 Michael Collison <michael.collison@arm.com>
279 * arm-dis.c (enum mve_instructions): Add new instructions.
280 (enum mve_undefined): Add new reasons.
281 (is_mve_encoding_conflict): Handle new instructions.
282 (is_mve_undefined): Likewise.
283 (is_mve_unpredictable): Likewise.
284 (print_mve_undefined): Likewise.
285 (print_mve_size): Likewise.
286 (print_insn_mve): Likewise.
288 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
289 Michael Collison <michael.collison@arm.com>
291 * arm-dis.c (enum mve_instructions): Add new instructions.
292 (is_mve_encoding_conflict): Handle new instructions.
293 (is_mve_undefined): Likewise.
294 (is_mve_unpredictable): Likewise.
295 (print_mve_size): Likewise.
296 (print_insn_mve): Likewise.
298 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
299 Michael Collison <michael.collison@arm.com>
301 * arm-dis.c (enum mve_instructions): Add new instructions.
302 (enum mve_unpredictable): Add new reasons.
303 (enum mve_undefined): Likewise.
304 (is_mve_okay_in_it): Handle new isntructions.
305 (is_mve_encoding_conflict): Likewise.
306 (is_mve_undefined): Likewise.
307 (is_mve_unpredictable): Likewise.
308 (print_mve_vmov_index): Likewise.
309 (print_simd_imm8): Likewise.
310 (print_mve_undefined): Likewise.
311 (print_mve_unpredictable): Likewise.
312 (print_mve_size): Likewise.
313 (print_insn_mve): Likewise.
315 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
316 Michael Collison <michael.collison@arm.com>
318 * arm-dis.c (enum mve_instructions): Add new instructions.
319 (enum mve_unpredictable): Add new reasons.
320 (enum mve_undefined): Likewise.
321 (is_mve_encoding_conflict): Handle new instructions.
322 (is_mve_undefined): Likewise.
323 (is_mve_unpredictable): Likewise.
324 (print_mve_undefined): Likewise.
325 (print_mve_unpredictable): Likewise.
326 (print_mve_rounding_mode): Likewise.
327 (print_mve_vcvt_size): Likewise.
328 (print_mve_size): Likewise.
329 (print_insn_mve): Likewise.
331 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
332 Michael Collison <michael.collison@arm.com>
334 * arm-dis.c (enum mve_instructions): Add new instructions.
335 (enum mve_unpredictable): Add new reasons.
336 (enum mve_undefined): Likewise.
337 (is_mve_undefined): Handle new instructions.
338 (is_mve_unpredictable): Likewise.
339 (print_mve_undefined): Likewise.
340 (print_mve_unpredictable): Likewise.
341 (print_mve_size): Likewise.
342 (print_insn_mve): Likewise.
344 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
345 Michael Collison <michael.collison@arm.com>
347 * arm-dis.c (enum mve_instructions): Add new instructions.
348 (enum mve_undefined): Add new reasons.
349 (insns): Add new instructions.
350 (is_mve_encoding_conflict):
351 (print_mve_vld_str_addr): New print function.
352 (is_mve_undefined): Handle new instructions.
353 (is_mve_unpredictable): Likewise.
354 (print_mve_undefined): Likewise.
355 (print_mve_size): Likewise.
356 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
357 (print_insn_mve): Handle new operands.
359 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
360 Michael Collison <michael.collison@arm.com>
362 * arm-dis.c (enum mve_instructions): Add new instructions.
363 (enum mve_unpredictable): Add new reasons.
364 (is_mve_encoding_conflict): Handle new instructions.
365 (is_mve_unpredictable): Likewise.
366 (mve_opcodes): Add new instructions.
367 (print_mve_unpredictable): Handle new reasons.
368 (print_mve_register_blocks): New print function.
369 (print_mve_size): Handle new instructions.
370 (print_insn_mve): Likewise.
372 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
373 Michael Collison <michael.collison@arm.com>
375 * arm-dis.c (enum mve_instructions): Add new instructions.
376 (enum mve_unpredictable): Add new reasons.
377 (enum mve_undefined): Likewise.
378 (is_mve_encoding_conflict): Handle new instructions.
379 (is_mve_undefined): Likewise.
380 (is_mve_unpredictable): Likewise.
381 (coprocessor_opcodes): Move NEON VDUP from here...
382 (neon_opcodes): ... to here.
383 (mve_opcodes): Add new instructions.
384 (print_mve_undefined): Handle new reasons.
385 (print_mve_unpredictable): Likewise.
386 (print_mve_size): Handle new instructions.
387 (print_insn_neon): Handle vdup.
388 (print_insn_mve): Handle new operands.
390 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
391 Michael Collison <michael.collison@arm.com>
393 * arm-dis.c (enum mve_instructions): Add new instructions.
394 (enum mve_unpredictable): Add new values.
395 (mve_opcodes): Add new instructions.
396 (vec_condnames): New array with vector conditions.
397 (mve_predicatenames): New array with predicate suffixes.
398 (mve_vec_sizename): New array with vector sizes.
399 (enum vpt_pred_state): New enum with vector predication states.
400 (struct vpt_block): New struct type for vpt blocks.
401 (vpt_block_state): Global struct to keep track of state.
402 (mve_extract_pred_mask): New helper function.
403 (num_instructions_vpt_block): Likewise.
404 (mark_outside_vpt_block): Likewise.
405 (mark_inside_vpt_block): Likewise.
406 (invert_next_predicate_state): Likewise.
407 (update_next_predicate_state): Likewise.
408 (update_vpt_block_state): Likewise.
409 (is_vpt_instruction): Likewise.
410 (is_mve_encoding_conflict): Add entries for new instructions.
411 (is_mve_unpredictable): Likewise.
412 (print_mve_unpredictable): Handle new cases.
413 (print_instruction_predicate): Likewise.
414 (print_mve_size): New function.
415 (print_vec_condition): New function.
416 (print_insn_mve): Handle vpt blocks and new print operands.
418 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
420 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
421 8, 14 and 15 for Armv8.1-M Mainline.
423 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
424 Michael Collison <michael.collison@arm.com>
426 * arm-dis.c (enum mve_instructions): New enum.
427 (enum mve_unpredictable): Likewise.
428 (enum mve_undefined): Likewise.
429 (struct mopcode32): New struct.
430 (is_mve_okay_in_it): New function.
431 (is_mve_architecture): Likewise.
432 (arm_decode_field): Likewise.
433 (arm_decode_field_multiple): Likewise.
434 (is_mve_encoding_conflict): Likewise.
435 (is_mve_undefined): Likewise.
436 (is_mve_unpredictable): Likewise.
437 (print_mve_undefined): Likewise.
438 (print_mve_unpredictable): Likewise.
439 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
440 (print_insn_mve): New function.
441 (print_insn_thumb32): Handle MVE architecture.
442 (select_arm_features): Force thumb for Armv8.1-m Mainline.
444 2019-05-10 Nick Clifton <nickc@redhat.com>
447 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
448 end of the table prematurely.
450 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
452 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
455 2019-05-11 Alan Modra <amodra@gmail.com>
457 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
458 when -Mraw is in effect.
460 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
462 * aarch64-dis-2.c: Regenerate.
463 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
464 (OP_SVE_BBB): New variant set.
465 (OP_SVE_DDDD): New variant set.
466 (OP_SVE_HHH): New variant set.
467 (OP_SVE_HHHU): New variant set.
468 (OP_SVE_SSS): New variant set.
469 (OP_SVE_SSSU): New variant set.
470 (OP_SVE_SHH): New variant set.
471 (OP_SVE_SBBU): New variant set.
472 (OP_SVE_DSS): New variant set.
473 (OP_SVE_DHHU): New variant set.
474 (OP_SVE_VMV_HSD_BHS): New variant set.
475 (OP_SVE_VVU_HSD_BHS): New variant set.
476 (OP_SVE_VVVU_SD_BH): New variant set.
477 (OP_SVE_VVVU_BHSD): New variant set.
478 (OP_SVE_VVV_QHD_DBS): New variant set.
479 (OP_SVE_VVV_HSD_BHS): New variant set.
480 (OP_SVE_VVV_HSD_BHS2): New variant set.
481 (OP_SVE_VVV_BHS_HSD): New variant set.
482 (OP_SVE_VV_BHS_HSD): New variant set.
483 (OP_SVE_VVV_SD): New variant set.
484 (OP_SVE_VVU_BHS_HSD): New variant set.
485 (OP_SVE_VZVV_SD): New variant set.
486 (OP_SVE_VZVV_BH): New variant set.
487 (OP_SVE_VZV_SD): New variant set.
488 (aarch64_opcode_table): Add sve2 instructions.
490 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
492 * aarch64-asm-2.c: Regenerated.
493 * aarch64-dis-2.c: Regenerated.
494 * aarch64-opc-2.c: Regenerated.
495 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
496 for SVE_SHLIMM_UNPRED_22.
497 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
498 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
501 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
503 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
504 sve_size_tsz_bhs iclass encode.
505 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
506 sve_size_tsz_bhs iclass decode.
508 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
510 * aarch64-asm-2.c: Regenerated.
511 * aarch64-dis-2.c: Regenerated.
512 * aarch64-opc-2.c: Regenerated.
513 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
514 for SVE_Zm4_11_INDEX.
515 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
516 (fields): Handle SVE_i2h field.
517 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
518 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
520 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
522 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
523 sve_shift_tsz_bhsd iclass encode.
524 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
525 sve_shift_tsz_bhsd iclass decode.
527 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
529 * aarch64-asm-2.c: Regenerated.
530 * aarch64-dis-2.c: Regenerated.
531 * aarch64-opc-2.c: Regenerated.
532 * aarch64-asm.c (aarch64_ins_sve_shrimm):
533 (aarch64_encode_variant_using_iclass): Handle
534 sve_shift_tsz_hsd iclass encode.
535 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
536 sve_shift_tsz_hsd iclass decode.
537 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
538 for SVE_SHRIMM_UNPRED_22.
539 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
540 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
543 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
545 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
546 sve_size_013 iclass encode.
547 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
548 sve_size_013 iclass decode.
550 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
552 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
553 sve_size_bh iclass encode.
554 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
555 sve_size_bh iclass decode.
557 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
559 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
560 sve_size_sd2 iclass encode.
561 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
562 sve_size_sd2 iclass decode.
563 * aarch64-opc.c (fields): Handle SVE_sz2 field.
564 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
566 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
568 * aarch64-asm-2.c: Regenerated.
569 * aarch64-dis-2.c: Regenerated.
570 * aarch64-opc-2.c: Regenerated.
571 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
573 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
574 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
576 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
578 * aarch64-asm-2.c: Regenerated.
579 * aarch64-dis-2.c: Regenerated.
580 * aarch64-opc-2.c: Regenerated.
581 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
582 for SVE_Zm3_11_INDEX.
583 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
584 (fields): Handle SVE_i3l and SVE_i3h2 fields.
585 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
587 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
589 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
591 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
592 sve_size_hsd2 iclass encode.
593 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
594 sve_size_hsd2 iclass decode.
595 * aarch64-opc.c (fields): Handle SVE_size field.
596 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
598 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
600 * aarch64-asm-2.c: Regenerated.
601 * aarch64-dis-2.c: Regenerated.
602 * aarch64-opc-2.c: Regenerated.
603 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
605 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
606 (fields): Handle SVE_rot3 field.
607 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
608 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
610 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
612 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
615 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
618 (aarch64_feature_sve2, aarch64_feature_sve2aes,
619 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
620 aarch64_feature_sve2bitperm): New feature sets.
621 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
622 for feature set addresses.
623 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
624 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
626 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
627 Faraz Shahbazker <fshahbazker@wavecomp.com>
629 * mips-dis.c (mips_calculate_combination_ases): Add ISA
630 argument and set ASE_EVA_R6 appropriately.
631 (set_default_mips_dis_options): Pass ISA to above.
632 (parse_mips_dis_option): Likewise.
633 * mips-opc.c (EVAR6): New macro.
634 (mips_builtin_opcodes): Add llwpe, scwpe.
636 2019-05-01 Sudakshina Das <sudi.das@arm.com>
638 * aarch64-asm-2.c: Regenerated.
639 * aarch64-dis-2.c: Regenerated.
640 * aarch64-opc-2.c: Regenerated.
641 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
642 AARCH64_OPND_TME_UIMM16.
643 (aarch64_print_operand): Likewise.
644 * aarch64-tbl.h (QL_IMM_NIL): New.
647 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
649 2019-04-29 John Darrington <john@darrington.wattle.id.au>
651 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
653 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
654 Faraz Shahbazker <fshahbazker@wavecomp.com>
656 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
658 2019-04-24 John Darrington <john@darrington.wattle.id.au>
660 * s12z-opc.h: Add extern "C" bracketing to help
661 users who wish to use this interface in c++ code.
663 2019-04-24 John Darrington <john@darrington.wattle.id.au>
665 * s12z-opc.c (bm_decode): Handle bit map operations with the
668 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
670 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
671 specifier. Add entries for VLDR and VSTR of system registers.
672 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
673 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
674 of %J and %K format specifier.
676 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
678 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
679 Add new entries for VSCCLRM instruction.
680 (print_insn_coprocessor): Handle new %C format control code.
682 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
684 * arm-dis.c (enum isa): New enum.
685 (struct sopcode32): New structure.
686 (coprocessor_opcodes): change type of entries to struct sopcode32 and
687 set isa field of all current entries to ANY.
688 (print_insn_coprocessor): Change type of insn to struct sopcode32.
689 Only match an entry if its isa field allows the current mode.
691 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
693 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
695 (print_insn_thumb32): Add logic to print %n CLRM register list.
697 2019-04-15 Sudakshina Das <sudi.das@arm.com>
699 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
702 2019-04-15 Sudakshina Das <sudi.das@arm.com>
704 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
705 (print_insn_thumb32): Edit the switch case for %Z.
707 2019-04-15 Sudakshina Das <sudi.das@arm.com>
709 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
711 2019-04-15 Sudakshina Das <sudi.das@arm.com>
713 * arm-dis.c (thumb32_opcodes): New instruction bfl.
715 2019-04-15 Sudakshina Das <sudi.das@arm.com>
717 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
719 2019-04-15 Sudakshina Das <sudi.das@arm.com>
721 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
722 Arm register with r13 and r15 unpredictable.
723 (thumb32_opcodes): New instructions for bfx and bflx.
725 2019-04-15 Sudakshina Das <sudi.das@arm.com>
727 * arm-dis.c (thumb32_opcodes): New instructions for bf.
729 2019-04-15 Sudakshina Das <sudi.das@arm.com>
731 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
733 2019-04-15 Sudakshina Das <sudi.das@arm.com>
735 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
737 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
739 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
741 2019-04-12 John Darrington <john@darrington.wattle.id.au>
743 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
744 "optr". ("operator" is a reserved word in c++).
746 2019-04-11 Sudakshina Das <sudi.das@arm.com>
748 * aarch64-opc.c (aarch64_print_operand): Add case for
750 (verify_constraints): Likewise.
751 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
752 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
753 to accept Rt|SP as first operand.
754 (AARCH64_OPERANDS): Add new Rt_SP.
755 * aarch64-asm-2.c: Regenerated.
756 * aarch64-dis-2.c: Regenerated.
757 * aarch64-opc-2.c: Regenerated.
759 2019-04-11 Sudakshina Das <sudi.das@arm.com>
761 * aarch64-asm-2.c: Regenerated.
762 * aarch64-dis-2.c: Likewise.
763 * aarch64-opc-2.c: Likewise.
764 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
766 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
768 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
770 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
772 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
773 * i386-init.h: Regenerated.
775 2019-04-07 Alan Modra <amodra@gmail.com>
777 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
778 op_separator to control printing of spaces, comma and parens
779 rather than need_comma, need_paren and spaces vars.
781 2019-04-07 Alan Modra <amodra@gmail.com>
784 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
785 (print_insn_neon, print_insn_arm): Likewise.
787 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
789 * i386-dis-evex.h (evex_table): Updated to support BF16
791 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
792 and EVEX_W_0F3872_P_3.
793 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
794 (cpu_flags): Add bitfield for CpuAVX512_BF16.
795 * i386-opc.h (enum): Add CpuAVX512_BF16.
796 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
797 * i386-opc.tbl: Add AVX512 BF16 instructions.
798 * i386-init.h: Regenerated.
799 * i386-tbl.h: Likewise.
801 2019-04-05 Alan Modra <amodra@gmail.com>
803 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
804 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
805 to favour printing of "-" branch hint when using the "y" bit.
806 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
808 2019-04-05 Alan Modra <amodra@gmail.com>
810 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
811 opcode until first operand is output.
813 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
816 * ppc-opc.c (valid_bo_pre_v2): Add comments.
817 (valid_bo_post_v2): Add support for 'at' branch hints.
818 (insert_bo): Only error on branch on ctr.
819 (get_bo_hint_mask): New function.
820 (insert_boe): Add new 'branch_taken' formal argument. Add support
821 for inserting 'at' branch hints.
822 (extract_boe): Add new 'branch_taken' formal argument. Add support
823 for extracting 'at' branch hints.
824 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
825 (BOE): Delete operand.
826 (BOM, BOP): New operands.
828 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
829 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
830 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
831 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
832 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
833 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
834 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
835 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
836 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
837 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
838 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
839 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
840 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
841 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
842 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
843 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
844 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
845 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
846 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
847 bttarl+>: New extended mnemonics.
849 2019-03-28 Alan Modra <amodra@gmail.com>
852 * ppc-opc.c (BTF): Define.
853 (powerpc_opcodes): Use for mtfsb*.
854 * ppc-dis.c (print_insn_powerpc): Print fields with both
855 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
857 2019-03-25 Tamar Christina <tamar.christina@arm.com>
859 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
860 (mapping_symbol_for_insn): Implement new algorithm.
861 (print_insn): Remove duplicate code.
863 2019-03-25 Tamar Christina <tamar.christina@arm.com>
865 * aarch64-dis.c (print_insn_aarch64):
868 2019-03-25 Tamar Christina <tamar.christina@arm.com>
870 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
873 2019-03-25 Tamar Christina <tamar.christina@arm.com>
875 * aarch64-dis.c (last_stop_offset): New.
876 (print_insn_aarch64): Use stop_offset.
878 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
881 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
883 * i386-init.h: Regenerated.
885 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
888 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
889 vmovdqu16, vmovdqu32 and vmovdqu64.
890 * i386-tbl.h: Regenerated.
892 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
894 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
895 from vstrszb, vstrszh, and vstrszf.
897 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
899 * s390-opc.txt: Add instruction descriptions.
901 2019-02-08 Jim Wilson <jimw@sifive.com>
903 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
906 2019-02-07 Tamar Christina <tamar.christina@arm.com>
908 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
910 2019-02-07 Tamar Christina <tamar.christina@arm.com>
913 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
914 * aarch64-opc.c (verify_elem_sd): New.
915 (fields): Add FLD_sz entr.
916 * aarch64-tbl.h (_SIMD_INSN): New.
917 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
918 fmulx scalar and vector by element isns.
920 2019-02-07 Nick Clifton <nickc@redhat.com>
922 * po/sv.po: Updated Swedish translation.
924 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
926 * s390-mkopc.c (main): Accept arch13 as cpu string.
927 * s390-opc.c: Add new instruction formats and instruction opcode
929 * s390-opc.txt: Add new arch13 instructions.
931 2019-01-25 Sudakshina Das <sudi.das@arm.com>
933 * aarch64-tbl.h (QL_LDST_AT): Update macro.
934 (aarch64_opcode): Change encoding for stg, stzg
936 * aarch64-asm-2.c: Regenerated.
937 * aarch64-dis-2.c: Regenerated.
938 * aarch64-opc-2.c: Regenerated.
940 2019-01-25 Sudakshina Das <sudi.das@arm.com>
942 * aarch64-asm-2.c: Regenerated.
943 * aarch64-dis-2.c: Likewise.
944 * aarch64-opc-2.c: Likewise.
945 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
947 2019-01-25 Sudakshina Das <sudi.das@arm.com>
948 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
950 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
951 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
952 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
953 * aarch64-dis.h (ext_addr_simple_2): Likewise.
954 * aarch64-opc.c (operand_general_constraint_met_p): Remove
955 case for ldstgv_indexed.
956 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
957 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
958 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
959 * aarch64-asm-2.c: Regenerated.
960 * aarch64-dis-2.c: Regenerated.
961 * aarch64-opc-2.c: Regenerated.
963 2019-01-23 Nick Clifton <nickc@redhat.com>
965 * po/pt_BR.po: Updated Brazilian Portuguese translation.
967 2019-01-21 Nick Clifton <nickc@redhat.com>
969 * po/de.po: Updated German translation.
970 * po/uk.po: Updated Ukranian translation.
972 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
973 * mips-dis.c (mips_arch_choices): Fix typo in
974 gs464, gs464e and gs264e descriptors.
976 2019-01-19 Nick Clifton <nickc@redhat.com>
978 * configure: Regenerate.
979 * po/opcodes.pot: Regenerate.
981 2018-06-24 Nick Clifton <nickc@redhat.com>
985 2019-01-09 John Darrington <john@darrington.wattle.id.au>
987 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
989 -dis.c (opr_emit_disassembly): Do not omit an index if it is
992 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
994 * configure: Regenerate.
996 2019-01-07 Alan Modra <amodra@gmail.com>
998 * configure: Regenerate.
999 * po/POTFILES.in: Regenerate.
1001 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1003 * s12z-opc.c: New file.
1004 * s12z-opc.h: New file.
1005 * s12z-dis.c: Removed all code not directly related to display
1006 of instructions. Used the interface provided by the new files
1008 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1009 * Makefile.in: Regenerate.
1010 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1011 * configure: Regenerate.
1013 2019-01-01 Alan Modra <amodra@gmail.com>
1015 Update year range in copyright notice of all files.
1017 For older changes see ChangeLog-2018
1019 Copyright (C) 2019 Free Software Foundation, Inc.
1021 Copying and distribution of this file, with or without modification,
1022 are permitted in any medium without royalty provided the copyright
1023 notice and this notice are preserved.
1029 version-control: never