1 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
3 * micromips-opc.c (WR_s): Delete.
5 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
7 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
9 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
10 (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
11 (mips_builtin_opcodes): Use the new position-based read-write flags
12 instead of field-based ones. Use UDI for "udi..." instructions.
13 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
15 (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
16 (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
17 (WR_SP, RD_16): New macros.
18 (RD_SP): Redefine as an INSN2_* flag.
19 (MOD_SP): Redefine in terms of RD_SP and WR_SP.
20 (mips16_opcodes): Use the new position-based read-write flags
21 instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
23 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
25 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
26 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
27 (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
28 (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
29 (micromips_opcodes): Use the new position-based read-write flags
30 instead of field-based ones.
31 * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
32 (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
35 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
37 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
38 (WR_SP): Replace with...
40 (mips16_opcodes): Update accordingly.
41 * mips-dis.c (print_insn_mips16): Likewise.
43 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
45 * mips16-opc.c (mips16_opcodes): Reformat.
47 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
49 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
50 for operands that are hard-coded to $0.
51 * micromips-opc.c (micromips_opcodes): Likewise.
53 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
55 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
56 for the single-operand forms of JALR and JALR.HB.
57 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
60 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
62 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
63 instructions. Fix them to use WR_MACC instead of WR_CC and
66 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
68 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
70 2013-07-29 Peter Bergner <bergner@vnet.ibm.com>
72 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
74 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
75 Alexander Ivchenko <alexander.ivchenko@intel.com>
76 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
77 Sergey Lega <sergey.s.lega@intel.com>
78 Anna Tikhonova <anna.tikhonova@intel.com>
79 Ilya Tocar <ilya.tocar@intel.com>
80 Andrey Turetskiy <andrey.turetskiy@intel.com>
81 Ilya Verbin <ilya.verbin@intel.com>
82 Kirill Yukhin <kirill.yukhin@intel.com>
83 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
85 * i386-dis-evex.h: New.
86 * i386-dis.c (OP_Rounding): New.
93 (EXEvexHalfBcstXmmq): New.
105 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
106 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
107 evex_rounding_mode, evex_sae_mode, mask_mode.
108 (USE_EVEX_TABLE): New.
111 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
113 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
114 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
115 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
116 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
117 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
118 MOD_EVEX_0F38C7_REG_6.
119 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
120 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
121 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
122 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
123 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
124 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
125 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
126 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
127 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
128 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
129 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
130 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
131 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
132 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
133 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
134 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
135 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
136 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
137 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
138 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
139 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
140 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
141 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
142 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
143 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
144 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
145 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
146 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
147 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
148 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
149 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
150 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
151 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
152 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
153 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
154 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
155 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
156 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
157 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
158 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
159 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
160 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
161 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
162 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
163 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
164 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
165 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
166 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
167 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
168 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
169 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
170 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
171 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
172 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
173 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
174 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
175 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
176 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
177 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
178 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
179 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
180 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
181 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
182 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
183 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
184 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
185 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
186 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
187 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
188 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
189 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
190 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
191 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
192 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
193 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
194 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
196 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
197 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
198 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
199 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
200 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
201 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
202 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
203 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
204 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
205 VEX_W_0F3A32_P_2_LEN_0.
206 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
207 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
208 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
209 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
210 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
211 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
212 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
213 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
214 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
215 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
216 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
217 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
218 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
219 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
220 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
221 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
222 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
223 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
224 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
225 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
226 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
227 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
228 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
229 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
230 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
231 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
232 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
233 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
234 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
235 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
236 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
237 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
238 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
239 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
240 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
241 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
242 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
243 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
244 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
245 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
246 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
247 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
248 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
249 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
250 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
251 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
252 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
253 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
254 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
255 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
256 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
257 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
258 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
259 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
260 (struct vex): Add fields evex, r, v, mask_register_specifier,
262 (intel_names_xmm): Add upper 16 registers.
263 (att_names_xmm): Ditto.
264 (intel_names_ymm): Ditto.
265 (att_names_ymm): Ditto.
267 (intel_names_zmm): Ditto.
268 (att_names_zmm): Ditto.
270 (intel_names_mask): Ditto.
271 (att_names_mask): Ditto.
272 (names_rounding): Ditto.
273 (names_broadcast): Ditto.
274 (x86_64_table): Add escape to evex-table.
275 (reg_table): Include reg_table evex-entries from
276 i386-dis-evex.h. Fix prefetchwt1 instruction.
277 (prefix_table): Add entries for new instructions.
279 (vex_len_table): Ditto.
280 (vex_w_table): Ditto.
282 (get_valid_dis386): Properly handle new instructions.
283 (print_insn): Handle zmm and mask registers, print mask operand.
284 (intel_operand_size): Support EVEX, new modes and sizes.
285 (OP_E_register): Handle new modes.
286 (OP_E_memory): Ditto.
291 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
292 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
293 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
294 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
295 CpuAVX512PF and CpuVREX.
296 (operand_type_init): Add OPERAND_TYPE_REGZMM,
297 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
298 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
299 StaticRounding, SAE, Disp8MemShift, NoDefMask.
300 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
301 * i386-init.h: Regenerate.
302 * i386-opc.h (CpuAVX512F): New.
307 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
308 cpuavx512pf and cpuvrex fields.
309 (VecSIB): Add VecSIB512.
314 (StaticRounding): New.
316 (Disp8MemShift): New.
318 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
319 staticrounding, sae, disp8memshift and nodefmask.
323 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
326 * i386-opc.tbl: Add AVX512 instructions.
327 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
328 registers, mask registers.
329 * i386-tbl.h: Regenerate.
331 2013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
334 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
335 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
337 2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
339 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
340 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
342 (prefix_table): Updated.
343 (three_byte_table): Likewise.
344 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
345 (cpu_flags): Add CpuSHA.
346 (i386_cpu_flags): Add cpusha.
347 * i386-init.h: Regenerate.
348 * i386-opc.h (CpuSHA): New.
349 (CpuUnused): Restored.
350 (i386_cpu_flags): Add cpusha.
351 * i386-opc.tbl: Add SHA instructions.
352 * i386-tbl.h: Regenerate.
354 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
355 Kirill Yukhin <kirill.yukhin@intel.com>
356 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
358 * i386-dis.c (BND_Fixup): New.
365 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
367 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
368 (dis tables): Replace XX with BND for near branch and call
370 (prefix_table): Add new entries.
371 (mod_table): Likewise.
373 (intel_names_bnd): New.
374 (att_names_bnd): New.
376 (prefix_name): Handle BND_PREFIX.
377 (print_insn): Initialize names_bnd.
378 (intel_operand_size): Handle new modes.
379 (OP_E_register): Likewise.
380 (OP_E_memory): Likewise.
382 * i386-gen.c (cpu_flag_init): Add CpuMPX.
383 (cpu_flags): Add CpuMPX.
384 (operand_type_init): Add RegBND.
385 (opcode_modifiers): Add BNDPrefixOk.
386 (operand_types): Add RegBND.
387 * i386-init.h: Regenerate.
388 * i386-opc.h (CpuMPX): New.
389 (CpuUnused): Comment out.
390 (i386_cpu_flags): Add cpumpx.
392 (i386_opcode_modifier): Add bndprefixok.
394 (i386_operand_type): Add regbnd.
395 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
396 Add MPX instructions and bnd prefix.
397 * i386-reg.tbl: Add bnd0-bnd3 registers.
398 * i386-tbl.h: Regenerate.
400 2013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
402 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
405 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
407 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
409 * Makefile.in: Regenerate.
410 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
411 all fields. Reformat.
413 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
415 * mips16-opc.c: Include mips-formats.h.
416 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
418 (decode_mips16_operand): New function.
419 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
420 (print_insn_arg): Handle OP_ENTRY_EXIT list.
421 Abort for OP_SAVE_RESTORE_LIST.
422 (print_mips16_insn_arg): Change interface. Use mips_operand
423 structures. Delete GET_OP_S. Move GET_OP definition to...
424 (print_insn_mips16): ...here. Call init_print_arg_state.
425 Update the call to print_mips16_insn_arg.
427 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
429 * mips-formats.h: New file.
430 * mips-opc.c: Include mips-formats.h.
431 (reg_0_map): New static array.
432 (decode_mips_operand): New function.
433 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
434 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
435 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
436 (int_c_map): New static arrays.
437 (decode_micromips_operand): New function.
438 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
439 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
440 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
441 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
442 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
443 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
444 (micromips_imm_b_map, micromips_imm_c_map): Delete.
445 (print_reg): New function.
446 (mips_print_arg_state): New structure.
447 (init_print_arg_state, print_insn_arg): New functions.
448 (print_insn_args): Change interface and use mips_operand structures.
449 Delete GET_OP_S. Move GET_OP definition to...
450 (print_insn_mips): ...here. Update the call to print_insn_args.
451 (print_insn_micromips): Use print_insn_args.
453 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
455 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
458 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
460 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
461 ADDA.S, MULA.S and SUBA.S.
463 2013-07-08 H.J. Lu <hongjiu.lu@intel.com>
466 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
467 * i386-tbl.h: Regenerated.
469 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
471 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
472 and SD A(B) macros up.
473 * micromips-opc.c (micromips_opcodes): Likewise.
475 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
477 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
480 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
482 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
483 MDMX-like instructions.
484 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
485 printing "Q" operands for INSN_5400 instructions.
487 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
489 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
491 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
494 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
496 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
498 * mips16-opc.c (mips16_opcodes): Likewise.
499 * micromips-opc.c (micromips_opcodes): Likewise.
500 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
501 (print_insn_mips16): Handle "+i".
502 (print_insn_micromips): Likewise. Conditionally preserve the
503 ISA bit for "a" but not for "+i".
505 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
507 * micromips-opc.c (WR_mhi): Rename to..
509 (micromips_opcodes): Update "movep" entry accordingly. Replace
511 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
512 (micromips_to_32_reg_h_map1): ...this.
513 (micromips_to_32_reg_i_map): Rename to...
514 (micromips_to_32_reg_h_map2): ...this.
515 (print_micromips_insn): Remove "mi" case. Print both registers
516 in the pair for "mh".
518 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
520 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
521 * micromips-opc.c (micromips_opcodes): Likewise.
522 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
523 and "+T" handling. Check for a "0" suffix when deciding whether to
524 use coprocessor 0 names. In that case, also check for ",H" selectors.
526 2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
528 * s390-opc.c (J12_12, J24_24): New macros.
529 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
530 (MASK_MII_UPI): Rename to MASK_MII_UPP.
531 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
533 2013-07-04 Alan Modra <amodra@gmail.com>
535 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
537 2013-06-26 Nick Clifton <nickc@redhat.com>
539 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
540 field when checking for type 2 nop.
541 * rx-decode.c: Regenerate.
543 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
545 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
548 2013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
550 * mips-dis.c (is_mips16_plt_tail): New function.
551 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
553 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
555 2013-06-21 DJ Delorie <dj@redhat.com>
557 * msp430-decode.opc: New.
558 * msp430-decode.c: New/generated.
559 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
560 (MAINTAINER_CLEANFILES): Likewise.
561 Add rule to build msp430-decode.c frommsp430decode.opc
562 using the opc2c program.
563 * Makefile.in: Regenerate.
564 * configure.in: Add msp430-decode.lo to msp430 architecture files.
565 * configure: Regenerate.
567 2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
569 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
570 (SYMTAB_AVAILABLE): Removed.
571 (#include "elf/aarch64.h): Ditto.
573 2013-06-17 Catherine Moore <clm@codesourcery.com>
574 Maciej W. Rozycki <macro@codesourcery.com>
575 Chao-Ying Fu <fu@mips.com>
577 * micromips-opc.c (EVA): Define.
579 (micromips_opcodes): Add EVA opcodes.
580 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
581 (print_insn_args): Handle EVA offsets.
582 (print_insn_micromips): Likewise.
583 * mips-opc.c (EVA): Define.
585 (mips_builtin_opcodes): Add EVA opcodes.
587 2013-06-17 Alan Modra <amodra@gmail.com>
589 * Makefile.am (mips-opc.lo): Add rules to create automatic
590 dependency files. Pass archdefs.
591 (micromips-opc.lo, mips16-opc.lo): Likewise.
592 * Makefile.in: Regenerate.
594 2013-06-14 DJ Delorie <dj@redhat.com>
596 * rx-decode.opc (rx_decode_opcode): Bit operations on
597 registers are 32-bit operations, not 8-bit operations.
598 * rx-decode.c: Regenerate.
600 2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
602 * micromips-opc.c (IVIRT): New define.
603 (IVIRT64): New define.
604 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
605 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
607 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
608 dmtgc0 to print cp0 names.
610 2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
612 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
615 2013-06-08 Catherine Moore <clm@codesourcery.com>
616 Richard Sandiford <rdsandiford@googlemail.com>
618 * micromips-opc.c (D32, D33, MC): Update definitions.
619 (micromips_opcodes): Initialize ase field.
620 * mips-dis.c (mips_arch_choice): Add ase field.
621 (mips_arch_choices): Initialize ase field.
622 (set_default_mips_dis_options): Declare and setup mips_ase.
623 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
624 MT32, MC): Update definitions.
625 (mips_builtin_opcodes): Initialize ase field.
627 2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
629 * s390-opc.txt (flogr): Require a register pair destination.
631 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
633 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
636 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
638 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
640 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
642 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
643 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
644 XLS_MASK, PPCVSX2): New defines.
645 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
646 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
647 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
648 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
649 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
650 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
651 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
652 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
653 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
654 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
655 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
656 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
657 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
658 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
659 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
660 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
661 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
662 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
663 <lxvx, stxvx>: New extended mnemonics.
665 2013-05-17 Alan Modra <amodra@gmail.com>
667 * ia64-raw.tbl: Replace non-ASCII char.
668 * ia64-waw.tbl: Likewise.
669 * ia64-asmtab.c: Regenerate.
671 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
673 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
674 * i386-init.h: Regenerated.
676 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
678 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
679 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
680 check from [0, 255] to [-128, 255].
682 2013-05-09 Andrew Pinski <apinski@cavium.com>
684 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
685 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
686 (parse_mips_dis_option): Handle the virt option.
687 (print_insn_args): Handle "+J".
688 (print_mips_disassembler_options): Print out message about virt64.
689 * mips-opc.c (IVIRT): New define.
690 (IVIRT64): New define.
691 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
692 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
693 Move rfe to the bottom as it conflicts with tlbgp.
695 2013-05-09 Alan Modra <amodra@gmail.com>
697 * ppc-opc.c (extract_vlesi): Properly sign extend.
698 (extract_vlensi): Likewise. Comment reason for setting invalid.
700 2013-05-02 Nick Clifton <nickc@redhat.com>
702 * msp430-dis.c: Add support for MSP430X instructions.
704 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
706 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
709 2013-04-17 Wei-chen Wang <cole945@gmail.com>
712 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
714 (hash_insns_list): Likewise.
716 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
718 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
721 2013-04-08 Jan Beulich <jbeulich@suse.com>
723 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
724 * i386-tbl.h: Re-generate.
726 2013-04-06 David S. Miller <davem@davemloft.net>
728 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
729 of an opcode, prefer the one with F_PREFERRED set.
730 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
731 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
732 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
733 mark existing mnenomics as aliases. Add "cc" suffix to edge
734 instructions generating condition codes, mark existing mnenomics
735 as aliases. Add "fp" prefix to VIS compare instructions, mark
736 existing mnenomics as aliases.
738 2013-04-03 Nick Clifton <nickc@redhat.com>
740 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
741 destination address by subtracting the operand from the current
743 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
744 a positive value in the insn.
745 (extract_u16_loop): Do not negate the returned value.
746 (D16_LOOP): Add V850_INVERSE_PCREL flag.
748 (ceilf.sw): Remove duplicate entry.
749 (cvtf.hs): New entry.
755 (maddf.s): Restrict to E3V5 architectures.
757 (nmaddf.s): Likewise.
758 (nmsubf.s): Likewise.
760 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
762 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
764 (print_insn): Pass sizeflag to get_sib.
766 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
769 * tic6x-dis.c: Add support for displaying 16-bit insns.
771 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
774 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
775 individual msb and lsb halves in src1 & src2 fields. Discard the
776 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
777 follow what Ti SDK does in that case as any value in the src1
778 field yields the same output with SDK disassembler.
780 2013-03-12 Michael Eager <eager@eagercon.com>
782 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
784 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
786 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
788 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
790 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
792 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
794 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
796 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
798 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
799 (thumb32_opcodes): Likewise.
800 (print_insn_thumb32): Handle 'S' control char.
802 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
804 * lm32-desc.c: Regenerate.
806 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
808 * i386-reg.tbl (riz): Add RegRex64.
809 * i386-tbl.h: Regenerated.
811 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
813 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
814 (aarch64_feature_crc): New static.
816 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
817 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
818 * aarch64-asm-2.c: Re-generate.
819 * aarch64-dis-2.c: Ditto.
820 * aarch64-opc-2.c: Ditto.
822 2013-02-27 Alan Modra <amodra@gmail.com>
824 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
825 * rl78-decode.c: Regenerate.
827 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
829 * rl78-decode.opc: Fix encoding of DIVWU insn.
830 * rl78-decode.c: Regenerate.
832 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
835 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
837 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
838 (cpu_flags): Add CpuSMAP.
840 * i386-opc.h (CpuSMAP): New.
841 (i386_cpu_flags): Add cpusmap.
843 * i386-opc.tbl: Add clac and stac.
845 * i386-init.h: Regenerated.
846 * i386-tbl.h: Likewise.
848 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
850 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
851 which also makes the disassembler output be in little
852 endian like it should be.
854 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
856 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
858 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
860 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
862 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
863 section disassembled.
865 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
867 * arm-dis.c: Update strht pattern.
869 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
871 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
872 single-float. Disable ll, lld, sc and scd for EE. Disable the
873 trunc.w.s macro for EE.
875 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
876 Andrew Jenner <andrew@codesourcery.com>
878 Based on patches from Altera Corporation.
880 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
882 * Makefile.in: Regenerated.
883 * configure.in: Add case for bfd_nios2_arch.
884 * configure: Regenerated.
885 * disassemble.c (ARCH_nios2): Define.
886 (disassembler): Add case for bfd_arch_nios2.
887 * nios2-dis.c: New file.
888 * nios2-opc.c: New file.
890 2013-02-04 Alan Modra <amodra@gmail.com>
892 * po/POTFILES.in: Regenerate.
893 * rl78-decode.c: Regenerate.
894 * rx-decode.c: Regenerate.
896 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
898 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
899 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
900 * aarch64-asm.c (convert_xtl_to_shll): New function.
901 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
902 calling convert_xtl_to_shll.
903 * aarch64-dis.c (convert_shll_to_xtl): New function.
904 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
905 calling convert_shll_to_xtl.
906 * aarch64-gen.c: Update copyright year.
907 * aarch64-asm-2.c: Re-generate.
908 * aarch64-dis-2.c: Re-generate.
909 * aarch64-opc-2.c: Re-generate.
911 2013-01-24 Nick Clifton <nickc@redhat.com>
913 * v850-dis.c: Add support for e3v5 architecture.
914 * v850-opc.c: Likewise.
916 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
918 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
919 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
920 * aarch64-opc.c (operand_general_constraint_met_p): For
921 AARCH64_MOD_LSL, move the range check on the shift amount before the
922 alignment check; change to call set_sft_amount_out_of_range_error
923 instead of set_imm_out_of_range_error.
924 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
925 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
926 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
929 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
931 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
933 * i386-init.h: Regenerated.
934 * i386-tbl.h: Likewise.
936 2013-01-15 Nick Clifton <nickc@redhat.com>
938 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
940 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
942 2013-01-14 Will Newton <will.newton@imgtec.com>
944 * metag-dis.c (REG_WIDTH): Increase to 64.
946 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
948 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
949 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
950 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
952 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
953 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
954 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
955 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
957 2013-01-10 Will Newton <will.newton@imgtec.com>
959 * Makefile.am: Add Meta.
960 * configure.in: Add Meta.
961 * disassemble.c: Add Meta support.
962 * metag-dis.c: New file.
963 * Makefile.in: Regenerate.
964 * configure: Regenerate.
966 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
968 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
969 (match_opcode): Rename to cr16_match_opcode.
971 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
973 * mips-dis.c: Add names for CP0 registers of r5900.
974 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
975 instructions sq and lq.
976 Add support for MIPS r5900 CPU.
977 Add support for 128 bit MMI (Multimedia Instructions).
978 Add support for EE instructions (Emotion Engine).
979 Disable unsupported floating point instructions (64 bit and
980 undefined compare operations).
981 Enable instructions of MIPS ISA IV which are supported by r5900.
982 Disable 64 bit co processor instructions.
983 Disable 64 bit multiplication and division instructions.
984 Disable instructions for co-processor 2 and 3, because these are
985 not supported (preparation for later VU0 support (Vector Unit)).
986 Disable cvt.w.s because this behaves like trunc.w.s and the
987 correct execution can't be ensured on r5900.
988 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
989 will confuse less developers and compilers.
991 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
993 * aarch64-opc.c (aarch64_print_operand): Change to print
994 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
996 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
997 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1000 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1002 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1003 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1005 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1007 * i386-gen.c (process_copyright): Update copyright year to 2013.
1009 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1011 * cr16-dis.c (match_opcode,make_instruction): Remove static
1013 (dwordU,wordU): Moved typedefs to opcode/cr16.h
1014 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1016 For older changes see ChangeLog-2012
1018 Copyright (C) 2013 Free Software Foundation, Inc.
1020 Copying and distribution of this file, with or without modification,
1021 are permitted in any medium without royalty provided the copyright
1022 notice and this notice are preserved.
1028 version-control: never