1 2013-06-08 Catherine Moore <clm@codesourcery.com>
2 Richard Sandiford <rdsandiford@googlemail.com>
4 * micromips-opc.c (D32, D33, MC): Update definitions.
5 (micromips_opcodes): Initialize ase field.
6 * mips-dis.c (mips_arch_choice): Add ase field.
7 (mips_arch_choices): Initialize ase field.
8 (set_default_mips_dis_options): Declare and setup mips_ase.
9 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
10 MT32, MC): Update definitions.
11 (mips_builtin_opcodes): Initialize ase field.
13 2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
15 * s390-opc.txt (flogr): Require a register pair destination.
17 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
19 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
22 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
24 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
26 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
28 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
29 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
30 XLS_MASK, PPCVSX2): New defines.
31 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
32 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
33 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
34 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
35 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
36 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
37 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
38 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
39 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
40 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
41 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
42 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
43 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
44 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
45 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
46 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
47 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
48 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
49 <lxvx, stxvx>: New extended mnemonics.
51 2013-05-17 Alan Modra <amodra@gmail.com>
53 * ia64-raw.tbl: Replace non-ASCII char.
54 * ia64-waw.tbl: Likewise.
55 * ia64-asmtab.c: Regenerate.
57 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
59 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
60 * i386-init.h: Regenerated.
62 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
64 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
65 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
66 check from [0, 255] to [-128, 255].
68 2013-05-09 Andrew Pinski <apinski@cavium.com>
70 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
71 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
72 (parse_mips_dis_option): Handle the virt option.
73 (print_insn_args): Handle "+J".
74 (print_mips_disassembler_options): Print out message about virt64.
75 * mips-opc.c (IVIRT): New define.
76 (IVIRT64): New define.
77 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
78 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
79 Move rfe to the bottom as it conflicts with tlbgp.
81 2013-05-09 Alan Modra <amodra@gmail.com>
83 * ppc-opc.c (extract_vlesi): Properly sign extend.
84 (extract_vlensi): Likewise. Comment reason for setting invalid.
86 2013-05-02 Nick Clifton <nickc@redhat.com>
88 * msp430-dis.c: Add support for MSP430X instructions.
90 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
92 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
95 2013-04-17 Wei-chen Wang <cole945@gmail.com>
98 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
100 (hash_insns_list): Likewise.
102 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
104 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
107 2013-04-08 Jan Beulich <jbeulich@suse.com>
109 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
110 * i386-tbl.h: Re-generate.
112 2013-04-06 David S. Miller <davem@davemloft.net>
114 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
115 of an opcode, prefer the one with F_PREFERRED set.
116 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
117 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
118 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
119 mark existing mnenomics as aliases. Add "cc" suffix to edge
120 instructions generating condition codes, mark existing mnenomics
121 as aliases. Add "fp" prefix to VIS compare instructions, mark
122 existing mnenomics as aliases.
124 2013-04-03 Nick Clifton <nickc@redhat.com>
126 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
127 destination address by subtracting the operand from the current
129 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
130 a positive value in the insn.
131 (extract_u16_loop): Do not negate the returned value.
132 (D16_LOOP): Add V850_INVERSE_PCREL flag.
134 (ceilf.sw): Remove duplicate entry.
135 (cvtf.hs): New entry.
141 (maddf.s): Restrict to E3V5 architectures.
143 (nmaddf.s): Likewise.
144 (nmsubf.s): Likewise.
146 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
148 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
150 (print_insn): Pass sizeflag to get_sib.
152 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
155 * tic6x-dis.c: Add support for displaying 16-bit insns.
157 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
160 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
161 individual msb and lsb halves in src1 & src2 fields. Discard the
162 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
163 follow what Ti SDK does in that case as any value in the src1
164 field yields the same output with SDK disassembler.
166 2013-03-12 Michael Eager <eager@eagercon.com>
168 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
170 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
172 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
174 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
176 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
178 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
180 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
182 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
184 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
185 (thumb32_opcodes): Likewise.
186 (print_insn_thumb32): Handle 'S' control char.
188 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
190 * lm32-desc.c: Regenerate.
192 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
194 * i386-reg.tbl (riz): Add RegRex64.
195 * i386-tbl.h: Regenerated.
197 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
199 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
200 (aarch64_feature_crc): New static.
202 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
203 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
204 * aarch64-asm-2.c: Re-generate.
205 * aarch64-dis-2.c: Ditto.
206 * aarch64-opc-2.c: Ditto.
208 2013-02-27 Alan Modra <amodra@gmail.com>
210 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
211 * rl78-decode.c: Regenerate.
213 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
215 * rl78-decode.opc: Fix encoding of DIVWU insn.
216 * rl78-decode.c: Regenerate.
218 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
221 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
223 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
224 (cpu_flags): Add CpuSMAP.
226 * i386-opc.h (CpuSMAP): New.
227 (i386_cpu_flags): Add cpusmap.
229 * i386-opc.tbl: Add clac and stac.
231 * i386-init.h: Regenerated.
232 * i386-tbl.h: Likewise.
234 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
236 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
237 which also makes the disassembler output be in little
238 endian like it should be.
240 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
242 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
244 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
246 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
248 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
249 section disassembled.
251 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
253 * arm-dis.c: Update strht pattern.
255 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
257 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
258 single-float. Disable ll, lld, sc and scd for EE. Disable the
259 trunc.w.s macro for EE.
261 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
262 Andrew Jenner <andrew@codesourcery.com>
264 Based on patches from Altera Corporation.
266 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
268 * Makefile.in: Regenerated.
269 * configure.in: Add case for bfd_nios2_arch.
270 * configure: Regenerated.
271 * disassemble.c (ARCH_nios2): Define.
272 (disassembler): Add case for bfd_arch_nios2.
273 * nios2-dis.c: New file.
274 * nios2-opc.c: New file.
276 2013-02-04 Alan Modra <amodra@gmail.com>
278 * po/POTFILES.in: Regenerate.
279 * rl78-decode.c: Regenerate.
280 * rx-decode.c: Regenerate.
282 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
284 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
285 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
286 * aarch64-asm.c (convert_xtl_to_shll): New function.
287 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
288 calling convert_xtl_to_shll.
289 * aarch64-dis.c (convert_shll_to_xtl): New function.
290 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
291 calling convert_shll_to_xtl.
292 * aarch64-gen.c: Update copyright year.
293 * aarch64-asm-2.c: Re-generate.
294 * aarch64-dis-2.c: Re-generate.
295 * aarch64-opc-2.c: Re-generate.
297 2013-01-24 Nick Clifton <nickc@redhat.com>
299 * v850-dis.c: Add support for e3v5 architecture.
300 * v850-opc.c: Likewise.
302 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
304 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
305 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
306 * aarch64-opc.c (operand_general_constraint_met_p): For
307 AARCH64_MOD_LSL, move the range check on the shift amount before the
308 alignment check; change to call set_sft_amount_out_of_range_error
309 instead of set_imm_out_of_range_error.
310 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
311 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
312 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
315 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
317 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
319 * i386-init.h: Regenerated.
320 * i386-tbl.h: Likewise.
322 2013-01-15 Nick Clifton <nickc@redhat.com>
324 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
326 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
328 2013-01-14 Will Newton <will.newton@imgtec.com>
330 * metag-dis.c (REG_WIDTH): Increase to 64.
332 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
334 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
335 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
336 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
338 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
339 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
340 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
341 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
343 2013-01-10 Will Newton <will.newton@imgtec.com>
345 * Makefile.am: Add Meta.
346 * configure.in: Add Meta.
347 * disassemble.c: Add Meta support.
348 * metag-dis.c: New file.
349 * Makefile.in: Regenerate.
350 * configure: Regenerate.
352 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
354 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
355 (match_opcode): Rename to cr16_match_opcode.
357 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
359 * mips-dis.c: Add names for CP0 registers of r5900.
360 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
361 instructions sq and lq.
362 Add support for MIPS r5900 CPU.
363 Add support for 128 bit MMI (Multimedia Instructions).
364 Add support for EE instructions (Emotion Engine).
365 Disable unsupported floating point instructions (64 bit and
366 undefined compare operations).
367 Enable instructions of MIPS ISA IV which are supported by r5900.
368 Disable 64 bit co processor instructions.
369 Disable 64 bit multiplication and division instructions.
370 Disable instructions for co-processor 2 and 3, because these are
371 not supported (preparation for later VU0 support (Vector Unit)).
372 Disable cvt.w.s because this behaves like trunc.w.s and the
373 correct execution can't be ensured on r5900.
374 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
375 will confuse less developers and compilers.
377 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
379 * aarch64-opc.c (aarch64_print_operand): Change to print
380 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
382 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
383 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
386 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
388 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
389 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
391 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
393 * i386-gen.c (process_copyright): Update copyright year to 2013.
395 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
397 * cr16-dis.c (match_opcode,make_instruction): Remove static
399 (dwordU,wordU): Moved typedefs to opcode/cr16.h
400 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
402 For older changes see ChangeLog-2012
404 Copyright (C) 2013 Free Software Foundation, Inc.
406 Copying and distribution of this file, with or without modification,
407 are permitted in any medium without royalty provided the copyright
408 notice and this notice are preserved.
414 version-control: never