1 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
3 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
4 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
5 check from [0, 255] to [-128, 255].
7 2013-05-09 Andrew Pinski <apinski@cavium.com>
9 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
10 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
11 (parse_mips_dis_option): Handle the virt option.
12 (print_insn_args): Handle "+J".
13 (print_mips_disassembler_options): Print out message about virt64.
14 * mips-opc.c (IVIRT): New define.
15 (IVIRT64): New define.
16 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
17 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
18 Move rfe to the bottom as it conflicts with tlbgp.
20 2013-05-09 Alan Modra <amodra@gmail.com>
22 * ppc-opc.c (extract_vlesi): Properly sign extend.
23 (extract_vlensi): Likewise. Comment reason for setting invalid.
25 2013-05-02 Nick Clifton <nickc@redhat.com>
27 * msp430-dis.c: Add support for MSP430X instructions.
29 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
31 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
34 2013-04-17 Wei-chen Wang <cole945@gmail.com>
37 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
39 (hash_insns_list): Likewise.
41 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
43 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
46 2013-04-08 Jan Beulich <jbeulich@suse.com>
48 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
49 * i386-tbl.h: Re-generate.
51 2013-04-06 David S. Miller <davem@davemloft.net>
53 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
54 of an opcode, prefer the one with F_PREFERRED set.
55 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
56 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
57 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
58 mark existing mnenomics as aliases. Add "cc" suffix to edge
59 instructions generating condition codes, mark existing mnenomics
60 as aliases. Add "fp" prefix to VIS compare instructions, mark
61 existing mnenomics as aliases.
63 2013-04-03 Nick Clifton <nickc@redhat.com>
65 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
66 destination address by subtracting the operand from the current
68 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
69 a positive value in the insn.
70 (extract_u16_loop): Do not negate the returned value.
71 (D16_LOOP): Add V850_INVERSE_PCREL flag.
73 (ceilf.sw): Remove duplicate entry.
80 (maddf.s): Restrict to E3V5 architectures.
85 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
87 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
89 (print_insn): Pass sizeflag to get_sib.
91 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
94 * tic6x-dis.c: Add support for displaying 16-bit insns.
96 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
99 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
100 individual msb and lsb halves in src1 & src2 fields. Discard the
101 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
102 follow what Ti SDK does in that case as any value in the src1
103 field yields the same output with SDK disassembler.
105 2013-03-12 Michael Eager <eager@eagercon.com>
107 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
109 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
111 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
113 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
115 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
117 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
119 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
121 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
123 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
124 (thumb32_opcodes): Likewise.
125 (print_insn_thumb32): Handle 'S' control char.
127 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
129 * lm32-desc.c: Regenerate.
131 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
133 * i386-reg.tbl (riz): Add RegRex64.
134 * i386-tbl.h: Regenerated.
136 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
138 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
139 (aarch64_feature_crc): New static.
141 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
142 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
143 * aarch64-asm-2.c: Re-generate.
144 * aarch64-dis-2.c: Ditto.
145 * aarch64-opc-2.c: Ditto.
147 2013-02-27 Alan Modra <amodra@gmail.com>
149 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
150 * rl78-decode.c: Regenerate.
152 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
154 * rl78-decode.opc: Fix encoding of DIVWU insn.
155 * rl78-decode.c: Regenerate.
157 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
160 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
162 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
163 (cpu_flags): Add CpuSMAP.
165 * i386-opc.h (CpuSMAP): New.
166 (i386_cpu_flags): Add cpusmap.
168 * i386-opc.tbl: Add clac and stac.
170 * i386-init.h: Regenerated.
171 * i386-tbl.h: Likewise.
173 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
175 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
176 which also makes the disassembler output be in little
177 endian like it should be.
179 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
181 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
183 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
185 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
187 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
188 section disassembled.
190 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
192 * arm-dis.c: Update strht pattern.
194 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
196 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
197 single-float. Disable ll, lld, sc and scd for EE. Disable the
198 trunc.w.s macro for EE.
200 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
201 Andrew Jenner <andrew@codesourcery.com>
203 Based on patches from Altera Corporation.
205 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
207 * Makefile.in: Regenerated.
208 * configure.in: Add case for bfd_nios2_arch.
209 * configure: Regenerated.
210 * disassemble.c (ARCH_nios2): Define.
211 (disassembler): Add case for bfd_arch_nios2.
212 * nios2-dis.c: New file.
213 * nios2-opc.c: New file.
215 2013-02-04 Alan Modra <amodra@gmail.com>
217 * po/POTFILES.in: Regenerate.
218 * rl78-decode.c: Regenerate.
219 * rx-decode.c: Regenerate.
221 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
223 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
224 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
225 * aarch64-asm.c (convert_xtl_to_shll): New function.
226 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
227 calling convert_xtl_to_shll.
228 * aarch64-dis.c (convert_shll_to_xtl): New function.
229 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
230 calling convert_shll_to_xtl.
231 * aarch64-gen.c: Update copyright year.
232 * aarch64-asm-2.c: Re-generate.
233 * aarch64-dis-2.c: Re-generate.
234 * aarch64-opc-2.c: Re-generate.
236 2013-01-24 Nick Clifton <nickc@redhat.com>
238 * v850-dis.c: Add support for e3v5 architecture.
239 * v850-opc.c: Likewise.
241 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
243 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
244 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
245 * aarch64-opc.c (operand_general_constraint_met_p): For
246 AARCH64_MOD_LSL, move the range check on the shift amount before the
247 alignment check; change to call set_sft_amount_out_of_range_error
248 instead of set_imm_out_of_range_error.
249 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
250 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
251 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
254 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
256 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
258 * i386-init.h: Regenerated.
259 * i386-tbl.h: Likewise.
261 2013-01-15 Nick Clifton <nickc@redhat.com>
263 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
265 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
267 2013-01-14 Will Newton <will.newton@imgtec.com>
269 * metag-dis.c (REG_WIDTH): Increase to 64.
271 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
273 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
274 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
275 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
277 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
278 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
279 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
280 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
282 2013-01-10 Will Newton <will.newton@imgtec.com>
284 * Makefile.am: Add Meta.
285 * configure.in: Add Meta.
286 * disassemble.c: Add Meta support.
287 * metag-dis.c: New file.
288 * Makefile.in: Regenerate.
289 * configure: Regenerate.
291 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
293 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
294 (match_opcode): Rename to cr16_match_opcode.
296 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
298 * mips-dis.c: Add names for CP0 registers of r5900.
299 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
300 instructions sq and lq.
301 Add support for MIPS r5900 CPU.
302 Add support for 128 bit MMI (Multimedia Instructions).
303 Add support for EE instructions (Emotion Engine).
304 Disable unsupported floating point instructions (64 bit and
305 undefined compare operations).
306 Enable instructions of MIPS ISA IV which are supported by r5900.
307 Disable 64 bit co processor instructions.
308 Disable 64 bit multiplication and division instructions.
309 Disable instructions for co-processor 2 and 3, because these are
310 not supported (preparation for later VU0 support (Vector Unit)).
311 Disable cvt.w.s because this behaves like trunc.w.s and the
312 correct execution can't be ensured on r5900.
313 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
314 will confuse less developers and compilers.
316 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
318 * aarch64-opc.c (aarch64_print_operand): Change to print
319 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
321 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
322 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
325 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
327 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
328 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
330 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
332 * i386-gen.c (process_copyright): Update copyright year to 2013.
334 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
336 * cr16-dis.c (match_opcode,make_instruction): Remove static
338 (dwordU,wordU): Moved typedefs to opcode/cr16.h
339 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
341 For older changes see ChangeLog-2012
343 Copyright (C) 2013 Free Software Foundation, Inc.
345 Copying and distribution of this file, with or without modification,
346 are permitted in any medium without royalty provided the copyright
347 notice and this notice are preserved.
353 version-control: never