1 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2 Michael Collison <michael.collison@arm.com>
4 * arm-dis.c (thumb32_opcodes): Add new instructions.
5 (print_insn_thumb32): Handle new instructions.
7 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
8 Michael Collison <michael.collison@arm.com>
10 * arm-dis.c (enum mve_instructions): Add new instructions.
11 (enum mve_undefined): Add new reasons.
12 (is_mve_encoding_conflict): Handle new instructions.
13 (is_mve_undefined): Likewise.
14 (is_mve_unpredictable): Likewise.
15 (print_mve_undefined): Likewise.
16 (print_mve_size): Likewise.
17 (print_mve_shift_n): Likewise.
18 (print_insn_mve): Likewise.
20 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
21 Michael Collison <michael.collison@arm.com>
23 * arm-dis.c (enum mve_instructions): Add new instructions.
24 (is_mve_encoding_conflict): Handle new instructions.
25 (is_mve_unpredictable): Likewise.
26 (print_mve_rotate): Likewise.
27 (print_mve_size): Likewise.
28 (print_insn_mve): Likewise.
30 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
31 Michael Collison <michael.collison@arm.com>
33 * arm-dis.c (enum mve_instructions): Add new instructions.
34 (is_mve_encoding_conflict): Handle new instructions.
35 (is_mve_unpredictable): Likewise.
36 (print_mve_size): Likewise.
37 (print_insn_mve): Likewise.
39 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
40 Michael Collison <michael.collison@arm.com>
42 * arm-dis.c (enum mve_instructions): Add new instructions.
43 (enum mve_undefined): Add new reasons.
44 (is_mve_encoding_conflict): Handle new instructions.
45 (is_mve_undefined): Likewise.
46 (is_mve_unpredictable): Likewise.
47 (print_mve_undefined): Likewise.
48 (print_mve_size): Likewise.
49 (print_insn_mve): Likewise.
51 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
52 Michael Collison <michael.collison@arm.com>
54 * arm-dis.c (enum mve_instructions): Add new instructions.
55 (is_mve_encoding_conflict): Handle new instructions.
56 (is_mve_undefined): Likewise.
57 (is_mve_unpredictable): Likewise.
58 (print_mve_size): Likewise.
59 (print_insn_mve): Likewise.
61 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
62 Michael Collison <michael.collison@arm.com>
64 * arm-dis.c (enum mve_instructions): Add new instructions.
65 (enum mve_unpredictable): Add new reasons.
66 (enum mve_undefined): Likewise.
67 (is_mve_okay_in_it): Handle new isntructions.
68 (is_mve_encoding_conflict): Likewise.
69 (is_mve_undefined): Likewise.
70 (is_mve_unpredictable): Likewise.
71 (print_mve_vmov_index): Likewise.
72 (print_simd_imm8): Likewise.
73 (print_mve_undefined): Likewise.
74 (print_mve_unpredictable): Likewise.
75 (print_mve_size): Likewise.
76 (print_insn_mve): Likewise.
78 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
79 Michael Collison <michael.collison@arm.com>
81 * arm-dis.c (enum mve_instructions): Add new instructions.
82 (enum mve_unpredictable): Add new reasons.
83 (enum mve_undefined): Likewise.
84 (is_mve_encoding_conflict): Handle new instructions.
85 (is_mve_undefined): Likewise.
86 (is_mve_unpredictable): Likewise.
87 (print_mve_undefined): Likewise.
88 (print_mve_unpredictable): Likewise.
89 (print_mve_rounding_mode): Likewise.
90 (print_mve_vcvt_size): Likewise.
91 (print_mve_size): Likewise.
92 (print_insn_mve): Likewise.
94 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
95 Michael Collison <michael.collison@arm.com>
97 * arm-dis.c (enum mve_instructions): Add new instructions.
98 (enum mve_unpredictable): Add new reasons.
99 (enum mve_undefined): Likewise.
100 (is_mve_undefined): Handle new instructions.
101 (is_mve_unpredictable): Likewise.
102 (print_mve_undefined): Likewise.
103 (print_mve_unpredictable): Likewise.
104 (print_mve_size): Likewise.
105 (print_insn_mve): Likewise.
107 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
108 Michael Collison <michael.collison@arm.com>
110 * arm-dis.c (enum mve_instructions): Add new instructions.
111 (enum mve_undefined): Add new reasons.
112 (insns): Add new instructions.
113 (is_mve_encoding_conflict):
114 (print_mve_vld_str_addr): New print function.
115 (is_mve_undefined): Handle new instructions.
116 (is_mve_unpredictable): Likewise.
117 (print_mve_undefined): Likewise.
118 (print_mve_size): Likewise.
119 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
120 (print_insn_mve): Handle new operands.
122 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
123 Michael Collison <michael.collison@arm.com>
125 * arm-dis.c (enum mve_instructions): Add new instructions.
126 (enum mve_unpredictable): Add new reasons.
127 (is_mve_encoding_conflict): Handle new instructions.
128 (is_mve_unpredictable): Likewise.
129 (mve_opcodes): Add new instructions.
130 (print_mve_unpredictable): Handle new reasons.
131 (print_mve_register_blocks): New print function.
132 (print_mve_size): Handle new instructions.
133 (print_insn_mve): Likewise.
135 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
136 Michael Collison <michael.collison@arm.com>
138 * arm-dis.c (enum mve_instructions): Add new instructions.
139 (enum mve_unpredictable): Add new reasons.
140 (enum mve_undefined): Likewise.
141 (is_mve_encoding_conflict): Handle new instructions.
142 (is_mve_undefined): Likewise.
143 (is_mve_unpredictable): Likewise.
144 (coprocessor_opcodes): Move NEON VDUP from here...
145 (neon_opcodes): ... to here.
146 (mve_opcodes): Add new instructions.
147 (print_mve_undefined): Handle new reasons.
148 (print_mve_unpredictable): Likewise.
149 (print_mve_size): Handle new instructions.
150 (print_insn_neon): Handle vdup.
151 (print_insn_mve): Handle new operands.
153 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
154 Michael Collison <michael.collison@arm.com>
156 * arm-dis.c (enum mve_instructions): Add new instructions.
157 (enum mve_unpredictable): Add new values.
158 (mve_opcodes): Add new instructions.
159 (vec_condnames): New array with vector conditions.
160 (mve_predicatenames): New array with predicate suffixes.
161 (mve_vec_sizename): New array with vector sizes.
162 (enum vpt_pred_state): New enum with vector predication states.
163 (struct vpt_block): New struct type for vpt blocks.
164 (vpt_block_state): Global struct to keep track of state.
165 (mve_extract_pred_mask): New helper function.
166 (num_instructions_vpt_block): Likewise.
167 (mark_outside_vpt_block): Likewise.
168 (mark_inside_vpt_block): Likewise.
169 (invert_next_predicate_state): Likewise.
170 (update_next_predicate_state): Likewise.
171 (update_vpt_block_state): Likewise.
172 (is_vpt_instruction): Likewise.
173 (is_mve_encoding_conflict): Add entries for new instructions.
174 (is_mve_unpredictable): Likewise.
175 (print_mve_unpredictable): Handle new cases.
176 (print_instruction_predicate): Likewise.
177 (print_mve_size): New function.
178 (print_vec_condition): New function.
179 (print_insn_mve): Handle vpt blocks and new print operands.
181 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
183 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
184 8, 14 and 15 for Armv8.1-M Mainline.
186 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
187 Michael Collison <michael.collison@arm.com>
189 * arm-dis.c (enum mve_instructions): New enum.
190 (enum mve_unpredictable): Likewise.
191 (enum mve_undefined): Likewise.
192 (struct mopcode32): New struct.
193 (is_mve_okay_in_it): New function.
194 (is_mve_architecture): Likewise.
195 (arm_decode_field): Likewise.
196 (arm_decode_field_multiple): Likewise.
197 (is_mve_encoding_conflict): Likewise.
198 (is_mve_undefined): Likewise.
199 (is_mve_unpredictable): Likewise.
200 (print_mve_undefined): Likewise.
201 (print_mve_unpredictable): Likewise.
202 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
203 (print_insn_mve): New function.
204 (print_insn_thumb32): Handle MVE architecture.
205 (select_arm_features): Force thumb for Armv8.1-m Mainline.
207 2019-05-10 Nick Clifton <nickc@redhat.com>
210 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
211 end of the table prematurely.
213 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
215 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
218 2019-05-11 Alan Modra <amodra@gmail.com>
220 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
221 when -Mraw is in effect.
223 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
225 * aarch64-dis-2.c: Regenerate.
226 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
227 (OP_SVE_BBB): New variant set.
228 (OP_SVE_DDDD): New variant set.
229 (OP_SVE_HHH): New variant set.
230 (OP_SVE_HHHU): New variant set.
231 (OP_SVE_SSS): New variant set.
232 (OP_SVE_SSSU): New variant set.
233 (OP_SVE_SHH): New variant set.
234 (OP_SVE_SBBU): New variant set.
235 (OP_SVE_DSS): New variant set.
236 (OP_SVE_DHHU): New variant set.
237 (OP_SVE_VMV_HSD_BHS): New variant set.
238 (OP_SVE_VVU_HSD_BHS): New variant set.
239 (OP_SVE_VVVU_SD_BH): New variant set.
240 (OP_SVE_VVVU_BHSD): New variant set.
241 (OP_SVE_VVV_QHD_DBS): New variant set.
242 (OP_SVE_VVV_HSD_BHS): New variant set.
243 (OP_SVE_VVV_HSD_BHS2): New variant set.
244 (OP_SVE_VVV_BHS_HSD): New variant set.
245 (OP_SVE_VV_BHS_HSD): New variant set.
246 (OP_SVE_VVV_SD): New variant set.
247 (OP_SVE_VVU_BHS_HSD): New variant set.
248 (OP_SVE_VZVV_SD): New variant set.
249 (OP_SVE_VZVV_BH): New variant set.
250 (OP_SVE_VZV_SD): New variant set.
251 (aarch64_opcode_table): Add sve2 instructions.
253 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
255 * aarch64-asm-2.c: Regenerated.
256 * aarch64-dis-2.c: Regenerated.
257 * aarch64-opc-2.c: Regenerated.
258 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
259 for SVE_SHLIMM_UNPRED_22.
260 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
261 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
264 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
266 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
267 sve_size_tsz_bhs iclass encode.
268 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
269 sve_size_tsz_bhs iclass decode.
271 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
273 * aarch64-asm-2.c: Regenerated.
274 * aarch64-dis-2.c: Regenerated.
275 * aarch64-opc-2.c: Regenerated.
276 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
277 for SVE_Zm4_11_INDEX.
278 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
279 (fields): Handle SVE_i2h field.
280 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
281 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
283 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
285 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
286 sve_shift_tsz_bhsd iclass encode.
287 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
288 sve_shift_tsz_bhsd iclass decode.
290 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
292 * aarch64-asm-2.c: Regenerated.
293 * aarch64-dis-2.c: Regenerated.
294 * aarch64-opc-2.c: Regenerated.
295 * aarch64-asm.c (aarch64_ins_sve_shrimm):
296 (aarch64_encode_variant_using_iclass): Handle
297 sve_shift_tsz_hsd iclass encode.
298 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
299 sve_shift_tsz_hsd iclass decode.
300 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
301 for SVE_SHRIMM_UNPRED_22.
302 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
303 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
306 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
308 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
309 sve_size_013 iclass encode.
310 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
311 sve_size_013 iclass decode.
313 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
315 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
316 sve_size_bh iclass encode.
317 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
318 sve_size_bh iclass decode.
320 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
322 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
323 sve_size_sd2 iclass encode.
324 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
325 sve_size_sd2 iclass decode.
326 * aarch64-opc.c (fields): Handle SVE_sz2 field.
327 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
329 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
331 * aarch64-asm-2.c: Regenerated.
332 * aarch64-dis-2.c: Regenerated.
333 * aarch64-opc-2.c: Regenerated.
334 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
336 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
337 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
339 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
341 * aarch64-asm-2.c: Regenerated.
342 * aarch64-dis-2.c: Regenerated.
343 * aarch64-opc-2.c: Regenerated.
344 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
345 for SVE_Zm3_11_INDEX.
346 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
347 (fields): Handle SVE_i3l and SVE_i3h2 fields.
348 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
350 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
352 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
354 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
355 sve_size_hsd2 iclass encode.
356 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
357 sve_size_hsd2 iclass decode.
358 * aarch64-opc.c (fields): Handle SVE_size field.
359 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
361 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
363 * aarch64-asm-2.c: Regenerated.
364 * aarch64-dis-2.c: Regenerated.
365 * aarch64-opc-2.c: Regenerated.
366 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
368 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
369 (fields): Handle SVE_rot3 field.
370 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
371 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
373 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
375 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
378 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
381 (aarch64_feature_sve2, aarch64_feature_sve2aes,
382 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
383 aarch64_feature_sve2bitperm): New feature sets.
384 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
385 for feature set addresses.
386 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
387 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
389 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
390 Faraz Shahbazker <fshahbazker@wavecomp.com>
392 * mips-dis.c (mips_calculate_combination_ases): Add ISA
393 argument and set ASE_EVA_R6 appropriately.
394 (set_default_mips_dis_options): Pass ISA to above.
395 (parse_mips_dis_option): Likewise.
396 * mips-opc.c (EVAR6): New macro.
397 (mips_builtin_opcodes): Add llwpe, scwpe.
399 2019-05-01 Sudakshina Das <sudi.das@arm.com>
401 * aarch64-asm-2.c: Regenerated.
402 * aarch64-dis-2.c: Regenerated.
403 * aarch64-opc-2.c: Regenerated.
404 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
405 AARCH64_OPND_TME_UIMM16.
406 (aarch64_print_operand): Likewise.
407 * aarch64-tbl.h (QL_IMM_NIL): New.
410 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
412 2019-04-29 John Darrington <john@darrington.wattle.id.au>
414 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
416 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
417 Faraz Shahbazker <fshahbazker@wavecomp.com>
419 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
421 2019-04-24 John Darrington <john@darrington.wattle.id.au>
423 * s12z-opc.h: Add extern "C" bracketing to help
424 users who wish to use this interface in c++ code.
426 2019-04-24 John Darrington <john@darrington.wattle.id.au>
428 * s12z-opc.c (bm_decode): Handle bit map operations with the
431 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
433 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
434 specifier. Add entries for VLDR and VSTR of system registers.
435 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
436 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
437 of %J and %K format specifier.
439 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
441 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
442 Add new entries for VSCCLRM instruction.
443 (print_insn_coprocessor): Handle new %C format control code.
445 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
447 * arm-dis.c (enum isa): New enum.
448 (struct sopcode32): New structure.
449 (coprocessor_opcodes): change type of entries to struct sopcode32 and
450 set isa field of all current entries to ANY.
451 (print_insn_coprocessor): Change type of insn to struct sopcode32.
452 Only match an entry if its isa field allows the current mode.
454 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
456 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
458 (print_insn_thumb32): Add logic to print %n CLRM register list.
460 2019-04-15 Sudakshina Das <sudi.das@arm.com>
462 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
465 2019-04-15 Sudakshina Das <sudi.das@arm.com>
467 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
468 (print_insn_thumb32): Edit the switch case for %Z.
470 2019-04-15 Sudakshina Das <sudi.das@arm.com>
472 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
474 2019-04-15 Sudakshina Das <sudi.das@arm.com>
476 * arm-dis.c (thumb32_opcodes): New instruction bfl.
478 2019-04-15 Sudakshina Das <sudi.das@arm.com>
480 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
482 2019-04-15 Sudakshina Das <sudi.das@arm.com>
484 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
485 Arm register with r13 and r15 unpredictable.
486 (thumb32_opcodes): New instructions for bfx and bflx.
488 2019-04-15 Sudakshina Das <sudi.das@arm.com>
490 * arm-dis.c (thumb32_opcodes): New instructions for bf.
492 2019-04-15 Sudakshina Das <sudi.das@arm.com>
494 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
496 2019-04-15 Sudakshina Das <sudi.das@arm.com>
498 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
500 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
502 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
504 2019-04-12 John Darrington <john@darrington.wattle.id.au>
506 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
507 "optr". ("operator" is a reserved word in c++).
509 2019-04-11 Sudakshina Das <sudi.das@arm.com>
511 * aarch64-opc.c (aarch64_print_operand): Add case for
513 (verify_constraints): Likewise.
514 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
515 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
516 to accept Rt|SP as first operand.
517 (AARCH64_OPERANDS): Add new Rt_SP.
518 * aarch64-asm-2.c: Regenerated.
519 * aarch64-dis-2.c: Regenerated.
520 * aarch64-opc-2.c: Regenerated.
522 2019-04-11 Sudakshina Das <sudi.das@arm.com>
524 * aarch64-asm-2.c: Regenerated.
525 * aarch64-dis-2.c: Likewise.
526 * aarch64-opc-2.c: Likewise.
527 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
529 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
531 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
533 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
535 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
536 * i386-init.h: Regenerated.
538 2019-04-07 Alan Modra <amodra@gmail.com>
540 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
541 op_separator to control printing of spaces, comma and parens
542 rather than need_comma, need_paren and spaces vars.
544 2019-04-07 Alan Modra <amodra@gmail.com>
547 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
548 (print_insn_neon, print_insn_arm): Likewise.
550 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
552 * i386-dis-evex.h (evex_table): Updated to support BF16
554 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
555 and EVEX_W_0F3872_P_3.
556 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
557 (cpu_flags): Add bitfield for CpuAVX512_BF16.
558 * i386-opc.h (enum): Add CpuAVX512_BF16.
559 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
560 * i386-opc.tbl: Add AVX512 BF16 instructions.
561 * i386-init.h: Regenerated.
562 * i386-tbl.h: Likewise.
564 2019-04-05 Alan Modra <amodra@gmail.com>
566 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
567 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
568 to favour printing of "-" branch hint when using the "y" bit.
569 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
571 2019-04-05 Alan Modra <amodra@gmail.com>
573 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
574 opcode until first operand is output.
576 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
579 * ppc-opc.c (valid_bo_pre_v2): Add comments.
580 (valid_bo_post_v2): Add support for 'at' branch hints.
581 (insert_bo): Only error on branch on ctr.
582 (get_bo_hint_mask): New function.
583 (insert_boe): Add new 'branch_taken' formal argument. Add support
584 for inserting 'at' branch hints.
585 (extract_boe): Add new 'branch_taken' formal argument. Add support
586 for extracting 'at' branch hints.
587 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
588 (BOE): Delete operand.
589 (BOM, BOP): New operands.
591 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
592 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
593 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
594 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
595 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
596 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
597 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
598 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
599 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
600 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
601 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
602 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
603 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
604 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
605 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
606 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
607 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
608 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
609 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
610 bttarl+>: New extended mnemonics.
612 2019-03-28 Alan Modra <amodra@gmail.com>
615 * ppc-opc.c (BTF): Define.
616 (powerpc_opcodes): Use for mtfsb*.
617 * ppc-dis.c (print_insn_powerpc): Print fields with both
618 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
620 2019-03-25 Tamar Christina <tamar.christina@arm.com>
622 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
623 (mapping_symbol_for_insn): Implement new algorithm.
624 (print_insn): Remove duplicate code.
626 2019-03-25 Tamar Christina <tamar.christina@arm.com>
628 * aarch64-dis.c (print_insn_aarch64):
631 2019-03-25 Tamar Christina <tamar.christina@arm.com>
633 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
636 2019-03-25 Tamar Christina <tamar.christina@arm.com>
638 * aarch64-dis.c (last_stop_offset): New.
639 (print_insn_aarch64): Use stop_offset.
641 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
644 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
646 * i386-init.h: Regenerated.
648 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
651 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
652 vmovdqu16, vmovdqu32 and vmovdqu64.
653 * i386-tbl.h: Regenerated.
655 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
657 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
658 from vstrszb, vstrszh, and vstrszf.
660 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
662 * s390-opc.txt: Add instruction descriptions.
664 2019-02-08 Jim Wilson <jimw@sifive.com>
666 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
669 2019-02-07 Tamar Christina <tamar.christina@arm.com>
671 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
673 2019-02-07 Tamar Christina <tamar.christina@arm.com>
676 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
677 * aarch64-opc.c (verify_elem_sd): New.
678 (fields): Add FLD_sz entr.
679 * aarch64-tbl.h (_SIMD_INSN): New.
680 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
681 fmulx scalar and vector by element isns.
683 2019-02-07 Nick Clifton <nickc@redhat.com>
685 * po/sv.po: Updated Swedish translation.
687 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
689 * s390-mkopc.c (main): Accept arch13 as cpu string.
690 * s390-opc.c: Add new instruction formats and instruction opcode
692 * s390-opc.txt: Add new arch13 instructions.
694 2019-01-25 Sudakshina Das <sudi.das@arm.com>
696 * aarch64-tbl.h (QL_LDST_AT): Update macro.
697 (aarch64_opcode): Change encoding for stg, stzg
699 * aarch64-asm-2.c: Regenerated.
700 * aarch64-dis-2.c: Regenerated.
701 * aarch64-opc-2.c: Regenerated.
703 2019-01-25 Sudakshina Das <sudi.das@arm.com>
705 * aarch64-asm-2.c: Regenerated.
706 * aarch64-dis-2.c: Likewise.
707 * aarch64-opc-2.c: Likewise.
708 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
710 2019-01-25 Sudakshina Das <sudi.das@arm.com>
711 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
713 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
714 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
715 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
716 * aarch64-dis.h (ext_addr_simple_2): Likewise.
717 * aarch64-opc.c (operand_general_constraint_met_p): Remove
718 case for ldstgv_indexed.
719 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
720 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
721 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
722 * aarch64-asm-2.c: Regenerated.
723 * aarch64-dis-2.c: Regenerated.
724 * aarch64-opc-2.c: Regenerated.
726 2019-01-23 Nick Clifton <nickc@redhat.com>
728 * po/pt_BR.po: Updated Brazilian Portuguese translation.
730 2019-01-21 Nick Clifton <nickc@redhat.com>
732 * po/de.po: Updated German translation.
733 * po/uk.po: Updated Ukranian translation.
735 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
736 * mips-dis.c (mips_arch_choices): Fix typo in
737 gs464, gs464e and gs264e descriptors.
739 2019-01-19 Nick Clifton <nickc@redhat.com>
741 * configure: Regenerate.
742 * po/opcodes.pot: Regenerate.
744 2018-06-24 Nick Clifton <nickc@redhat.com>
748 2019-01-09 John Darrington <john@darrington.wattle.id.au>
750 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
752 -dis.c (opr_emit_disassembly): Do not omit an index if it is
755 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
757 * configure: Regenerate.
759 2019-01-07 Alan Modra <amodra@gmail.com>
761 * configure: Regenerate.
762 * po/POTFILES.in: Regenerate.
764 2019-01-03 John Darrington <john@darrington.wattle.id.au>
766 * s12z-opc.c: New file.
767 * s12z-opc.h: New file.
768 * s12z-dis.c: Removed all code not directly related to display
769 of instructions. Used the interface provided by the new files
771 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
772 * Makefile.in: Regenerate.
773 * configure.ac (bfd_s12z_arch): Correct the dependencies.
774 * configure: Regenerate.
776 2019-01-01 Alan Modra <amodra@gmail.com>
778 Update year range in copyright notice of all files.
780 For older changes see ChangeLog-2018
782 Copyright (C) 2019 Free Software Foundation, Inc.
784 Copying and distribution of this file, with or without modification,
785 are permitted in any medium without royalty provided the copyright
786 notice and this notice are preserved.
792 version-control: never