1 2011-09-08 David S. Miller <davem@davemloft.net>
3 * sparc-opc.c (pdistn): Destination is integer not float register.
5 2011-09-07 Andreas Schwab <schwab@linux-m68k.org>
7 * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
9 2011-08-26 Nick Clifton <nickc@redhat.com>
11 * po/es.po: Updated Spanish translation.
13 2011-08-22 Nick Clifton <nickc@redhat.com>
15 * Makefile.am (CPUDIR): Redfine to point to top level cpu
17 (stamp-frv): Use CPUDIR.
18 (stamp-iq2000): Likewise.
19 (stamp-lm32): Likewise.
20 (stamp-m32c): Likewise.
22 (stamp-xc16x): Likewise.
23 * Makefile.in: Regenerate.
25 2011-08-09 Chao-ying Fu <fu@mips.com>
26 Maciej W. Rozycki <macro@codesourcery.com>
28 * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
30 (print_insn_args, print_insn_micromips): Handle MCU.
31 * micromips-opc.c (MC): New macro.
32 (micromips_opcodes): Add "aclr", "aset" and "iret".
33 * mips-opc.c (MC): New macro.
34 (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
36 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
38 * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
39 (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
40 (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
41 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
42 (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
43 (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
45 (micromips_opcodes): Update register use flags of: "addiu",
46 "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
47 "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
48 "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
49 "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
50 "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
51 "swm" and "xor" instructions.
53 2011-08-05 David S. Miller <davem@davemloft.net>
55 * sparc-dis.c (v9a_ast_reg_names): Add "cps".
57 (print_insn_sparc): Handle '4', '5', and '(' format codes.
58 Accept %asr numbers below 28.
59 * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
62 2011-08-02 Quentin Neill <quentin.neill@amd.com>
64 * i386-dis.c (xop_table): Remove spurious bextr insn.
66 2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
69 * i386-dis.c (print_insn): Optimize info->mach check.
71 2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
74 * i386-opc.tbl: Add Disp32S to 64bit call.
75 * i386-tbl.h: Regenerated.
77 2011-07-24 Chao-ying Fu <fu@mips.com>
78 Maciej W. Rozycki <macro@codesourcery.com>
80 * micromips-opc.c: New file.
81 * mips-dis.c (micromips_to_32_reg_b_map): New array.
82 (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
83 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
84 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
85 (micromips_to_32_reg_q_map): Likewise.
86 (micromips_imm_b_map, micromips_imm_c_map): Likewise.
87 (micromips_ase): New variable.
88 (is_micromips): New function.
89 (set_default_mips_dis_options): Handle microMIPS ASE.
90 (print_insn_micromips): New function.
91 (is_compressed_mode_p): Likewise.
92 (_print_insn_mips): Handle microMIPS instructions.
93 * Makefile.am (CFILES): Add micromips-opc.c.
94 * configure.in (bfd_mips_arch): Add micromips-opc.lo.
95 * Makefile.in: Regenerate.
96 * configure: Regenerate.
98 * mips-dis.c (micromips_to_32_reg_h_map): New variable.
99 (micromips_to_32_reg_i_map): Likewise.
100 (micromips_to_32_reg_m_map): Likewise.
101 (micromips_to_32_reg_n_map): New macro.
103 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
105 * mips-opc.c (NODS): New macro.
106 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
107 (DSP_VOLA): Likewise.
108 (mips_builtin_opcodes): Add NODS annotation to "deret" and
109 "eret". Replace INSN_SYNC with NODS throughout. Use NODS in
110 place of TRAP for "wait", "waiti" and "yield".
111 * mips16-opc.c (NODS): New macro.
112 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
113 (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
114 "restore" and "save".
116 2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
118 * configure.in: Handle bfd_k1om_arch.
119 * configure: Regenerated.
121 * disassemble.c (disassembler): Handle bfd_k1om_arch.
123 * i386-dis.c (print_insn): Handle bfd_mach_k1om and
124 bfd_mach_k1om_intel_syntax.
126 * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
127 ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
128 (cpu_flags): Add CpuK1OM.
130 * i386-opc.h (CpuK1OM): New.
131 (i386_cpu_flags): Add cpuk1om.
133 * i386-init.h: Regenerated.
134 * i386-tbl.h: Likewise.
136 2011-07-12 Nick Clifton <nickc@redhat.com>
138 * arm-dis.c (print_insn_arm): Revert previous, undocumented,
141 2011-07-01 Nick Clifton <nickc@redhat.com>
144 * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
145 insns using post-increment addressing.
147 2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
149 * i386-dis.c (vex_len_table): Update rorxS.
151 2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
153 AVX Programming Reference (June, 2011)
154 * i386-dis.c (vex_len_table): Correct rorxS.
156 * i386-opc.tbl: Correct rorx.
157 * i386-tbl.h: Regenerated.
159 2011-06-29 H.J. Lu <hongjiu.lu@intel.com>
161 * tilegx-opc.c (find_opcode): Replace "index" with "i".
162 * tilepro-opc.c (find_opcode): Likewise.
164 2011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
166 * mips16-opc.c (jalrc, jrc): Move earlier in file.
168 2011-06-21 H.J. Lu <hongjiu.lu@intel.com>
170 * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
173 2011-06-17 Andreas Schwab <schwab@redhat.com>
175 * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
176 (MOSTLYCLEANFILES): ... here.
177 * Makefile.in: Regenerate.
179 2011-06-14 Alan Modra <amodra@gmail.com>
181 * Makefile.in: Regenerate.
183 2011-06-13 Walter Lee <walt@tilera.com>
185 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
186 tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
187 * Makefile.in: Regenerate.
188 * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
189 * configure: Regenerate.
190 * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
191 * po/POTFILES.in: Regenerate.
192 * tilegx-dis.c: New file.
193 * tilegx-opc.c: New file.
194 * tilepro-dis.c: New file.
195 * tilepro-opc.c: New file.
197 2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
199 AVX Programming Reference (June, 2011)
200 * i386-dis.c (XMGatherQ): New.
201 * i386-dis.c (EXxmm_mb): New.
202 (EXxmm_mb): Likewise.
203 (EXxmm_mw): Likewise.
204 (EXxmm_md): Likewise.
205 (EXxmm_mq): Likewise.
208 (VexGatherQ): Likewise.
209 (MVexVSIBDWpX): Likewise.
210 (MVexVSIBQWpX): Likewise.
211 (xmm_mb_mode): Likewise.
212 (xmm_mw_mode): Likewise.
213 (xmm_md_mode): Likewise.
214 (xmm_mq_mode): Likewise.
215 (xmmdw_mode): Likewise.
216 (xmmqd_mode): Likewise.
217 (ymmxmm_mode): Likewise.
218 (vex_vsib_d_w_dq_mode): Likewise.
219 (vex_vsib_q_w_dq_mode): Likewise.
220 (MOD_VEX_0F385A_PREFIX_2): Likewise.
221 (MOD_VEX_0F388C_PREFIX_2): Likewise.
222 (MOD_VEX_0F388E_PREFIX_2): Likewise.
223 (PREFIX_0F3882): Likewise.
224 (PREFIX_VEX_0F3816): Likewise.
225 (PREFIX_VEX_0F3836): Likewise.
226 (PREFIX_VEX_0F3845): Likewise.
227 (PREFIX_VEX_0F3846): Likewise.
228 (PREFIX_VEX_0F3847): Likewise.
229 (PREFIX_VEX_0F3858): Likewise.
230 (PREFIX_VEX_0F3859): Likewise.
231 (PREFIX_VEX_0F385A): Likewise.
232 (PREFIX_VEX_0F3878): Likewise.
233 (PREFIX_VEX_0F3879): Likewise.
234 (PREFIX_VEX_0F388C): Likewise.
235 (PREFIX_VEX_0F388E): Likewise.
236 (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
237 (PREFIX_VEX_0F38F5): Likewise.
238 (PREFIX_VEX_0F38F6): Likewise.
239 (PREFIX_VEX_0F3A00): Likewise.
240 (PREFIX_VEX_0F3A01): Likewise.
241 (PREFIX_VEX_0F3A02): Likewise.
242 (PREFIX_VEX_0F3A38): Likewise.
243 (PREFIX_VEX_0F3A39): Likewise.
244 (PREFIX_VEX_0F3A46): Likewise.
245 (PREFIX_VEX_0F3AF0): Likewise.
246 (VEX_LEN_0F3816_P_2): Likewise.
247 (VEX_LEN_0F3819_P_2): Likewise.
248 (VEX_LEN_0F3836_P_2): Likewise.
249 (VEX_LEN_0F385A_P_2_M_0): Likewise.
250 (VEX_LEN_0F38F5_P_0): Likewise.
251 (VEX_LEN_0F38F5_P_1): Likewise.
252 (VEX_LEN_0F38F5_P_3): Likewise.
253 (VEX_LEN_0F38F6_P_3): Likewise.
254 (VEX_LEN_0F38F7_P_1): Likewise.
255 (VEX_LEN_0F38F7_P_2): Likewise.
256 (VEX_LEN_0F38F7_P_3): Likewise.
257 (VEX_LEN_0F3A00_P_2): Likewise.
258 (VEX_LEN_0F3A01_P_2): Likewise.
259 (VEX_LEN_0F3A38_P_2): Likewise.
260 (VEX_LEN_0F3A39_P_2): Likewise.
261 (VEX_LEN_0F3A46_P_2): Likewise.
262 (VEX_LEN_0F3AF0_P_3): Likewise.
263 (VEX_W_0F3816_P_2): Likewise.
264 (VEX_W_0F3818_P_2): Likewise.
265 (VEX_W_0F3819_P_2): Likewise.
266 (VEX_W_0F3836_P_2): Likewise.
267 (VEX_W_0F3846_P_2): Likewise.
268 (VEX_W_0F3858_P_2): Likewise.
269 (VEX_W_0F3859_P_2): Likewise.
270 (VEX_W_0F385A_P_2_M_0): Likewise.
271 (VEX_W_0F3878_P_2): Likewise.
272 (VEX_W_0F3879_P_2): Likewise.
273 (VEX_W_0F3A00_P_2): Likewise.
274 (VEX_W_0F3A01_P_2): Likewise.
275 (VEX_W_0F3A02_P_2): Likewise.
276 (VEX_W_0F3A38_P_2): Likewise.
277 (VEX_W_0F3A39_P_2): Likewise.
278 (VEX_W_0F3A46_P_2): Likewise.
279 (MOD_VEX_0F3818_PREFIX_2): Removed.
280 (MOD_VEX_0F3819_PREFIX_2): Likewise.
281 (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
282 (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
283 (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
284 (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
285 (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
286 (VEX_LEN_0F3A0E_P_2): Likewise.
287 (VEX_LEN_0F3A0F_P_2): Likewise.
288 (VEX_LEN_0F3A42_P_2): Likewise.
289 (VEX_LEN_0F3A4C_P_2): Likewise.
290 (VEX_W_0F3818_P_2_M_0): Likewise.
291 (VEX_W_0F3819_P_2_M_0): Likewise.
292 (prefix_table): Updated.
293 (three_byte_table): Likewise.
294 (vex_table): Likewise.
295 (vex_len_table): Likewise.
296 (vex_w_table): Likewise.
297 (mod_table): Likewise.
298 (putop): Handle "LW".
299 (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
300 xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
301 vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
303 (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
304 vex_vsib_q_w_dq_mode.
305 (OP_XMM): Handle vex_vsib_q_w_dq_mode.
308 * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
309 and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
310 CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
311 (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
312 (opcode_modifiers): Add VecSIB.
314 * i386-opc.h (CpuAVX2): New.
316 (CpuLZCNT): Likewise.
317 (CpuINVPCID): Likewise.
318 (VecSIB128): Likewise.
319 (VecSIB256): Likewise.
321 (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
322 (i386_opcode_modifier): Add vecsib.
324 * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
325 * i386-init.h: Regenerated.
326 * i386-tbl.h: Likewise.
328 2011-06-03 Quentin Neill <quentin.neill@amd.com>
330 * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
331 * i386-init.h: Regenerated.
333 2011-06-03 Nick Clifton <nickc@redhat.com>
336 * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
337 computing address offsets.
338 (print_arm_address): Likewise.
339 (print_insn_arm): Likewise.
340 (print_insn_thumb16): Likewise.
341 (print_insn_thumb32): Likewise.
343 2011-06-02 Jie Zhang <jie@codesourcery.com>
344 Nathan Sidwell <nathan@codesourcery.com>
345 Maciej Rozycki <macro@codesourcery.com>
347 * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
349 (print_arm_address): Likewise. Elide positive #0 appropriately.
350 (print_insn_arm): Likewise.
352 2011-06-02 Nick Clifton <nickc@redhat.com>
355 * arm-dis.c (print_insn_thumb32): Do not sign extend addresses
356 passed to print_address_func.
358 2011-06-02 Nick Clifton <nickc@redhat.com>
360 * arm-dis.c: Fix spelling mistakes.
361 * op/opcodes.pot: Regenerate.
363 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
365 * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
366 S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
367 * s390-opc.txt: Fix cxr instruction type.
369 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
371 * s390-opc.c: Add new instruction types marking register pair
373 * s390-opc.txt: Match instructions having register pair operands
374 to the new instruction types.
376 2011-05-19 Nick Clifton <nickc@redhat.com>
378 * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
381 2011-05-10 Quentin Neill <quentin.neill@amd.com>
383 * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
384 * i386-init.h: Regenerated.
386 2011-04-27 Nick Clifton <nickc@redhat.com>
388 * po/da.po: Updated Danish translation.
390 2011-04-26 Anton Blanchard <anton@samba.org>
392 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
394 2011-04-21 DJ Delorie <dj@redhat.com>
396 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
397 * rx-decode.c: Regenerate.
399 2011-04-20 H.J. Lu <hongjiu.lu@intel.com>
401 * i386-init.h: Regenerated.
403 2011-04-19 Quentin Neill <quentin.neill@amd.com>
405 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
408 2011-04-13 Nick Clifton <nickc@redhat.com>
410 * v850-dis.c (disassemble): Always print a closing square brace if
411 an opening square brace was printed.
413 2011-04-12 Nick Clifton <nickc@redhat.com>
416 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
418 (print_insn_thumb32): Handle %L.
420 2011-04-11 Julian Brown <julian@codesourcery.com>
422 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
423 (print_insn_thumb32): Add APSR bitmask support.
425 2011-04-07 Paul Carroll<pcarroll@codesourcery.com>
427 * arm-dis.c (print_insn): init vars moved into private_data structure.
429 2011-03-24 Mike Frysinger <vapier@gentoo.org>
431 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
433 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
435 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
436 post-increment to support LPM Z+ instruction. Add support for 'E'
437 constraint for DES instruction.
438 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
440 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
442 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
444 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
446 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
447 Use branch types instead.
448 (print_insn): Likewise.
450 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
452 * mips-opc.c (mips_builtin_opcodes): Correct register use
453 annotation of "alnv.ps".
455 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
457 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
459 2011-02-22 Mike Frysinger <vapier@gentoo.org>
461 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
463 2011-02-22 Mike Frysinger <vapier@gentoo.org>
465 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
467 2011-02-19 Mike Frysinger <vapier@gentoo.org>
469 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
470 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
471 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
472 exception, end_of_registers, msize, memory, bfd_mach.
473 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
474 LB0REG, LC1REG, LT1REG, LB1REG): Delete
475 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
476 (get_allreg): Change to new defines. Fallback to abort().
478 2011-02-14 Mike Frysinger <vapier@gentoo.org>
480 * bfin-dis.c: Add whitespace/parenthesis where needed.
482 2011-02-14 Mike Frysinger <vapier@gentoo.org>
484 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
487 2011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
489 * configure: Regenerate.
491 2011-02-13 Mike Frysinger <vapier@gentoo.org>
493 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
495 2011-02-13 Mike Frysinger <vapier@gentoo.org>
497 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
498 dregs only when P is set, and dregs_lo otherwise.
500 2011-02-13 Mike Frysinger <vapier@gentoo.org>
502 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
504 2011-02-12 Mike Frysinger <vapier@gentoo.org>
506 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
508 2011-02-12 Mike Frysinger <vapier@gentoo.org>
510 * bfin-dis.c (machine_registers): Delete REG_GP.
511 (reg_names): Delete "GP".
512 (decode_allregs): Change REG_GP to REG_LASTREG.
514 2011-02-12 Mike Frysinger <vapier@gentoo.org>
516 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
519 2011-02-11 Mike Frysinger <vapier@gentoo.org>
521 * bfin-dis.c (reg_names): Add const.
522 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
523 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
524 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
525 decode_counters, decode_allregs): Likewise.
527 2011-02-09 Michael Snyder <msnyder@vmware.com>
529 * i386-dis.c (OP_J): Parenthesize expression to prevent
531 (print_insn): Fix indentation off-by-one.
533 2011-02-01 Nick Clifton <nickc@redhat.com>
535 * po/da.po: Updated Danish translation.
537 2011-01-21 Dave Murphy <davem@devkitpro.org>
539 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
541 2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
543 * i386-dis.c (sIbT): New.
544 (b_T_mode): Likewise.
545 (dis386): Replace sIb with sIbT on "pushT".
546 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
547 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
549 2011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
551 * i386-init.h: Regenerated.
552 * i386-tbl.h: Regenerated
554 2011-01-17 Quentin Neill <quentin.neill@amd.com>
556 * i386-dis.c (REG_XOP_TBM_01): New.
557 (REG_XOP_TBM_02): New.
558 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
559 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
560 entries, and add bextr instruction.
562 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
563 (cpu_flags): Add CpuTBM.
565 * i386-opc.h (CpuTBM) New.
566 (i386_cpu_flags): Add bit cputbm.
568 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
569 blcs, blsfill, blsic, t1mskc, and tzmsk.
571 2011-01-12 DJ Delorie <dj@redhat.com>
573 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
575 2011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
577 * mips-dis.c (print_insn_args): Adjust the value to print the real
578 offset for "+c" argument.
580 2011-01-10 Nick Clifton <nickc@redhat.com>
582 * po/da.po: Updated Danish translation.
584 2011-01-05 Nathan Sidwell <nathan@codesourcery.com>
586 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
588 2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
590 * i386-dis.c (REG_VEX_38F3): New.
591 (PREFIX_0FBC): Likewise.
592 (PREFIX_VEX_38F2): Likewise.
593 (PREFIX_VEX_38F3_REG_1): Likewise.
594 (PREFIX_VEX_38F3_REG_2): Likewise.
595 (PREFIX_VEX_38F3_REG_3): Likewise.
596 (PREFIX_VEX_38F7): Likewise.
597 (VEX_LEN_38F2_P_0): Likewise.
598 (VEX_LEN_38F3_R_1_P_0): Likewise.
599 (VEX_LEN_38F3_R_2_P_0): Likewise.
600 (VEX_LEN_38F3_R_3_P_0): Likewise.
601 (VEX_LEN_38F7_P_0): Likewise.
602 (dis386_twobyte): Use PREFIX_0FBC.
603 (reg_table): Add REG_VEX_38F3.
604 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
605 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
606 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
607 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
609 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
610 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
613 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
614 (cpu_flags): Add CpuBMI.
616 * i386-opc.h (CpuBMI): New.
617 (i386_cpu_flags): Add cpubmi.
619 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
620 * i386-init.h: Regenerated.
621 * i386-tbl.h: Likewise.
623 2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
625 * i386-dis.c (VexGdq): New.
626 (OP_VEX): Handle dq_mode.
628 2011-01-01 H.J. Lu <hongjiu.lu@intel.com>
630 * i386-gen.c (process_copyright): Update copyright to 2011.
632 For older changes see ChangeLog-2010
638 version-control: never