1 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
3 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
5 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
7 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
8 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
9 XLS_MASK, PPCVSX2): New defines.
10 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
11 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
12 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
13 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
14 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
15 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
16 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
17 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
18 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
19 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
20 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
21 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
22 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
23 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
24 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
25 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
26 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
27 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
28 <lxvx, stxvx>: New extended mnemonics.
30 2013-05-17 Alan Modra <amodra@gmail.com>
32 * ia64-raw.tbl: Replace non-ASCII char.
33 * ia64-waw.tbl: Likewise.
34 * ia64-asmtab.c: Regenerate.
36 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
38 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
39 * i386-init.h: Regenerated.
41 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
43 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
44 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
45 check from [0, 255] to [-128, 255].
47 2013-05-09 Andrew Pinski <apinski@cavium.com>
49 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
50 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
51 (parse_mips_dis_option): Handle the virt option.
52 (print_insn_args): Handle "+J".
53 (print_mips_disassembler_options): Print out message about virt64.
54 * mips-opc.c (IVIRT): New define.
55 (IVIRT64): New define.
56 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
57 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
58 Move rfe to the bottom as it conflicts with tlbgp.
60 2013-05-09 Alan Modra <amodra@gmail.com>
62 * ppc-opc.c (extract_vlesi): Properly sign extend.
63 (extract_vlensi): Likewise. Comment reason for setting invalid.
65 2013-05-02 Nick Clifton <nickc@redhat.com>
67 * msp430-dis.c: Add support for MSP430X instructions.
69 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
71 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
74 2013-04-17 Wei-chen Wang <cole945@gmail.com>
77 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
79 (hash_insns_list): Likewise.
81 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
83 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
86 2013-04-08 Jan Beulich <jbeulich@suse.com>
88 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
89 * i386-tbl.h: Re-generate.
91 2013-04-06 David S. Miller <davem@davemloft.net>
93 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
94 of an opcode, prefer the one with F_PREFERRED set.
95 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
96 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
97 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
98 mark existing mnenomics as aliases. Add "cc" suffix to edge
99 instructions generating condition codes, mark existing mnenomics
100 as aliases. Add "fp" prefix to VIS compare instructions, mark
101 existing mnenomics as aliases.
103 2013-04-03 Nick Clifton <nickc@redhat.com>
105 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
106 destination address by subtracting the operand from the current
108 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
109 a positive value in the insn.
110 (extract_u16_loop): Do not negate the returned value.
111 (D16_LOOP): Add V850_INVERSE_PCREL flag.
113 (ceilf.sw): Remove duplicate entry.
114 (cvtf.hs): New entry.
120 (maddf.s): Restrict to E3V5 architectures.
122 (nmaddf.s): Likewise.
123 (nmsubf.s): Likewise.
125 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
127 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
129 (print_insn): Pass sizeflag to get_sib.
131 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
134 * tic6x-dis.c: Add support for displaying 16-bit insns.
136 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
139 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
140 individual msb and lsb halves in src1 & src2 fields. Discard the
141 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
142 follow what Ti SDK does in that case as any value in the src1
143 field yields the same output with SDK disassembler.
145 2013-03-12 Michael Eager <eager@eagercon.com>
147 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
149 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
151 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
153 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
155 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
157 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
159 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
161 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
163 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
164 (thumb32_opcodes): Likewise.
165 (print_insn_thumb32): Handle 'S' control char.
167 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
169 * lm32-desc.c: Regenerate.
171 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
173 * i386-reg.tbl (riz): Add RegRex64.
174 * i386-tbl.h: Regenerated.
176 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
178 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
179 (aarch64_feature_crc): New static.
181 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
182 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
183 * aarch64-asm-2.c: Re-generate.
184 * aarch64-dis-2.c: Ditto.
185 * aarch64-opc-2.c: Ditto.
187 2013-02-27 Alan Modra <amodra@gmail.com>
189 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
190 * rl78-decode.c: Regenerate.
192 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
194 * rl78-decode.opc: Fix encoding of DIVWU insn.
195 * rl78-decode.c: Regenerate.
197 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
200 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
202 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
203 (cpu_flags): Add CpuSMAP.
205 * i386-opc.h (CpuSMAP): New.
206 (i386_cpu_flags): Add cpusmap.
208 * i386-opc.tbl: Add clac and stac.
210 * i386-init.h: Regenerated.
211 * i386-tbl.h: Likewise.
213 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
215 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
216 which also makes the disassembler output be in little
217 endian like it should be.
219 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
221 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
223 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
225 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
227 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
228 section disassembled.
230 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
232 * arm-dis.c: Update strht pattern.
234 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
236 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
237 single-float. Disable ll, lld, sc and scd for EE. Disable the
238 trunc.w.s macro for EE.
240 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
241 Andrew Jenner <andrew@codesourcery.com>
243 Based on patches from Altera Corporation.
245 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
247 * Makefile.in: Regenerated.
248 * configure.in: Add case for bfd_nios2_arch.
249 * configure: Regenerated.
250 * disassemble.c (ARCH_nios2): Define.
251 (disassembler): Add case for bfd_arch_nios2.
252 * nios2-dis.c: New file.
253 * nios2-opc.c: New file.
255 2013-02-04 Alan Modra <amodra@gmail.com>
257 * po/POTFILES.in: Regenerate.
258 * rl78-decode.c: Regenerate.
259 * rx-decode.c: Regenerate.
261 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
263 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
264 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
265 * aarch64-asm.c (convert_xtl_to_shll): New function.
266 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
267 calling convert_xtl_to_shll.
268 * aarch64-dis.c (convert_shll_to_xtl): New function.
269 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
270 calling convert_shll_to_xtl.
271 * aarch64-gen.c: Update copyright year.
272 * aarch64-asm-2.c: Re-generate.
273 * aarch64-dis-2.c: Re-generate.
274 * aarch64-opc-2.c: Re-generate.
276 2013-01-24 Nick Clifton <nickc@redhat.com>
278 * v850-dis.c: Add support for e3v5 architecture.
279 * v850-opc.c: Likewise.
281 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
283 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
284 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
285 * aarch64-opc.c (operand_general_constraint_met_p): For
286 AARCH64_MOD_LSL, move the range check on the shift amount before the
287 alignment check; change to call set_sft_amount_out_of_range_error
288 instead of set_imm_out_of_range_error.
289 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
290 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
291 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
294 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
296 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
298 * i386-init.h: Regenerated.
299 * i386-tbl.h: Likewise.
301 2013-01-15 Nick Clifton <nickc@redhat.com>
303 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
305 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
307 2013-01-14 Will Newton <will.newton@imgtec.com>
309 * metag-dis.c (REG_WIDTH): Increase to 64.
311 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
313 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
314 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
315 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
317 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
318 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
319 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
320 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
322 2013-01-10 Will Newton <will.newton@imgtec.com>
324 * Makefile.am: Add Meta.
325 * configure.in: Add Meta.
326 * disassemble.c: Add Meta support.
327 * metag-dis.c: New file.
328 * Makefile.in: Regenerate.
329 * configure: Regenerate.
331 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
333 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
334 (match_opcode): Rename to cr16_match_opcode.
336 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
338 * mips-dis.c: Add names for CP0 registers of r5900.
339 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
340 instructions sq and lq.
341 Add support for MIPS r5900 CPU.
342 Add support for 128 bit MMI (Multimedia Instructions).
343 Add support for EE instructions (Emotion Engine).
344 Disable unsupported floating point instructions (64 bit and
345 undefined compare operations).
346 Enable instructions of MIPS ISA IV which are supported by r5900.
347 Disable 64 bit co processor instructions.
348 Disable 64 bit multiplication and division instructions.
349 Disable instructions for co-processor 2 and 3, because these are
350 not supported (preparation for later VU0 support (Vector Unit)).
351 Disable cvt.w.s because this behaves like trunc.w.s and the
352 correct execution can't be ensured on r5900.
353 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
354 will confuse less developers and compilers.
356 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
358 * aarch64-opc.c (aarch64_print_operand): Change to print
359 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
361 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
362 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
365 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
367 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
368 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
370 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
372 * i386-gen.c (process_copyright): Update copyright year to 2013.
374 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
376 * cr16-dis.c (match_opcode,make_instruction): Remove static
378 (dwordU,wordU): Moved typedefs to opcode/cr16.h
379 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
381 For older changes see ChangeLog-2012
383 Copyright (C) 2013 Free Software Foundation, Inc.
385 Copying and distribution of this file, with or without modification,
386 are permitted in any medium without royalty provided the copyright
387 notice and this notice are preserved.
393 version-control: never