1 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
2 Kirill Yukhin <kirill.yukhin@intel.com>
3 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
5 * i386-dis.c (BND_Fixup): New.
12 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
14 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
15 (dis tables): Replace XX with BND for near branch and call
17 (prefix_table): Add new entries.
18 (mod_table): Likewise.
20 (intel_names_bnd): New.
23 (prefix_name): Handle BND_PREFIX.
24 (print_insn): Initialize names_bnd.
25 (intel_operand_size): Handle new modes.
26 (OP_E_register): Likewise.
27 (OP_E_memory): Likewise.
29 * i386-gen.c (cpu_flag_init): Add CpuMPX.
30 (cpu_flags): Add CpuMPX.
31 (operand_type_init): Add RegBND.
32 (opcode_modifiers): Add BNDPrefixOk.
33 (operand_types): Add RegBND.
34 * i386-init.h: Regenerate.
35 * i386-opc.h (CpuMPX): New.
36 (CpuUnused): Comment out.
37 (i386_cpu_flags): Add cpumpx.
39 (i386_opcode_modifier): Add bndprefixok.
41 (i386_operand_type): Add regbnd.
42 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
43 Add MPX instructions and bnd prefix.
44 * i386-reg.tbl: Add bnd0-bnd3 registers.
45 * i386-tbl.h: Regenerate.
47 2013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
49 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
52 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
54 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
56 * Makefile.in: Regenerate.
57 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
60 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
62 * mips16-opc.c: Include mips-formats.h.
63 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
65 (decode_mips16_operand): New function.
66 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
67 (print_insn_arg): Handle OP_ENTRY_EXIT list.
68 Abort for OP_SAVE_RESTORE_LIST.
69 (print_mips16_insn_arg): Change interface. Use mips_operand
70 structures. Delete GET_OP_S. Move GET_OP definition to...
71 (print_insn_mips16): ...here. Call init_print_arg_state.
72 Update the call to print_mips16_insn_arg.
74 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
76 * mips-formats.h: New file.
77 * mips-opc.c: Include mips-formats.h.
78 (reg_0_map): New static array.
79 (decode_mips_operand): New function.
80 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
81 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
82 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
83 (int_c_map): New static arrays.
84 (decode_micromips_operand): New function.
85 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
86 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
87 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
88 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
89 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
90 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
91 (micromips_imm_b_map, micromips_imm_c_map): Delete.
92 (print_reg): New function.
93 (mips_print_arg_state): New structure.
94 (init_print_arg_state, print_insn_arg): New functions.
95 (print_insn_args): Change interface and use mips_operand structures.
96 Delete GET_OP_S. Move GET_OP definition to...
97 (print_insn_mips): ...here. Update the call to print_insn_args.
98 (print_insn_micromips): Use print_insn_args.
100 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
102 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
105 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
107 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
108 ADDA.S, MULA.S and SUBA.S.
110 2013-07-08 H.J. Lu <hongjiu.lu@intel.com>
113 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
114 * i386-tbl.h: Regenerated.
116 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
118 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
119 and SD A(B) macros up.
120 * micromips-opc.c (micromips_opcodes): Likewise.
122 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
124 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
127 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
129 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
130 MDMX-like instructions.
131 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
132 printing "Q" operands for INSN_5400 instructions.
134 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
136 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
138 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
141 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
143 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
145 * mips16-opc.c (mips16_opcodes): Likewise.
146 * micromips-opc.c (micromips_opcodes): Likewise.
147 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
148 (print_insn_mips16): Handle "+i".
149 (print_insn_micromips): Likewise. Conditionally preserve the
150 ISA bit for "a" but not for "+i".
152 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
154 * micromips-opc.c (WR_mhi): Rename to..
156 (micromips_opcodes): Update "movep" entry accordingly. Replace
158 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
159 (micromips_to_32_reg_h_map1): ...this.
160 (micromips_to_32_reg_i_map): Rename to...
161 (micromips_to_32_reg_h_map2): ...this.
162 (print_micromips_insn): Remove "mi" case. Print both registers
163 in the pair for "mh".
165 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
167 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
168 * micromips-opc.c (micromips_opcodes): Likewise.
169 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
170 and "+T" handling. Check for a "0" suffix when deciding whether to
171 use coprocessor 0 names. In that case, also check for ",H" selectors.
173 2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
175 * s390-opc.c (J12_12, J24_24): New macros.
176 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
177 (MASK_MII_UPI): Rename to MASK_MII_UPP.
178 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
180 2013-07-04 Alan Modra <amodra@gmail.com>
182 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
184 2013-06-26 Nick Clifton <nickc@redhat.com>
186 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
187 field when checking for type 2 nop.
188 * rx-decode.c: Regenerate.
190 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
192 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
195 2013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
197 * mips-dis.c (is_mips16_plt_tail): New function.
198 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
200 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
202 2013-06-21 DJ Delorie <dj@redhat.com>
204 * msp430-decode.opc: New.
205 * msp430-decode.c: New/generated.
206 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
207 (MAINTAINER_CLEANFILES): Likewise.
208 Add rule to build msp430-decode.c frommsp430decode.opc
209 using the opc2c program.
210 * Makefile.in: Regenerate.
211 * configure.in: Add msp430-decode.lo to msp430 architecture files.
212 * configure: Regenerate.
214 2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
216 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
217 (SYMTAB_AVAILABLE): Removed.
218 (#include "elf/aarch64.h): Ditto.
220 2013-06-17 Catherine Moore <clm@codesourcery.com>
221 Maciej W. Rozycki <macro@codesourcery.com>
222 Chao-Ying Fu <fu@mips.com>
224 * micromips-opc.c (EVA): Define.
226 (micromips_opcodes): Add EVA opcodes.
227 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
228 (print_insn_args): Handle EVA offsets.
229 (print_insn_micromips): Likewise.
230 * mips-opc.c (EVA): Define.
232 (mips_builtin_opcodes): Add EVA opcodes.
234 2013-06-17 Alan Modra <amodra@gmail.com>
236 * Makefile.am (mips-opc.lo): Add rules to create automatic
237 dependency files. Pass archdefs.
238 (micromips-opc.lo, mips16-opc.lo): Likewise.
239 * Makefile.in: Regenerate.
241 2013-06-14 DJ Delorie <dj@redhat.com>
243 * rx-decode.opc (rx_decode_opcode): Bit operations on
244 registers are 32-bit operations, not 8-bit operations.
245 * rx-decode.c: Regenerate.
247 2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
249 * micromips-opc.c (IVIRT): New define.
250 (IVIRT64): New define.
251 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
252 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
254 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
255 dmtgc0 to print cp0 names.
257 2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
259 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
262 2013-06-08 Catherine Moore <clm@codesourcery.com>
263 Richard Sandiford <rdsandiford@googlemail.com>
265 * micromips-opc.c (D32, D33, MC): Update definitions.
266 (micromips_opcodes): Initialize ase field.
267 * mips-dis.c (mips_arch_choice): Add ase field.
268 (mips_arch_choices): Initialize ase field.
269 (set_default_mips_dis_options): Declare and setup mips_ase.
270 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
271 MT32, MC): Update definitions.
272 (mips_builtin_opcodes): Initialize ase field.
274 2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
276 * s390-opc.txt (flogr): Require a register pair destination.
278 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
280 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
283 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
285 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
287 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
289 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
290 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
291 XLS_MASK, PPCVSX2): New defines.
292 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
293 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
294 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
295 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
296 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
297 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
298 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
299 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
300 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
301 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
302 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
303 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
304 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
305 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
306 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
307 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
308 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
309 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
310 <lxvx, stxvx>: New extended mnemonics.
312 2013-05-17 Alan Modra <amodra@gmail.com>
314 * ia64-raw.tbl: Replace non-ASCII char.
315 * ia64-waw.tbl: Likewise.
316 * ia64-asmtab.c: Regenerate.
318 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
320 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
321 * i386-init.h: Regenerated.
323 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
325 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
326 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
327 check from [0, 255] to [-128, 255].
329 2013-05-09 Andrew Pinski <apinski@cavium.com>
331 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
332 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
333 (parse_mips_dis_option): Handle the virt option.
334 (print_insn_args): Handle "+J".
335 (print_mips_disassembler_options): Print out message about virt64.
336 * mips-opc.c (IVIRT): New define.
337 (IVIRT64): New define.
338 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
339 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
340 Move rfe to the bottom as it conflicts with tlbgp.
342 2013-05-09 Alan Modra <amodra@gmail.com>
344 * ppc-opc.c (extract_vlesi): Properly sign extend.
345 (extract_vlensi): Likewise. Comment reason for setting invalid.
347 2013-05-02 Nick Clifton <nickc@redhat.com>
349 * msp430-dis.c: Add support for MSP430X instructions.
351 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
353 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
356 2013-04-17 Wei-chen Wang <cole945@gmail.com>
359 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
361 (hash_insns_list): Likewise.
363 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
365 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
368 2013-04-08 Jan Beulich <jbeulich@suse.com>
370 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
371 * i386-tbl.h: Re-generate.
373 2013-04-06 David S. Miller <davem@davemloft.net>
375 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
376 of an opcode, prefer the one with F_PREFERRED set.
377 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
378 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
379 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
380 mark existing mnenomics as aliases. Add "cc" suffix to edge
381 instructions generating condition codes, mark existing mnenomics
382 as aliases. Add "fp" prefix to VIS compare instructions, mark
383 existing mnenomics as aliases.
385 2013-04-03 Nick Clifton <nickc@redhat.com>
387 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
388 destination address by subtracting the operand from the current
390 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
391 a positive value in the insn.
392 (extract_u16_loop): Do not negate the returned value.
393 (D16_LOOP): Add V850_INVERSE_PCREL flag.
395 (ceilf.sw): Remove duplicate entry.
396 (cvtf.hs): New entry.
402 (maddf.s): Restrict to E3V5 architectures.
404 (nmaddf.s): Likewise.
405 (nmsubf.s): Likewise.
407 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
409 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
411 (print_insn): Pass sizeflag to get_sib.
413 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
416 * tic6x-dis.c: Add support for displaying 16-bit insns.
418 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
421 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
422 individual msb and lsb halves in src1 & src2 fields. Discard the
423 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
424 follow what Ti SDK does in that case as any value in the src1
425 field yields the same output with SDK disassembler.
427 2013-03-12 Michael Eager <eager@eagercon.com>
429 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
431 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
433 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
435 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
437 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
439 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
441 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
443 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
445 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
446 (thumb32_opcodes): Likewise.
447 (print_insn_thumb32): Handle 'S' control char.
449 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
451 * lm32-desc.c: Regenerate.
453 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
455 * i386-reg.tbl (riz): Add RegRex64.
456 * i386-tbl.h: Regenerated.
458 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
460 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
461 (aarch64_feature_crc): New static.
463 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
464 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
465 * aarch64-asm-2.c: Re-generate.
466 * aarch64-dis-2.c: Ditto.
467 * aarch64-opc-2.c: Ditto.
469 2013-02-27 Alan Modra <amodra@gmail.com>
471 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
472 * rl78-decode.c: Regenerate.
474 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
476 * rl78-decode.opc: Fix encoding of DIVWU insn.
477 * rl78-decode.c: Regenerate.
479 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
482 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
484 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
485 (cpu_flags): Add CpuSMAP.
487 * i386-opc.h (CpuSMAP): New.
488 (i386_cpu_flags): Add cpusmap.
490 * i386-opc.tbl: Add clac and stac.
492 * i386-init.h: Regenerated.
493 * i386-tbl.h: Likewise.
495 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
497 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
498 which also makes the disassembler output be in little
499 endian like it should be.
501 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
503 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
505 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
507 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
509 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
510 section disassembled.
512 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
514 * arm-dis.c: Update strht pattern.
516 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
518 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
519 single-float. Disable ll, lld, sc and scd for EE. Disable the
520 trunc.w.s macro for EE.
522 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
523 Andrew Jenner <andrew@codesourcery.com>
525 Based on patches from Altera Corporation.
527 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
529 * Makefile.in: Regenerated.
530 * configure.in: Add case for bfd_nios2_arch.
531 * configure: Regenerated.
532 * disassemble.c (ARCH_nios2): Define.
533 (disassembler): Add case for bfd_arch_nios2.
534 * nios2-dis.c: New file.
535 * nios2-opc.c: New file.
537 2013-02-04 Alan Modra <amodra@gmail.com>
539 * po/POTFILES.in: Regenerate.
540 * rl78-decode.c: Regenerate.
541 * rx-decode.c: Regenerate.
543 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
545 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
546 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
547 * aarch64-asm.c (convert_xtl_to_shll): New function.
548 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
549 calling convert_xtl_to_shll.
550 * aarch64-dis.c (convert_shll_to_xtl): New function.
551 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
552 calling convert_shll_to_xtl.
553 * aarch64-gen.c: Update copyright year.
554 * aarch64-asm-2.c: Re-generate.
555 * aarch64-dis-2.c: Re-generate.
556 * aarch64-opc-2.c: Re-generate.
558 2013-01-24 Nick Clifton <nickc@redhat.com>
560 * v850-dis.c: Add support for e3v5 architecture.
561 * v850-opc.c: Likewise.
563 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
565 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
566 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
567 * aarch64-opc.c (operand_general_constraint_met_p): For
568 AARCH64_MOD_LSL, move the range check on the shift amount before the
569 alignment check; change to call set_sft_amount_out_of_range_error
570 instead of set_imm_out_of_range_error.
571 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
572 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
573 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
576 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
578 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
580 * i386-init.h: Regenerated.
581 * i386-tbl.h: Likewise.
583 2013-01-15 Nick Clifton <nickc@redhat.com>
585 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
587 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
589 2013-01-14 Will Newton <will.newton@imgtec.com>
591 * metag-dis.c (REG_WIDTH): Increase to 64.
593 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
595 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
596 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
597 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
599 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
600 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
601 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
602 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
604 2013-01-10 Will Newton <will.newton@imgtec.com>
606 * Makefile.am: Add Meta.
607 * configure.in: Add Meta.
608 * disassemble.c: Add Meta support.
609 * metag-dis.c: New file.
610 * Makefile.in: Regenerate.
611 * configure: Regenerate.
613 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
615 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
616 (match_opcode): Rename to cr16_match_opcode.
618 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
620 * mips-dis.c: Add names for CP0 registers of r5900.
621 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
622 instructions sq and lq.
623 Add support for MIPS r5900 CPU.
624 Add support for 128 bit MMI (Multimedia Instructions).
625 Add support for EE instructions (Emotion Engine).
626 Disable unsupported floating point instructions (64 bit and
627 undefined compare operations).
628 Enable instructions of MIPS ISA IV which are supported by r5900.
629 Disable 64 bit co processor instructions.
630 Disable 64 bit multiplication and division instructions.
631 Disable instructions for co-processor 2 and 3, because these are
632 not supported (preparation for later VU0 support (Vector Unit)).
633 Disable cvt.w.s because this behaves like trunc.w.s and the
634 correct execution can't be ensured on r5900.
635 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
636 will confuse less developers and compilers.
638 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
640 * aarch64-opc.c (aarch64_print_operand): Change to print
641 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
643 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
644 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
647 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
649 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
650 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
652 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
654 * i386-gen.c (process_copyright): Update copyright year to 2013.
656 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
658 * cr16-dis.c (match_opcode,make_instruction): Remove static
660 (dwordU,wordU): Moved typedefs to opcode/cr16.h
661 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
663 For older changes see ChangeLog-2012
665 Copyright (C) 2013 Free Software Foundation, Inc.
667 Copying and distribution of this file, with or without modification,
668 are permitted in any medium without royalty provided the copyright
669 notice and this notice are preserved.
675 version-control: never