1 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
3 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
5 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
6 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
7 * testsuite/ld-arm/tls-longplt.d: Likewise.
9 2018-06-29 Tamar Christina <tamar.christina@arm.com>
12 * aarch64-asm-2.c: Regenerate.
13 * aarch64-dis-2.c: Likewise.
14 * aarch64-opc-2.c: Likewise.
15 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
16 * aarch64-opc.c (operand_general_constraint_met_p,
17 aarch64_print_operand): Likewise.
18 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
19 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
21 (AARCH64_OPERANDS): Add Em2.
23 2018-06-26 Nick Clifton <nickc@redhat.com>
25 * po/uk.po: Updated Ukranian translation.
26 * po/de.po: Updated German translation.
27 * po/pt_BR.po: Updated Brazilian Portuguese translation.
29 2018-06-26 Nick Clifton <nickc@redhat.com>
31 * nfp-dis.c: Fix spelling mistake.
33 2018-06-24 Nick Clifton <nickc@redhat.com>
35 * configure: Regenerate.
36 * po/opcodes.pot: Regenerate.
38 2018-06-24 Nick Clifton <nickc@redhat.com>
42 2018-06-19 Tamar Christina <tamar.christina@arm.com>
44 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
45 * aarch64-asm-2.c: Regenerate.
46 * aarch64-dis-2.c: Likewise.
48 2018-06-21 Maciej W. Rozycki <macro@mips.com>
50 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
51 `-M ginv' option description.
53 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
56 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
59 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
61 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
62 * configure.ac: Remove AC_PREREQ.
63 * Makefile.in: Re-generate.
64 * aclocal.m4: Re-generate.
65 * configure: Re-generate.
67 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
69 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
71 (parse_mips_ase_option): Handle -Mginv option.
72 (print_mips_disassembler_options): Document -Mginv.
73 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
75 (mips_opcodes): Define ginvi and ginvt.
77 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
78 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
80 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
81 * mips-opc.c (CRC, CRC64): New macros.
82 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
83 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
86 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
89 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
90 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
92 2018-06-06 Alan Modra <amodra@gmail.com>
94 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
95 setjmp. Move init for some other vars later too.
97 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
99 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
100 (dis_private): Add new fields for property section tracking.
101 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
102 (xtensa_instruction_fits): New functions.
103 (fetch_data): Bump minimal fetch size to 4.
104 (print_insn_xtensa): Make struct dis_private static.
105 Load and prepare property table on section change.
106 Don't disassemble literals. Don't disassemble instructions that
107 cross property table boundaries.
109 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
111 * configure: Regenerated.
113 2018-06-01 Jan Beulich <jbeulich@suse.com>
115 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
116 * i386-tbl.h: Re-generate.
118 2018-06-01 Jan Beulich <jbeulich@suse.com>
120 * i386-opc.tbl (sldt, str): Add NoRex64.
121 * i386-tbl.h: Re-generate.
123 2018-06-01 Jan Beulich <jbeulich@suse.com>
125 * i386-opc.tbl (invpcid): Add Oword.
126 * i386-tbl.h: Re-generate.
128 2018-06-01 Alan Modra <amodra@gmail.com>
130 * sysdep.h (_bfd_error_handler): Don't declare.
131 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
132 * rl78-decode.opc: Likewise.
133 * msp430-decode.c: Regenerate.
134 * rl78-decode.c: Regenerate.
136 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
138 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
139 * i386-init.h : Regenerated.
141 2018-05-25 Alan Modra <amodra@gmail.com>
143 * Makefile.in: Regenerate.
144 * po/POTFILES.in: Regenerate.
146 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
148 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
149 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
150 (insert_bab, extract_bab, insert_btab, extract_btab,
151 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
152 (BAT, BBA VBA RBS XB6S): Delete macros.
153 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
154 (BB, BD, RBX, XC6): Update for new macros.
155 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
156 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
157 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
158 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
160 2018-05-18 John Darrington <john@darrington.wattle.id.au>
162 * Makefile.am: Add support for s12z architecture.
163 * configure.ac: Likewise.
164 * disassemble.c: Likewise.
165 * disassemble.h: Likewise.
166 * Makefile.in: Regenerate.
167 * configure: Regenerate.
168 * s12z-dis.c: New file.
171 2018-05-18 Alan Modra <amodra@gmail.com>
173 * nfp-dis.c: Don't #include libbfd.h.
174 (init_nfp3200_priv): Use bfd_get_section_contents.
175 (nit_nfp6000_mecsr_sec): Likewise.
177 2018-05-17 Nick Clifton <nickc@redhat.com>
179 * po/zh_CN.po: Updated simplified Chinese translation.
181 2018-05-16 Tamar Christina <tamar.christina@arm.com>
184 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
185 * aarch64-dis-2.c: Regenerate.
187 2018-05-15 Tamar Christina <tamar.christina@arm.com>
190 * aarch64-asm.c (opintl.h): Include.
191 (aarch64_ins_sysreg): Enforce read/write constraints.
192 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
193 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
194 (F_REG_READ, F_REG_WRITE): New.
195 * aarch64-opc.c (aarch64_print_operand): Generate notes for
197 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
198 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
199 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
200 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
201 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
202 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
203 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
204 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
205 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
206 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
207 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
208 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
209 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
210 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
211 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
212 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
213 msr (F_SYS_WRITE), mrs (F_SYS_READ).
215 2018-05-15 Tamar Christina <tamar.christina@arm.com>
218 * aarch64-dis.c (no_notes: New.
219 (parse_aarch64_dis_option): Support notes.
220 (aarch64_decode_insn, print_operands): Likewise.
221 (print_aarch64_disassembler_options): Document notes.
222 * aarch64-opc.c (aarch64_print_operand): Support notes.
224 2018-05-15 Tamar Christina <tamar.christina@arm.com>
227 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
228 and take error struct.
229 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
230 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
231 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
232 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
233 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
234 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
235 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
236 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
237 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
238 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
239 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
240 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
241 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
242 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
243 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
244 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
245 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
246 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
247 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
248 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
249 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
250 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
251 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
252 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
253 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
254 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
255 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
256 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
257 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
258 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
259 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
260 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
261 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
262 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
263 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
264 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
265 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
266 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
267 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
268 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
269 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
270 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
271 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
272 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
273 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
274 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
275 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
276 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
277 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
278 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
279 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
280 (determine_disassembling_preference, aarch64_decode_insn,
281 print_insn_aarch64_word, print_insn_data): Take errors struct.
282 (print_insn_aarch64): Use errors.
283 * aarch64-asm-2.c: Regenerate.
284 * aarch64-dis-2.c: Regenerate.
285 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
286 boolean in aarch64_insert_operan.
287 (print_operand_extractor): Likewise.
288 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
290 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
292 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
294 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
296 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
298 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
300 * cr16-opc.c (cr16_instruction): Comment typo fix.
301 * hppa-dis.c (print_insn_hppa): Likewise.
303 2018-05-08 Jim Wilson <jimw@sifive.com>
305 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
306 (match_c_slli64, match_srxi_as_c_srxi): New.
307 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
308 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
309 <c.slli, c.srli, c.srai>: Use match_s_slli.
310 <c.slli64, c.srli64, c.srai64>: New.
312 2018-05-08 Alan Modra <amodra@gmail.com>
314 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
315 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
316 partition opcode space for index lookup.
318 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
320 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
321 <insn_length>: ...with this. Update usage.
322 Remove duplicate call to *info->memory_error_func.
324 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
325 H.J. Lu <hongjiu.lu@intel.com>
327 * i386-dis.c (Gva): New.
328 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
329 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
330 (prefix_table): New instructions (see prefix above).
331 (mod_table): New instructions (see prefix above).
332 (OP_G): Handle va_mode.
333 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
335 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
336 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
337 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
338 * i386-opc.tbl: Add movidir{i,64b}.
339 * i386-init.h: Regenerated.
340 * i386-tbl.h: Likewise.
342 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
344 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
346 * i386-opc.h (AddrPrefixOp0): Renamed to ...
347 (AddrPrefixOpReg): This.
348 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
349 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
351 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
353 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
354 (vle_num_opcodes): Likewise.
355 (spe2_num_opcodes): Likewise.
356 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
358 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
359 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
362 2018-05-01 Tamar Christina <tamar.christina@arm.com>
364 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
366 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
368 Makefile.am: Added nfp-dis.c.
369 configure.ac: Added bfd_nfp_arch.
370 disassemble.h: Added print_insn_nfp prototype.
371 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
372 nfp-dis.c: New, for NFP support.
373 po/POTFILES.in: Added nfp-dis.c to the list.
374 Makefile.in: Regenerate.
375 configure: Regenerate.
377 2018-04-26 Jan Beulich <jbeulich@suse.com>
379 * i386-opc.tbl: Fold various non-memory operand AVX512VL
380 templates into their base ones.
381 * i386-tlb.h: Re-generate.
383 2018-04-26 Jan Beulich <jbeulich@suse.com>
385 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
386 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
387 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
388 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
389 * i386-init.h: Re-generate.
391 2018-04-26 Jan Beulich <jbeulich@suse.com>
393 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
394 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
395 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
396 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
398 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
400 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
402 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
403 cpuregzmm, and cpuregmask.
404 * i386-init.h: Re-generate.
405 * i386-tbl.h: Re-generate.
407 2018-04-26 Jan Beulich <jbeulich@suse.com>
409 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
410 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
411 * i386-init.h: Re-generate.
413 2018-04-26 Jan Beulich <jbeulich@suse.com>
415 * i386-gen.c (VexImmExt): Delete.
416 * i386-opc.h (VexImmExt, veximmext): Delete.
417 * i386-opc.tbl: Drop all VexImmExt uses.
418 * i386-tlb.h: Re-generate.
420 2018-04-25 Jan Beulich <jbeulich@suse.com>
422 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
424 * i386-tlb.h: Re-generate.
426 2018-04-25 Tamar Christina <tamar.christina@arm.com>
428 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
430 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
432 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
434 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
435 (cpu_flags): Add CpuCLDEMOTE.
436 * i386-init.h: Regenerate.
437 * i386-opc.h (enum): Add CpuCLDEMOTE,
438 (i386_cpu_flags): Add cpucldemote.
439 * i386-opc.tbl: Add cldemote.
440 * i386-tbl.h: Regenerate.
442 2018-04-16 Alan Modra <amodra@gmail.com>
444 * Makefile.am: Remove sh5 and sh64 support.
445 * configure.ac: Likewise.
446 * disassemble.c: Likewise.
447 * disassemble.h: Likewise.
448 * sh-dis.c: Likewise.
449 * sh64-dis.c: Delete.
450 * sh64-opc.c: Delete.
451 * sh64-opc.h: Delete.
452 * Makefile.in: Regenerate.
453 * configure: Regenerate.
454 * po/POTFILES.in: Regenerate.
456 2018-04-16 Alan Modra <amodra@gmail.com>
458 * Makefile.am: Remove w65 support.
459 * configure.ac: Likewise.
460 * disassemble.c: Likewise.
461 * disassemble.h: Likewise.
464 * Makefile.in: Regenerate.
465 * configure: Regenerate.
466 * po/POTFILES.in: Regenerate.
468 2018-04-16 Alan Modra <amodra@gmail.com>
470 * configure.ac: Remove we32k support.
471 * configure: Regenerate.
473 2018-04-16 Alan Modra <amodra@gmail.com>
475 * Makefile.am: Remove m88k support.
476 * configure.ac: Likewise.
477 * disassemble.c: Likewise.
478 * disassemble.h: Likewise.
479 * m88k-dis.c: Delete.
480 * Makefile.in: Regenerate.
481 * configure: Regenerate.
482 * po/POTFILES.in: Regenerate.
484 2018-04-16 Alan Modra <amodra@gmail.com>
486 * Makefile.am: Remove i370 support.
487 * configure.ac: Likewise.
488 * disassemble.c: Likewise.
489 * disassemble.h: Likewise.
490 * i370-dis.c: Delete.
491 * i370-opc.c: Delete.
492 * Makefile.in: Regenerate.
493 * configure: Regenerate.
494 * po/POTFILES.in: Regenerate.
496 2018-04-16 Alan Modra <amodra@gmail.com>
498 * Makefile.am: Remove h8500 support.
499 * configure.ac: Likewise.
500 * disassemble.c: Likewise.
501 * disassemble.h: Likewise.
502 * h8500-dis.c: Delete.
503 * h8500-opc.h: Delete.
504 * Makefile.in: Regenerate.
505 * configure: Regenerate.
506 * po/POTFILES.in: Regenerate.
508 2018-04-16 Alan Modra <amodra@gmail.com>
510 * configure.ac: Remove tahoe support.
511 * configure: Regenerate.
513 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
515 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
517 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
519 * i386-tbl.h: Regenerated.
521 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
523 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
524 PREFIX_MOD_1_0FAE_REG_6.
526 (OP_E_register): Use va_mode.
527 * i386-dis-evex.h (prefix_table):
528 New instructions (see prefixes above).
529 * i386-gen.c (cpu_flag_init): Add WAITPKG.
530 (cpu_flags): Likewise.
531 * i386-opc.h (enum): Likewise.
532 (i386_cpu_flags): Likewise.
533 * i386-opc.tbl: Add umonitor, umwait, tpause.
534 * i386-init.h: Regenerate.
535 * i386-tbl.h: Likewise.
537 2018-04-11 Alan Modra <amodra@gmail.com>
539 * opcodes/i860-dis.c: Delete.
540 * opcodes/i960-dis.c: Delete.
541 * Makefile.am: Remove i860 and i960 support.
542 * configure.ac: Likewise.
543 * disassemble.c: Likewise.
544 * disassemble.h: Likewise.
545 * Makefile.in: Regenerate.
546 * configure: Regenerate.
547 * po/POTFILES.in: Regenerate.
549 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
552 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
554 (print_insn): Clear vex instead of vex.evex.
556 2018-04-04 Nick Clifton <nickc@redhat.com>
558 * po/es.po: Updated Spanish translation.
560 2018-03-28 Jan Beulich <jbeulich@suse.com>
562 * i386-gen.c (opcode_modifiers): Delete VecESize.
563 * i386-opc.h (VecESize): Delete.
564 (struct i386_opcode_modifier): Delete vecesize.
565 * i386-opc.tbl: Drop VecESize.
566 * i386-tlb.h: Re-generate.
568 2018-03-28 Jan Beulich <jbeulich@suse.com>
570 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
571 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
572 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
573 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
574 * i386-tlb.h: Re-generate.
576 2018-03-28 Jan Beulich <jbeulich@suse.com>
578 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
580 * i386-tlb.h: Re-generate.
582 2018-03-28 Jan Beulich <jbeulich@suse.com>
584 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
585 (vex_len_table): Drop Y for vcvt*2si.
586 (putop): Replace plain 'Y' handling by abort().
588 2018-03-28 Nick Clifton <nickc@redhat.com>
591 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
592 instructions with only a base address register.
593 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
594 handle AARHC64_OPND_SVE_ADDR_R.
595 (aarch64_print_operand): Likewise.
596 * aarch64-asm-2.c: Regenerate.
597 * aarch64_dis-2.c: Regenerate.
598 * aarch64-opc-2.c: Regenerate.
600 2018-03-22 Jan Beulich <jbeulich@suse.com>
602 * i386-opc.tbl: Drop VecESize from register only insn forms and
603 memory forms not allowing broadcast.
604 * i386-tlb.h: Re-generate.
606 2018-03-22 Jan Beulich <jbeulich@suse.com>
608 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
609 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
610 sha256*): Drop Disp<N>.
612 2018-03-22 Jan Beulich <jbeulich@suse.com>
614 * i386-dis.c (EbndS, bnd_swap_mode): New.
615 (prefix_table): Use EbndS.
616 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
617 * i386-opc.tbl (bndmov): Move misplaced Load.
618 * i386-tlb.h: Re-generate.
620 2018-03-22 Jan Beulich <jbeulich@suse.com>
622 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
623 templates allowing memory operands and folded ones for register
625 * i386-tlb.h: Re-generate.
627 2018-03-22 Jan Beulich <jbeulich@suse.com>
629 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
630 256-bit templates. Drop redundant leftover Disp<N>.
631 * i386-tlb.h: Re-generate.
633 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
635 * riscv-opc.c (riscv_insn_types): New.
637 2018-03-13 Nick Clifton <nickc@redhat.com>
639 * po/pt_BR.po: Updated Brazilian Portuguese translation.
641 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
643 * i386-opc.tbl: Add Optimize to clr.
644 * i386-tbl.h: Regenerated.
646 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
648 * i386-gen.c (opcode_modifiers): Remove OldGcc.
649 * i386-opc.h (OldGcc): Removed.
650 (i386_opcode_modifier): Remove oldgcc.
651 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
652 instructions for old (<= 2.8.1) versions of gcc.
653 * i386-tbl.h: Regenerated.
655 2018-03-08 Jan Beulich <jbeulich@suse.com>
657 * i386-opc.h (EVEXDYN): New.
658 * i386-opc.tbl: Fold various AVX512VL templates.
659 * i386-tlb.h: Re-generate.
661 2018-03-08 Jan Beulich <jbeulich@suse.com>
663 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
664 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
665 vpexpandd, vpexpandq): Fold AFX512VF templates.
666 * i386-tlb.h: Re-generate.
668 2018-03-08 Jan Beulich <jbeulich@suse.com>
670 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
671 Fold 128- and 256-bit VEX-encoded templates.
672 * i386-tlb.h: Re-generate.
674 2018-03-08 Jan Beulich <jbeulich@suse.com>
676 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
677 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
678 vpexpandd, vpexpandq): Fold AVX512F templates.
679 * i386-tlb.h: Re-generate.
681 2018-03-08 Jan Beulich <jbeulich@suse.com>
683 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
684 64-bit templates. Drop Disp<N>.
685 * i386-tlb.h: Re-generate.
687 2018-03-08 Jan Beulich <jbeulich@suse.com>
689 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
690 and 256-bit templates.
691 * i386-tlb.h: Re-generate.
693 2018-03-08 Jan Beulich <jbeulich@suse.com>
695 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
696 * i386-tlb.h: Re-generate.
698 2018-03-08 Jan Beulich <jbeulich@suse.com>
700 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
702 * i386-tlb.h: Re-generate.
704 2018-03-08 Jan Beulich <jbeulich@suse.com>
706 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
707 * i386-tlb.h: Re-generate.
709 2018-03-08 Jan Beulich <jbeulich@suse.com>
711 * i386-gen.c (opcode_modifiers): Delete FloatD.
712 * i386-opc.h (FloatD): Delete.
713 (struct i386_opcode_modifier): Delete floatd.
714 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
716 * i386-tlb.h: Re-generate.
718 2018-03-08 Jan Beulich <jbeulich@suse.com>
720 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
722 2018-03-08 Jan Beulich <jbeulich@suse.com>
724 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
725 * i386-tlb.h: Re-generate.
727 2018-03-08 Jan Beulich <jbeulich@suse.com>
729 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
731 * i386-tlb.h: Re-generate.
733 2018-03-07 Alan Modra <amodra@gmail.com>
735 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
737 * disassemble.h (print_insn_rs6000): Delete.
738 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
739 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
740 (print_insn_rs6000): Delete.
742 2018-03-03 Alan Modra <amodra@gmail.com>
744 * sysdep.h (opcodes_error_handler): Define.
745 (_bfd_error_handler): Declare.
746 * Makefile.am: Remove stray #.
747 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
749 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
750 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
751 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
752 opcodes_error_handler to print errors. Standardize error messages.
753 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
754 and include opintl.h.
755 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
756 * i386-gen.c: Standardize error messages.
757 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
758 * Makefile.in: Regenerate.
759 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
760 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
761 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
762 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
763 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
764 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
765 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
766 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
767 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
768 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
769 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
770 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
771 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
773 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
775 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
776 vpsub[bwdq] instructions.
777 * i386-tbl.h: Regenerated.
779 2018-03-01 Alan Modra <amodra@gmail.com>
781 * configure.ac (ALL_LINGUAS): Sort.
782 * configure: Regenerate.
784 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
786 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
787 macro by assignements.
789 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
792 * i386-gen.c (opcode_modifiers): Add Optimize.
793 * i386-opc.h (Optimize): New enum.
794 (i386_opcode_modifier): Add optimize.
795 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
796 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
797 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
798 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
799 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
801 * i386-tbl.h: Regenerated.
803 2018-02-26 Alan Modra <amodra@gmail.com>
805 * crx-dis.c (getregliststring): Allocate a large enough buffer
806 to silence false positive gcc8 warning.
808 2018-02-22 Shea Levy <shea@shealevy.com>
810 * disassemble.c (ARCH_riscv): Define if ARCH_all.
812 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
814 * i386-opc.tbl: Add {rex},
815 * i386-tbl.h: Regenerated.
817 2018-02-20 Maciej W. Rozycki <macro@mips.com>
819 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
820 (mips16_opcodes): Replace `M' with `m' for "restore".
822 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
824 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
826 2018-02-13 Maciej W. Rozycki <macro@mips.com>
828 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
829 variable to `function_index'.
831 2018-02-13 Nick Clifton <nickc@redhat.com>
834 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
835 about truncation of printing.
837 2018-02-12 Henry Wong <henry@stuffedcow.net>
839 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
841 2018-02-05 Nick Clifton <nickc@redhat.com>
843 * po/pt_BR.po: Updated Brazilian Portuguese translation.
845 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
847 * i386-dis.c (enum): Add pconfig.
848 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
849 (cpu_flags): Add CpuPCONFIG.
850 * i386-opc.h (enum): Add CpuPCONFIG.
851 (i386_cpu_flags): Add cpupconfig.
852 * i386-opc.tbl: Add PCONFIG instruction.
853 * i386-init.h: Regenerate.
854 * i386-tbl.h: Likewise.
856 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
858 * i386-dis.c (enum): Add PREFIX_0F09.
859 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
860 (cpu_flags): Add CpuWBNOINVD.
861 * i386-opc.h (enum): Add CpuWBNOINVD.
862 (i386_cpu_flags): Add cpuwbnoinvd.
863 * i386-opc.tbl: Add WBNOINVD instruction.
864 * i386-init.h: Regenerate.
865 * i386-tbl.h: Likewise.
867 2018-01-17 Jim Wilson <jimw@sifive.com>
869 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
871 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
873 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
874 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
875 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
876 (cpu_flags): Add CpuIBT, CpuSHSTK.
877 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
878 (i386_cpu_flags): Add cpuibt, cpushstk.
879 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
880 * i386-init.h: Regenerate.
881 * i386-tbl.h: Likewise.
883 2018-01-16 Nick Clifton <nickc@redhat.com>
885 * po/pt_BR.po: Updated Brazilian Portugese translation.
886 * po/de.po: Updated German translation.
888 2018-01-15 Jim Wilson <jimw@sifive.com>
890 * riscv-opc.c (match_c_nop): New.
891 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
893 2018-01-15 Nick Clifton <nickc@redhat.com>
895 * po/uk.po: Updated Ukranian translation.
897 2018-01-13 Nick Clifton <nickc@redhat.com>
899 * po/opcodes.pot: Regenerated.
901 2018-01-13 Nick Clifton <nickc@redhat.com>
903 * configure: Regenerate.
905 2018-01-13 Nick Clifton <nickc@redhat.com>
909 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
911 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
912 * i386-tbl.h: Regenerate.
914 2018-01-10 Jan Beulich <jbeulich@suse.com>
916 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
917 * i386-tbl.h: Re-generate.
919 2018-01-10 Jan Beulich <jbeulich@suse.com>
921 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
922 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
923 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
924 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
925 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
926 Disp8MemShift of AVX512VL forms.
927 * i386-tbl.h: Re-generate.
929 2018-01-09 Jim Wilson <jimw@sifive.com>
931 * riscv-dis.c (maybe_print_address): If base_reg is zero,
932 then the hi_addr value is zero.
934 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
936 * arm-dis.c (arm_opcodes): Add csdb.
937 (thumb32_opcodes): Add csdb.
939 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
941 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
942 * aarch64-asm-2.c: Regenerate.
943 * aarch64-dis-2.c: Regenerate.
944 * aarch64-opc-2.c: Regenerate.
946 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
949 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
950 Remove AVX512 vmovd with 64-bit operands.
951 * i386-tbl.h: Regenerated.
953 2018-01-05 Jim Wilson <jimw@sifive.com>
955 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
958 2018-01-03 Alan Modra <amodra@gmail.com>
960 Update year range in copyright notice of all files.
962 2018-01-02 Jan Beulich <jbeulich@suse.com>
964 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
965 and OPERAND_TYPE_REGZMM entries.
967 For older changes see ChangeLog-2017
969 Copyright (C) 2018 Free Software Foundation, Inc.
971 Copying and distribution of this file, with or without modification,
972 are permitted in any medium without royalty provided the copyright
973 notice and this notice are preserved.
979 version-control: never