1 2017-03-27 Rinat Zelig <rinat@mellanox.com>
3 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
4 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
5 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
6 (insert_nps_misc_imm_offset): New function.
7 (extract_nps_misc imm_offset): New function.
8 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
9 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
11 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
13 * s390-mkopc.c (main): Remove vx2 check.
14 * s390-opc.txt: Remove vx2 instruction flags.
16 2017-03-21 Rinat Zelig <rinat@mellanox.com>
18 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
19 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
20 (insert_nps_imm_offset): New function.
21 (extract_nps_imm_offset): New function.
22 (insert_nps_imm_entry): New function.
23 (extract_nps_imm_entry): New function.
25 2017-03-17 Alan Modra <amodra@gmail.com>
28 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
29 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
30 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
32 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
34 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
38 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
40 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
42 2017-03-13 Andrew Waterman <andrew@sifive.com>
44 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
49 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
51 * i386-gen.c (opcode_modifiers): Replace S with Load.
52 * i386-opc.h (S): Removed.
54 (i386_opcode_modifier): Replace s with load.
55 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
56 and {evex}. Replace S with Load.
57 * i386-tbl.h: Regenerated.
59 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
61 * i386-opc.tbl: Use CpuCET on rdsspq.
62 * i386-tbl.h: Regenerated.
64 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
66 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
67 <vsx>: Do not use PPC_OPCODE_VSX3;
69 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
71 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
73 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
75 * i386-dis.c (REG_0F1E_MOD_3): New enum.
76 (MOD_0F1E_PREFIX_1): Likewise.
77 (MOD_0F38F5_PREFIX_2): Likewise.
78 (MOD_0F38F6_PREFIX_0): Likewise.
79 (RM_0F1E_MOD_3_REG_7): Likewise.
80 (PREFIX_MOD_0_0F01_REG_5): Likewise.
81 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
82 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
83 (PREFIX_0F1E): Likewise.
84 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
85 (PREFIX_0F38F5): Likewise.
86 (dis386_twobyte): Use PREFIX_0F1E.
87 (reg_table): Add REG_0F1E_MOD_3.
88 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
89 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
90 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
91 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
92 (three_byte_table): Use PREFIX_0F38F5.
93 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
94 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
95 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
96 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
97 PREFIX_MOD_3_0F01_REG_5_RM_2.
98 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
99 (cpu_flags): Add CpuCET.
100 * i386-opc.h (CpuCET): New enum.
101 (CpuUnused): Commented out.
102 (i386_cpu_flags): Add cpucet.
103 * i386-opc.tbl: Add Intel CET instructions.
104 * i386-init.h: Regenerated.
105 * i386-tbl.h: Likewise.
107 2017-03-06 Alan Modra <amodra@gmail.com>
110 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
111 (extract_raq, extract_ras, extract_rbx): New functions.
112 (powerpc_operands): Use opposite corresponding insert function.
114 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
115 register restriction.
117 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
119 * disassemble.c Include "safe-ctype.h".
120 (disassemble_init_for_target): Handle s390 init.
121 (remove_whitespace_and_extra_commas): New function.
122 (disassembler_options_cmp): Likewise.
123 * arm-dis.c: Include "libiberty.h".
125 (regnames): Use long disassembler style names.
126 Add force-thumb and no-force-thumb options.
127 (NUM_ARM_REGNAMES): Rename from this...
128 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
129 (get_arm_regname_num_options): Delete.
130 (set_arm_regname_option): Likewise.
131 (get_arm_regnames): Likewise.
132 (parse_disassembler_options): Likewise.
133 (parse_arm_disassembler_option): Rename from this...
134 (parse_arm_disassembler_options): ...to this. Make static.
135 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
136 (print_insn): Use parse_arm_disassembler_options.
137 (disassembler_options_arm): New function.
138 (print_arm_disassembler_options): Handle updated regnames.
139 * ppc-dis.c: Include "libiberty.h".
140 (ppc_opts): Add "32" and "64" entries.
141 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
142 (powerpc_init_dialect): Add break to switch statement.
143 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
144 (disassembler_options_powerpc): New function.
145 (print_ppc_disassembler_options): Use ARRAY_SIZE.
146 Remove printing of "32" and "64".
147 * s390-dis.c: Include "libiberty.h".
148 (init_flag): Remove unneeded variable.
149 (struct s390_options_t): New structure type.
150 (options): New structure.
151 (init_disasm): Rename from this...
152 (disassemble_init_s390): ...to this. Add initializations for
153 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
154 (print_insn_s390): Delete call to init_disasm.
155 (disassembler_options_s390): New function.
156 (print_s390_disassembler_options): Print using information from
158 * po/opcodes.pot: Regenerate.
160 2017-02-28 Jan Beulich <jbeulich@suse.com>
162 * i386-dis.c (PCMPESTR_Fixup): New.
163 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
164 (prefix_table): Use PCMPESTR_Fixup.
165 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
167 (vex_w_table): Delete VPCMPESTR{I,M} entries.
168 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
169 Split 64-bit and non-64-bit variants.
170 * opcodes/i386-tbl.h: Re-generate.
172 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
174 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
175 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
176 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
177 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
178 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
179 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
180 (OP_SVE_V_HSD): New macros.
181 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
182 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
183 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
184 (aarch64_opcode_table): Add new SVE instructions.
185 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
186 for rotation operands. Add new SVE operands.
187 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
188 (ins_sve_quad_index): Likewise.
189 (ins_imm_rotate): Split into...
190 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
191 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
192 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
194 (aarch64_ins_sve_addr_ri_s4): New function.
195 (aarch64_ins_sve_quad_index): Likewise.
196 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
197 * aarch64-asm-2.c: Regenerate.
198 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
199 (ext_sve_quad_index): Likewise.
200 (ext_imm_rotate): Split into...
201 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
202 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
203 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
205 (aarch64_ext_sve_addr_ri_s4): New function.
206 (aarch64_ext_sve_quad_index): Likewise.
207 (aarch64_ext_sve_index): Allow quad indices.
208 (do_misc_decoding): Likewise.
209 * aarch64-dis-2.c: Regenerate.
210 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
212 (OPD_F_OD_MASK): Widen by one bit.
213 (OPD_F_NO_ZR): Bump accordingly.
214 (get_operand_field_width): New function.
215 * aarch64-opc.c (fields): Add new SVE fields.
216 (operand_general_constraint_met_p): Handle new SVE operands.
217 (aarch64_print_operand): Likewise.
218 * aarch64-opc-2.c: Regenerate.
220 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
222 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
223 (aarch64_feature_compnum): ...this.
224 (SIMD_V8_3): Replace with...
226 (CNUM_INSN): New macro.
227 (aarch64_opcode_table): Use it for the complex number instructions.
229 2017-02-24 Jan Beulich <jbeulich@suse.com>
231 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
233 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
235 Add support for associating SPARC ASIs with an architecture level.
236 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
237 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
238 decoding of SPARC ASIs.
240 2017-02-23 Jan Beulich <jbeulich@suse.com>
242 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
243 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
245 2017-02-21 Jan Beulich <jbeulich@suse.com>
247 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
248 1 (instead of to itself). Correct typo.
250 2017-02-14 Andrew Waterman <andrew@sifive.com>
252 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
255 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
257 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
258 (aarch64_sys_reg_supported_p): Handle them.
260 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
262 * arc-opc.c (UIMM6_20R): Define.
263 (SIMM12_20): Use above.
264 (SIMM12_20R): Define.
265 (SIMM3_5_S): Use above.
266 (UIMM7_A32_11R_S): Define.
267 (UIMM7_9_S): Use above.
268 (UIMM3_13R_S): Define.
269 (SIMM11_A32_7_S): Use above.
271 (UIMM10_A32_8_S): Use above.
272 (UIMM8_8R_S): Define.
274 (arc_relax_opcodes): Use all above defines.
276 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
278 * arc-regs.h: Distinguish some of the registers different on
279 ARC700 and HS38 cpus.
281 2017-02-14 Alan Modra <amodra@gmail.com>
284 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
285 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
287 2017-02-11 Stafford Horne <shorne@gmail.com>
288 Alan Modra <amodra@gmail.com>
290 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
291 Use insn_bytes_value and insn_int_value directly instead. Don't
292 free allocated memory until function exit.
294 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
296 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
298 2017-02-03 Nick Clifton <nickc@redhat.com>
301 * aarch64-opc.c (print_register_list): Ensure that the register
302 list index will fir into the tb buffer.
303 (print_register_offset_address): Likewise.
304 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
306 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
309 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
310 instructions when the previous fetch packet ends with a 32-bit
313 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
315 * pru-opc.c: Remove vague reference to a future GDB port.
317 2017-01-20 Nick Clifton <nickc@redhat.com>
319 * po/ga.po: Updated Irish translation.
321 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
323 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
325 2017-01-13 Yao Qi <yao.qi@linaro.org>
327 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
328 if FETCH_DATA returns 0.
329 (m68k_scan_mask): Likewise.
330 (print_insn_m68k): Update code to handle -1 return value.
332 2017-01-13 Yao Qi <yao.qi@linaro.org>
334 * m68k-dis.c (enum print_insn_arg_error): New.
335 (NEXTBYTE): Replace -3 with
336 PRINT_INSN_ARG_MEMORY_ERROR.
337 (NEXTULONG): Likewise.
338 (NEXTSINGLE): Likewise.
339 (NEXTDOUBLE): Likewise.
340 (NEXTDOUBLE): Likewise.
341 (NEXTPACKED): Likewise.
342 (FETCH_ARG): Likewise.
343 (FETCH_DATA): Update comments.
344 (print_insn_arg): Update comments. Replace magic numbers with
346 (match_insn_m68k): Likewise.
348 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
350 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
351 * i386-dis-evex.h (evex_table): Updated.
352 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
353 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
354 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
355 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
356 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
357 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
358 * i386-init.h: Regenerate.
361 2017-01-12 Yao Qi <yao.qi@linaro.org>
363 * msp430-dis.c (msp430_singleoperand): Return -1 if
364 msp430dis_opcode_signed returns false.
365 (msp430_doubleoperand): Likewise.
366 (msp430_branchinstr): Return -1 if
367 msp430dis_opcode_unsigned returns false.
368 (msp430x_calla_instr): Likewise.
369 (print_insn_msp430): Likewise.
371 2017-01-05 Nick Clifton <nickc@redhat.com>
374 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
375 could not be matched.
376 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
379 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
381 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
382 (aarch64_opcode_table): Use RCPC_INSN.
384 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
386 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
388 * riscv-opcodes/all-opcodes: Likewise.
390 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
392 * riscv-dis.c (print_insn_args): Add fall through comment.
394 2017-01-03 Nick Clifton <nickc@redhat.com>
396 * po/sr.po: New Serbian translation.
397 * configure.ac (ALL_LINGUAS): Add sr.
398 * configure: Regenerate.
400 2017-01-02 Alan Modra <amodra@gmail.com>
402 * epiphany-desc.h: Regenerate.
403 * epiphany-opc.h: Regenerate.
404 * fr30-desc.h: Regenerate.
405 * fr30-opc.h: Regenerate.
406 * frv-desc.h: Regenerate.
407 * frv-opc.h: Regenerate.
408 * ip2k-desc.h: Regenerate.
409 * ip2k-opc.h: Regenerate.
410 * iq2000-desc.h: Regenerate.
411 * iq2000-opc.h: Regenerate.
412 * lm32-desc.h: Regenerate.
413 * lm32-opc.h: Regenerate.
414 * m32c-desc.h: Regenerate.
415 * m32c-opc.h: Regenerate.
416 * m32r-desc.h: Regenerate.
417 * m32r-opc.h: Regenerate.
418 * mep-desc.h: Regenerate.
419 * mep-opc.h: Regenerate.
420 * mt-desc.h: Regenerate.
421 * mt-opc.h: Regenerate.
422 * or1k-desc.h: Regenerate.
423 * or1k-opc.h: Regenerate.
424 * xc16x-desc.h: Regenerate.
425 * xc16x-opc.h: Regenerate.
426 * xstormy16-desc.h: Regenerate.
427 * xstormy16-opc.h: Regenerate.
429 2017-01-02 Alan Modra <amodra@gmail.com>
431 Update year range in copyright notice of all files.
433 For older changes see ChangeLog-2016
435 Copyright (C) 2017 Free Software Foundation, Inc.
437 Copying and distribution of this file, with or without modification,
438 are permitted in any medium without royalty provided the copyright
439 notice and this notice are preserved.
445 version-control: never