1 2017-11-14 Jan Beulich <jbeulich@suse.com>
3 * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
4 (vex_len_table): Use VPCOM.
6 2017-11-14 Jan Beulich <jbeulich@suse.com>
8 * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
9 (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
10 * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
12 (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
13 vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
14 vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
15 vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
17 * i386-tbl.h: Re-generate.
19 2017-11-14 Jan Beulich <jbeulich@suse.com>
21 * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
22 smov, ssca, stos, ssto, xlat): Drop Disp*.
23 * i386-tbl.h: Re-generate.
25 2017-11-13 Jan Beulich <jbeulich@suse.com>
27 * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
28 xsaveopt64): Add No_qSuf.
29 * i386-tbl.h: Re-generate.
31 2017-11-09 Tamar Christina <tamar.christina@arm.com>
33 * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
34 dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
35 cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
37 (aarch64_sys_reg_supported_p): Likewise.
38 (aarch64_pstatefields): Add dit register.
39 (aarch64_pstatefield_supported_p): Likewise.
40 (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
41 vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
42 vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
43 rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
44 rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
45 ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
46 rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
48 2017-11-09 Tamar Christina <tamar.christina@arm.com>
50 * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
51 (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
52 (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
53 (QL_STLW, QL_STLX): New.
55 2017-11-09 Tamar Christina <tamar.christina@arm.com>
57 * aarch64-asm.h (ins_addr_offset): New.
58 * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
59 (aarch64_ins_addr_offset): New.
60 * aarch64-asm-2.c: Regenerate.
61 * aarch64-dis.h (ext_addr_offset): New.
62 * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
63 (aarch64_ext_addr_offset): New.
64 * aarch64-dis-2.c: Regenerate.
65 * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
66 FLD_imm4_2 and FLD_SM3_imm2.
67 * aarch64-opc.c (fields): Add FLD_imm6_2,
68 FLD_imm4_2 and FLD_SM3_imm2.
69 (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
70 (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
71 AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
72 * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
74 (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
76 2017-11-09 Tamar Christina <tamar.christina@arm.com>
79 (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
80 (aarch64_feature_sm4, aarch64_feature_sha3): New.
81 (aarch64_feature_fp_16_v8_2): New.
82 (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
83 (V8_4_INSN, CRYPTO_V8_2_INSN): New.
84 (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
86 2017-11-08 Tamar Christina <tamar.christina@arm.com>
88 * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
89 (aarch64_feature_sha2, aarch64_feature_aes): New.
91 (AES_INSN, SHA2_INSN): New.
92 (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
93 (sha1h, sha1su1, sha256su0, sha1c, sha1p,
94 sha1m, sha1su0, sha256h, sha256h2, sha256su1):
97 2017-11-08 Jiong Wang <jiong.wang@arm.com>
98 Tamar Christina <tamar.christina@arm.com>
100 * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
101 FP16 instructions, including vfmal.f16 and vfmsl.f16.
103 2017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
105 * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
107 2017-11-07 Alan Modra <amodra@gmail.com>
109 * opintl.h: Formatting, comment fixes.
110 (gettext, ngettext): Redefine when ENABLE_NLS.
111 (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
112 (_): Define using gettext.
113 (textdomain, bindtextdomain): Use safer "do nothing".
115 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
117 * arc-dis.c (print_hex): New variable.
118 (parse_option): Check for hex option.
119 (print_insn_arc): Use hexadecimal representation for short
120 immediate values when requested.
121 (print_arc_disassembler_options): Add hex option to the list.
123 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
125 * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
126 (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
127 (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
128 (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
129 (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
130 (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
131 (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
132 (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
133 (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
134 (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
135 (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
136 (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
137 (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
138 (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
139 (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
140 (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
141 (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
142 (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
143 (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
145 (prealloc, prefetch*): Place them before ld instruction.
146 * arc-opc.c (skip_this_opcode): Add ARITH class.
148 2017-10-25 Alan Modra <amodra@gmail.com>
151 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
152 (cr16_words, cr16_allWords, processing_argument_number): Likewise.
153 (imm4flag, size_changed): Likewise.
154 * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
155 (words, allWords, processing_argument_number): Likewise.
156 (cst4flag, size_changed): Likewise.
157 * crx-opc.c (crx_cst4_map): Rename from cst4_map.
158 (crx_cst4_maps): Rename from cst4_maps.
159 (crx_no_op_insn): Rename from no_op_insn.
161 2017-10-24 Andrew Waterman <andrew@sifive.com>
163 * riscv-opc.c (match_c_addi16sp) : New function.
164 (match_c_addi4spn): New function.
165 (match_c_lui): Don't allow 0-immediate encodings.
166 (riscv_opcodes) <addi>: Use the above functions.
168 <c.addi4spn>: Likewise.
169 <c.addi16sp>: Likewise.
171 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
173 * i386-init.h: Regenerate
174 * i386-tbl.h: Likewise
176 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
178 * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
179 (enum): Add EVEX_W_0F3854_P_2.
180 * i386-dis-evex.h (evex_table): Updated.
181 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
182 CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
183 (cpu_flags): Add CpuAVX512_BITALG.
184 * i386-opc.h (enum): Add CpuAVX512_BITALG.
185 (i386_cpu_flags): Add cpuavx512_bitalg..
186 * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
187 * i386-init.h: Regenerate.
188 * i386-tbl.h: Likewise.
190 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
192 * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
193 * i386-dis-evex.h (evex_table): Updated.
194 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
195 CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
196 (cpu_flags): Add CpuAVX512_VNNI.
197 * i386-opc.h (enum): Add CpuAVX512_VNNI.
198 (i386_cpu_flags): Add cpuavx512_vnni.
199 * i386-opc.tbl Add Intel AVX512_VNNI instructions.
200 * i386-init.h: Regenerate.
201 * i386-tbl.h: Likewise.
203 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
205 * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
206 (enum): Remove VEX_LEN_0F3A44_P_2.
207 (vex_len_table): Ditto.
208 (enum): Remove VEX_W_0F3A44_P_2.
209 (vew_w_table): Ditto.
210 (prefix_table): Adjust instructions (see prefixes above).
211 * i386-dis-evex.h (evex_table):
212 Add new instructions (see prefixes above).
213 * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
214 (bitfield_cpu_flags): Ditto.
215 * i386-opc.h (enum): Ditto.
216 (i386_cpu_flags): Ditto.
217 (CpuUnused): Comment out to avoid zero-width field problem.
218 * i386-opc.tbl (vpclmulqdq): New instruction.
219 * i386-init.h: Regenerate.
222 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
224 * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
225 PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
226 (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
227 VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
228 (vex_len_table): Ditto.
229 (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
230 VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
231 (vew_w_table): Ditto.
232 (prefix_table): Adjust instructions (see prefixes above).
233 * i386-dis-evex.h (evex_table):
234 Add new instructions (see prefixes above).
235 * i386-gen.c (cpu_flag_init): Add VAES.
236 (bitfield_cpu_flags): Ditto.
237 * i386-opc.h (enum): Ditto.
238 (i386_cpu_flags): Ditto.
239 * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
240 * i386-init.h: Regenerate.
243 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
245 * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
246 PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
247 PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
248 (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
249 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
250 (prefix_table): Updated (see prefixes above).
251 (three_byte_table): Likewise.
252 (vex_w_table): Likewise.
253 * i386-dis-evex.h: Likewise.
254 * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
255 (cpu_flags): Add CpuGFNI.
256 * i386-opc.h (enum): Add CpuGFNI.
257 (i386_cpu_flags): Add cpugfni.
258 * i386-opc.tbl: Add Intel GFNI instructions.
259 * i386-init.h: Regenerate.
260 * i386-tbl.h: Likewise.
262 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
264 * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
265 Define EXbScalar and EXwScalar for OP_EX.
266 (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
267 PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
268 PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
269 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
270 (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
271 EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
272 EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
273 EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
274 (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
275 (OP_E_memory): Likewise.
276 * i386-dis-evex.h: Updated.
277 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
278 CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
279 (cpu_flags): Add CpuAVX512_VBMI2.
280 * i386-opc.h (enum): Add CpuAVX512_VBMI2.
281 (i386_cpu_flags): Add cpuavx512_vbmi2.
282 * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
283 * i386-init.h: Regenerate.
284 * i386-tbl.h: Likewise.
286 2017-10-18 Eric Botcazou <ebotcazou@adacore.com>
288 * visium-dis.c (disassem_class1) <case 0>: Print the operands.
290 2017-10-12 James Bowman <james.bowman@ftdichip.com>
292 * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
293 * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
294 K15. Add jmpix pattern.
296 2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
298 * s390-opc.txt (prno, tpei, irbm): New instructions added.
300 2017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
302 * s390-opc.c (INSTR_SI_RD): New macro.
303 (INSTR_S_RD): Adjust example instruction.
304 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
307 2017-10-01 Alexander Fedotov <alfedotov@gmail.com>
309 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
310 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
311 VLE multimple load/store instructions. Old e_ldm* variants are
313 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
315 2017-09-27 Nick Clifton <nickc@redhat.com>
318 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
319 names for the fmv.x.s and fmv.s.x instructions respectively.
321 2017-09-26 do <do@nerilex.org>
324 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
325 be used on CPUs that have emacs support.
327 2017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
329 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
331 2017-09-09 Kamil Rytarowski <n54@gmx.com>
333 * nds32-asm.c: Rename __BIT() to N32_BIT().
334 * nds32-asm.h: Likewise.
335 * nds32-dis.c: Likewise.
337 2017-09-09 H.J. Lu <hongjiu.lu@intel.com>
339 * i386-dis.c (last_active_prefix): Removed.
340 (ckprefix): Don't set last_active_prefix.
341 (NOTRACK_Fixup): Don't check last_active_prefix.
343 2017-08-31 Nick Clifton <nickc@redhat.com>
345 * po/fr.po: Updated French translation.
347 2017-08-31 James Bowman <james.bowman@ftdichip.com>
349 * ft32-dis.c (print_insn_ft32): Correct display of non-address
352 2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
353 Edmar Wienskoski <edmar.wienskoski@nxp.com>
355 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
356 PPC_OPCODE_EFS2 flag to "e200z4" entry.
357 New entries efs2 and spe2.
358 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
359 (SPE2_OPCD_SEGS): New macro.
360 (spe2_opcd_indices): New.
361 (disassemble_init_powerpc): Handle SPE2 opcodes.
362 (lookup_spe2): New function.
363 (print_insn_powerpc): call lookup_spe2.
364 * ppc-opc.c (insert_evuimm1_ex0): New function.
365 (extract_evuimm1_ex0): Likewise.
366 (insert_evuimm_lt8): Likewise.
367 (extract_evuimm_lt8): Likewise.
368 (insert_off_spe2): Likewise.
369 (extract_off_spe2): Likewise.
370 (insert_Ddd): Likewise.
371 (extract_Ddd): Likewise.
373 (EVUIMM_LT8): Likewise.
374 (EVUIMM_LT16): Adjust.
376 (EVUIMM_1): Likewise.
377 (EVUIMM_1_EX0): Likewise.
380 (VX_OFF_SPE2): Likewise.
383 (VX_MASK_DDD): New mask.
385 (VX_RA_CONST): New macro.
386 (VX_RA_CONST_MASK): Likewise.
387 (VX_RB_CONST): Likewise.
388 (VX_RB_CONST_MASK): Likewise.
389 (VX_OFF_SPE2_MASK): Likewise.
390 (VX_SPE_CRFD): Likewise.
391 (VX_SPE_CRFD_MASK VX): Likewise.
392 (VX_SPE2_CLR): Likewise.
393 (VX_SPE2_CLR_MASK): Likewise.
394 (VX_SPE2_SPLATB): Likewise.
395 (VX_SPE2_SPLATB_MASK): Likewise.
396 (VX_SPE2_OCTET): Likewise.
397 (VX_SPE2_OCTET_MASK): Likewise.
398 (VX_SPE2_DDHH): Likewise.
399 (VX_SPE2_DDHH_MASK): Likewise.
400 (VX_SPE2_HH): Likewise.
401 (VX_SPE2_HH_MASK): Likewise.
402 (VX_SPE2_EVMAR): Likewise.
403 (VX_SPE2_EVMAR_MASK): Likewise.
406 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
407 (powerpc_macros): Map old SPE instructions have new names
408 with the same opcodes. Add SPE2 instructions which just are
410 (spe2_opcodes): Add SPE2 opcodes.
412 2017-08-23 Alan Modra <amodra@gmail.com>
414 * ppc-opc.c: Formatting and comment fixes. Move insert and
415 extract functions earlier, deleting forward declarations.
416 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
419 2017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
421 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
423 2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
424 Edmar Wienskoski <edmar.wienskoski@nxp.com>
426 * ppc-opc.c (insert_evuimm2_ex0): New function.
427 (extract_evuimm2_ex0): Likewise.
428 (insert_evuimm4_ex0): Likewise.
429 (extract_evuimm4_ex0): Likewise.
430 (insert_evuimm8_ex0): Likewise.
431 (extract_evuimm8_ex0): Likewise.
432 (insert_evuimm_lt16): Likewise.
433 (extract_evuimm_lt16): Likewise.
434 (insert_rD_rS_even): Likewise.
435 (extract_rD_rS_even): Likewise.
436 (insert_off_lsp): Likewise.
437 (extract_off_lsp): Likewise.
438 (RD_EVEN): New operand.
441 (EVUIMM_LT16): New operand.
443 (EVUIMM_2_EX0): New operand.
445 (EVUIMM_4_EX0): New operand.
447 (EVUIMM_8_EX0): New operand.
449 (VX_OFF): New operand.
451 (VX_LSP_MASK): Likewise.
452 (VX_LSP_OFF_MASK): Likewise.
453 (PPC_OPCODE_LSP): Likewise.
454 (vle_opcodes): Add LSP opcodes.
455 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
457 2017-08-09 Jiong Wang <jiong.wang@arm.com>
459 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
460 register operands in CRC instructions.
461 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
464 2017-08-07 H.J. Lu <hongjiu.lu@intel.com>
466 * disassemble.c (disassembler): Mark big and mach with
469 2017-08-07 Maciej W. Rozycki <macro@imgtec.com>
471 * disassemble.c (disassembler): Remove arch/mach/endian
474 2017-07-25 Nick Clifton <nickc@redhat.com>
477 * arc-opc.c (insert_rhv2): Use lower case first letter in error
479 (insert_r0): Likewise.
480 (insert_r1): Likewise.
481 (insert_r2): Likewise.
482 (insert_r3): Likewise.
483 (insert_sp): Likewise.
484 (insert_gp): Likewise.
485 (insert_pcl): Likewise.
486 (insert_blink): Likewise.
487 (insert_ilink1): Likewise.
488 (insert_ilink2): Likewise.
489 (insert_ras): Likewise.
490 (insert_rbs): Likewise.
491 (insert_rcs): Likewise.
492 (insert_simm3s): Likewise.
493 (insert_rrange): Likewise.
494 (insert_r13el): Likewise.
495 (insert_fpel): Likewise.
496 (insert_blinkel): Likewise.
497 (insert_pclel): Likewise.
498 (insert_nps_bitop_size_2b): Likewise.
499 (insert_nps_imm_offset): Likewise.
500 (insert_nps_imm_entry): Likewise.
501 (insert_nps_size_16bit): Likewise.
502 (insert_nps_##NAME##_pos): Likewise.
503 (insert_nps_##NAME): Likewise.
504 (insert_nps_bitop_ins_ext): Likewise.
505 (insert_nps_##NAME): Likewise.
506 (insert_nps_min_hofs): Likewise.
507 (insert_nps_##NAME): Likewise.
508 (insert_nps_rbdouble_64): Likewise.
509 (insert_nps_misc_imm_offset): Likewise.
510 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
513 2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
514 Jiong Wang <jiong.wang@arm.com>
516 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
518 * aarch64-dis-2.c: Regenerated.
520 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
522 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
525 2017-07-20 Nick Clifton <nickc@redhat.com>
527 * po/de.po: Updated German translation.
529 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
531 * arc-regs.h (sec_stat): New aux register.
532 (aux_kernel_sp): Likewise.
533 (aux_sec_u_sp): Likewise.
534 (aux_sec_k_sp): Likewise.
535 (sec_vecbase_build): Likewise.
536 (nsc_table_top): Likewise.
537 (nsc_table_base): Likewise.
538 (ersec_stat): Likewise.
539 (aux_sec_except): Likewise.
541 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
543 * arc-opc.c (extract_uimm12_20): New function.
544 (UIMM12_20): New operand.
546 * arc-tbl.h (sjli): Add new instruction.
548 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
549 John Eric Martin <John.Martin@emmicro-us.com>
551 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
552 (UIMM3_23): Adjust accordingly.
553 * arc-regs.h: Add/correct jli_base register.
554 * arc-tbl.h (jli_s): Likewise.
556 2017-07-18 Nick Clifton <nickc@redhat.com>
559 * aarch64-opc.c: Fix spelling typos.
560 * i386-dis.c: Likewise.
562 2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
564 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
565 max_addr_offset and octets variables to size_t.
567 2017-07-12 Alan Modra <amodra@gmail.com>
569 * po/da.po: Update from translationproject.org/latest/opcodes/.
570 * po/de.po: Likewise.
571 * po/es.po: Likewise.
572 * po/fi.po: Likewise.
573 * po/fr.po: Likewise.
574 * po/id.po: Likewise.
575 * po/it.po: Likewise.
576 * po/nl.po: Likewise.
577 * po/pt_BR.po: Likewise.
578 * po/ro.po: Likewise.
579 * po/sv.po: Likewise.
580 * po/tr.po: Likewise.
581 * po/uk.po: Likewise.
582 * po/vi.po: Likewise.
583 * po/zh_CN.po: Likewise.
585 2017-07-11 Yao Qi <yao.qi@linaro.org>
586 Alan Modra <amodra@gmail.com>
588 * cgen.sh: Mark generated files read-only.
589 * epiphany-asm.c: Regenerate.
590 * epiphany-desc.c: Regenerate.
591 * epiphany-desc.h: Regenerate.
592 * epiphany-dis.c: Regenerate.
593 * epiphany-ibld.c: Regenerate.
594 * epiphany-opc.c: Regenerate.
595 * epiphany-opc.h: Regenerate.
596 * fr30-asm.c: Regenerate.
597 * fr30-desc.c: Regenerate.
598 * fr30-desc.h: Regenerate.
599 * fr30-dis.c: Regenerate.
600 * fr30-ibld.c: Regenerate.
601 * fr30-opc.c: Regenerate.
602 * fr30-opc.h: Regenerate.
603 * frv-asm.c: Regenerate.
604 * frv-desc.c: Regenerate.
605 * frv-desc.h: Regenerate.
606 * frv-dis.c: Regenerate.
607 * frv-ibld.c: Regenerate.
608 * frv-opc.c: Regenerate.
609 * frv-opc.h: Regenerate.
610 * ip2k-asm.c: Regenerate.
611 * ip2k-desc.c: Regenerate.
612 * ip2k-desc.h: Regenerate.
613 * ip2k-dis.c: Regenerate.
614 * ip2k-ibld.c: Regenerate.
615 * ip2k-opc.c: Regenerate.
616 * ip2k-opc.h: Regenerate.
617 * iq2000-asm.c: Regenerate.
618 * iq2000-desc.c: Regenerate.
619 * iq2000-desc.h: Regenerate.
620 * iq2000-dis.c: Regenerate.
621 * iq2000-ibld.c: Regenerate.
622 * iq2000-opc.c: Regenerate.
623 * iq2000-opc.h: Regenerate.
624 * lm32-asm.c: Regenerate.
625 * lm32-desc.c: Regenerate.
626 * lm32-desc.h: Regenerate.
627 * lm32-dis.c: Regenerate.
628 * lm32-ibld.c: Regenerate.
629 * lm32-opc.c: Regenerate.
630 * lm32-opc.h: Regenerate.
631 * lm32-opinst.c: Regenerate.
632 * m32c-asm.c: Regenerate.
633 * m32c-desc.c: Regenerate.
634 * m32c-desc.h: Regenerate.
635 * m32c-dis.c: Regenerate.
636 * m32c-ibld.c: Regenerate.
637 * m32c-opc.c: Regenerate.
638 * m32c-opc.h: Regenerate.
639 * m32r-asm.c: Regenerate.
640 * m32r-desc.c: Regenerate.
641 * m32r-desc.h: Regenerate.
642 * m32r-dis.c: Regenerate.
643 * m32r-ibld.c: Regenerate.
644 * m32r-opc.c: Regenerate.
645 * m32r-opc.h: Regenerate.
646 * m32r-opinst.c: Regenerate.
647 * mep-asm.c: Regenerate.
648 * mep-desc.c: Regenerate.
649 * mep-desc.h: Regenerate.
650 * mep-dis.c: Regenerate.
651 * mep-ibld.c: Regenerate.
652 * mep-opc.c: Regenerate.
653 * mep-opc.h: Regenerate.
654 * mt-asm.c: Regenerate.
655 * mt-desc.c: Regenerate.
656 * mt-desc.h: Regenerate.
657 * mt-dis.c: Regenerate.
658 * mt-ibld.c: Regenerate.
659 * mt-opc.c: Regenerate.
660 * mt-opc.h: Regenerate.
661 * or1k-asm.c: Regenerate.
662 * or1k-desc.c: Regenerate.
663 * or1k-desc.h: Regenerate.
664 * or1k-dis.c: Regenerate.
665 * or1k-ibld.c: Regenerate.
666 * or1k-opc.c: Regenerate.
667 * or1k-opc.h: Regenerate.
668 * or1k-opinst.c: Regenerate.
669 * xc16x-asm.c: Regenerate.
670 * xc16x-desc.c: Regenerate.
671 * xc16x-desc.h: Regenerate.
672 * xc16x-dis.c: Regenerate.
673 * xc16x-ibld.c: Regenerate.
674 * xc16x-opc.c: Regenerate.
675 * xc16x-opc.h: Regenerate.
676 * xstormy16-asm.c: Regenerate.
677 * xstormy16-desc.c: Regenerate.
678 * xstormy16-desc.h: Regenerate.
679 * xstormy16-dis.c: Regenerate.
680 * xstormy16-ibld.c: Regenerate.
681 * xstormy16-opc.c: Regenerate.
682 * xstormy16-opc.h: Regenerate.
684 2017-07-07 Alan Modra <amodra@gmail.com>
686 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
687 * m32c-dis.c: Regenerate.
688 * mep-dis.c: Regenerate.
690 2017-07-05 Borislav Petkov <bp@suse.de>
692 * i386-dis.c: Enable ModRM.reg /6 aliases.
694 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
696 * opcodes/arm-dis.c: Support MVFR2 in disassembly
699 2017-07-04 Tristan Gingold <gingold@adacore.com>
701 * configure: Regenerate.
703 2017-07-03 Tristan Gingold <gingold@adacore.com>
705 * po/opcodes.pot: Regenerate.
707 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
709 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
710 entries to the MSA ASE instruction block.
712 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
713 Maciej W. Rozycki <macro@imgtec.com>
715 * micromips-opc.c (XPA, XPAVZ): New macros.
716 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
719 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
720 Maciej W. Rozycki <macro@imgtec.com>
722 * micromips-opc.c (I36): New macro.
723 (micromips_opcodes): Add "eretnc".
725 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
726 Andrew Bennett <andrew.bennett@imgtec.com>
728 * mips-dis.c (mips_calculate_combination_ases): Handle the
730 (parse_mips_ase_option): New function.
731 (parse_mips_dis_option): Factor out ASE option handling to the
732 new function. Call `mips_calculate_combination_ases'.
733 * mips-opc.c (XPAVZ): New macro.
734 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
735 "mfhgc0", "mthc0" and "mthgc0".
737 2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
739 * mips-dis.c (mips_calculate_combination_ases): New function.
740 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
741 calculation to the new function.
742 (set_default_mips_dis_options): Call the new function.
744 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
746 * arc-dis.c (parse_disassembler_options): Use
747 FOR_EACH_DISASSEMBLER_OPTION.
749 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
751 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
752 disassembler option strings.
753 (parse_cpu_option): Likewise.
755 2017-06-28 Tamar Christina <tamar.christina@arm.com>
757 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
758 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
759 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
760 (aarch64_feature_dotprod, DOT_INSN): New.
762 * aarch64-dis-2.c: Regenerated.
764 2017-06-28 Jiong Wang <jiong.wang@arm.com>
766 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
768 2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
769 Matthew Fortune <matthew.fortune@imgtec.com>
770 Andrew Bennett <andrew.bennett@imgtec.com>
772 * mips-formats.h (INT_BIAS): New macro.
773 (INT_ADJ): Redefine in INT_BIAS terms.
774 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
775 (mips_print_save_restore): New function.
776 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
777 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
779 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
780 (print_mips16_insn_arg): Call `mips_print_save_restore' for
781 OP_SAVE_RESTORE_LIST handling, factored out from here.
782 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
783 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
784 (mips_builtin_opcodes): Add "restore" and "save" entries.
785 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
787 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
789 2017-06-23 Andrew Waterman <andrew@sifive.com>
791 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
792 alias; do not mark SLTI instruction as an alias.
794 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
796 * i386-dis.c (RM_0FAE_REG_5): Removed.
797 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
798 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
799 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
800 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
801 PREFIX_MOD_3_0F01_REG_5_RM_0.
802 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
803 PREFIX_MOD_3_0FAE_REG_5.
804 (mod_table): Update MOD_0FAE_REG_5.
805 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
806 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
807 * i386-tbl.h: Regenerated.
809 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
811 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
812 * i386-opc.tbl: Likewise.
813 * i386-tbl.h: Regenerated.
815 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
817 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
819 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
822 2017-06-19 Nick Clifton <nickc@redhat.com>
825 * score-dis.c (score_opcodes): Add sentinel.
827 2017-06-16 Alan Modra <amodra@gmail.com>
829 * rx-decode.c: Regenerate.
831 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
834 * i386-dis.c (OP_E_register): Check valid bnd register.
837 2017-06-15 Nick Clifton <nickc@redhat.com>
840 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
843 2017-06-15 Nick Clifton <nickc@redhat.com>
846 * rl78-decode.opc (OP_BUF_LEN): Define.
847 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
848 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
850 * rl78-decode.c: Regenerate.
852 2017-06-15 Nick Clifton <nickc@redhat.com>
855 * bfin-dis.c (gregs): Clip index to prevent overflow.
860 2017-06-14 Nick Clifton <nickc@redhat.com>
863 * score7-dis.c (score_opcodes): Add sentinel.
865 2017-06-14 Yao Qi <yao.qi@linaro.org>
867 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
868 * arm-dis.c: Likewise.
869 * ia64-dis.c: Likewise.
870 * mips-dis.c: Likewise.
871 * spu-dis.c: Likewise.
872 * disassemble.h (print_insn_aarch64): New declaration, moved from
874 (print_insn_big_arm, print_insn_big_mips): Likewise.
875 (print_insn_i386, print_insn_ia64): Likewise.
876 (print_insn_little_arm, print_insn_little_mips): Likewise.
878 2017-06-14 Nick Clifton <nickc@redhat.com>
881 * rx-decode.opc: Include libiberty.h
882 (GET_SCALE): New macro - validates access to SCALE array.
883 (GET_PSCALE): New macro - validates access to PSCALE array.
884 (DIs, SIs, S2Is, rx_disp): Use new macros.
885 * rx-decode.c: Regenerate.
887 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
889 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
891 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
893 * arc-dis.c (enforced_isa_mask): Declare.
894 (cpu_types): Likewise.
895 (parse_cpu_option): New function.
896 (parse_disassembler_options): Use it.
897 (print_insn_arc): Use enforced_isa_mask.
898 (print_arc_disassembler_options): Document new options.
900 2017-05-24 Yao Qi <yao.qi@linaro.org>
902 * alpha-dis.c: Include disassemble.h, don't include
904 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
905 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
906 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
907 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
908 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
909 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
910 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
911 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
912 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
913 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
914 * moxie-dis.c, msp430-dis.c, mt-dis.c:
915 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
916 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
917 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
918 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
919 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
920 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
921 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
922 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
923 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
924 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
925 * z80-dis.c, z8k-dis.c: Likewise.
926 * disassemble.h: New file.
928 2017-05-24 Yao Qi <yao.qi@linaro.org>
930 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
931 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
933 2017-05-24 Yao Qi <yao.qi@linaro.org>
935 * disassemble.c (disassembler): Add arguments a, big and mach.
938 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
940 * i386-dis.c (NOTRACK_Fixup): New.
942 (NOTRACK_PREFIX): Likewise.
943 (last_active_prefix): Likewise.
944 (reg_table): Use NOTRACK on indirect call and jmp.
945 (ckprefix): Set last_active_prefix.
946 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
947 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
948 * i386-opc.h (NoTrackPrefixOk): New.
949 (i386_opcode_modifier): Add notrackprefixok.
950 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
952 * i386-tbl.h: Regenerated.
954 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
956 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
958 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
960 (print_insn_sparc): Handle new operand types.
961 * sparc-opc.c (MASK_M8): Define.
963 (v6notlet): Likewise.
974 (v9andleon): Likewise.
977 (HWS2_VM8): Likewise.
978 (sparc_opcode_archs): Add entry for "m8".
979 (sparc_opcodes): Add OSA2017 and M8 instructions
980 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
982 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
983 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
984 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
985 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
986 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
987 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
988 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
989 ASI_CORE_SELECT_COMMIT_NHT.
991 2017-05-18 Alan Modra <amodra@gmail.com>
993 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
994 * aarch64-dis.c: Likewise.
995 * aarch64-gen.c: Likewise.
996 * aarch64-opc.c: Likewise.
998 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
999 Matthew Fortune <matthew.fortune@imgtec.com>
1001 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1002 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1003 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1004 (print_insn_arg) <OP_REG28>: Add handler.
1005 (validate_insn_args) <OP_REG28>: Handle.
1006 (print_mips16_insn_arg): Handle MIPS16 instructions that require
1007 32-bit encoding and 9-bit immediates.
1008 (print_insn_mips16): Handle MIPS16 instructions that require
1009 32-bit encoding and MFC0/MTC0 operand decoding.
1010 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1011 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1012 (RD_C0, WR_C0, E2, E2MT): New macros.
1013 (mips16_opcodes): Add entries for MIPS16e2 instructions:
1014 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1015 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1016 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1017 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1018 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1019 instructions, "swl", "swr", "sync" and its "sync_acquire",
1020 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1021 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
1022 regular/extended entries for original MIPS16 ISA revision
1023 instructions whose extended forms are subdecoded in the MIPS16e2
1024 ISA revision: "li", "sll" and "srl".
1026 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1028 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1029 reference in CP0 move operand decoding.
1031 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
1033 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1034 type to hexadecimal.
1035 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1037 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
1039 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1040 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1041 "sync_rmb" and "sync_wmb" as aliases.
1042 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1043 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1045 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
1047 * arc-dis.c (parse_option): Update quarkse_em option..
1048 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1050 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1052 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
1054 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1056 2017-05-01 Michael Clark <michaeljclark@mac.com>
1058 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1061 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
1063 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1064 and branches and not synthetic data instructions.
1066 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
1068 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1070 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1072 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1073 * arc-opc.c (insert_r13el): New function.
1075 * arc-tbl.h: Add new enter/leave variants.
1077 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1079 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1081 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1083 * mips-dis.c (print_mips_disassembler_options): Add
1086 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1088 * mips16-opc.c (AL): New macro.
1089 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1090 of "ld" and "lw" as aliases.
1092 2017-04-24 Tamar Christina <tamar.christina@arm.com>
1094 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1097 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
1098 Alan Modra <amodra@gmail.com>
1100 * ppc-opc.c (ELEV): Define.
1101 (vle_opcodes): Add se_rfgi and e_sc.
1102 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1105 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
1107 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1109 2017-04-21 Nick Clifton <nickc@redhat.com>
1112 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1115 2017-04-13 Alan Modra <amodra@gmail.com>
1117 * epiphany-desc.c: Regenerate.
1118 * fr30-desc.c: Regenerate.
1119 * frv-desc.c: Regenerate.
1120 * ip2k-desc.c: Regenerate.
1121 * iq2000-desc.c: Regenerate.
1122 * lm32-desc.c: Regenerate.
1123 * m32c-desc.c: Regenerate.
1124 * m32r-desc.c: Regenerate.
1125 * mep-desc.c: Regenerate.
1126 * mt-desc.c: Regenerate.
1127 * or1k-desc.c: Regenerate.
1128 * xc16x-desc.c: Regenerate.
1129 * xstormy16-desc.c: Regenerate.
1131 2017-04-11 Alan Modra <amodra@gmail.com>
1133 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1134 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
1135 PPC_OPCODE_TMR for e6500.
1136 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1137 (PPCVEC3): Define as PPC_OPCODE_POWER9.
1138 (PPCVSX2): Define as PPC_OPCODE_POWER8.
1139 (PPCVSX3): Define as PPC_OPCODE_POWER9.
1140 (PPCHTM): Define as PPC_OPCODE_POWER8.
1141 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1143 2017-04-10 Alan Modra <amodra@gmail.com>
1145 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1146 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1147 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1148 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1150 2017-04-09 Pip Cet <pipcet@gmail.com>
1152 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1153 appropriate floating-point precision directly.
1155 2017-04-07 Alan Modra <amodra@gmail.com>
1157 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1158 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1159 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1160 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1161 vector instructions with E6500 not PPCVEC2.
1163 2017-04-06 Pip Cet <pipcet@gmail.com>
1165 * Makefile.am: Add wasm32-dis.c.
1166 * configure.ac: Add wasm32-dis.c to wasm32 target.
1167 * disassemble.c: Add wasm32 disassembler code.
1168 * wasm32-dis.c: New file.
1169 * Makefile.in: Regenerate.
1170 * configure: Regenerate.
1171 * po/POTFILES.in: Regenerate.
1172 * po/opcodes.pot: Regenerate.
1174 2017-04-05 Pedro Alves <palves@redhat.com>
1176 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1177 * arm-dis.c (parse_arm_disassembler_options): Constify.
1178 * ppc-dis.c (powerpc_init_dialect): Constify local.
1179 * vax-dis.c (parse_disassembler_options): Constify.
1181 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
1183 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1186 2017-03-30 Pip Cet <pipcet@gmail.com>
1188 * configure.ac: Add (empty) bfd_wasm32_arch target.
1189 * configure: Regenerate
1190 * po/opcodes.pot: Regenerate.
1192 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
1194 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1196 * opcodes/sparc-opc.c (asi_table): New ASIs.
1198 2017-03-29 Alan Modra <amodra@gmail.com>
1200 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
1202 (lookup_powerpc): Don't special case -1 dialect. Handle
1204 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1205 lookup_powerpc call, pass it on second.
1207 2017-03-27 Alan Modra <amodra@gmail.com>
1210 * ppc-dis.c (struct ppc_mopt): Comment.
1211 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1213 2017-03-27 Rinat Zelig <rinat@mellanox.com>
1215 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1216 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1217 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1218 (insert_nps_misc_imm_offset): New function.
1219 (extract_nps_misc imm_offset): New function.
1220 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1221 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1223 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1225 * s390-mkopc.c (main): Remove vx2 check.
1226 * s390-opc.txt: Remove vx2 instruction flags.
1228 2017-03-21 Rinat Zelig <rinat@mellanox.com>
1230 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1231 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1232 (insert_nps_imm_offset): New function.
1233 (extract_nps_imm_offset): New function.
1234 (insert_nps_imm_entry): New function.
1235 (extract_nps_imm_entry): New function.
1237 2017-03-17 Alan Modra <amodra@gmail.com>
1240 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1241 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
1242 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
1244 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1246 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1250 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1252 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1254 2017-03-13 Andrew Waterman <andrew@sifive.com>
1256 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1261 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1263 * i386-gen.c (opcode_modifiers): Replace S with Load.
1264 * i386-opc.h (S): Removed.
1266 (i386_opcode_modifier): Replace s with load.
1267 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1268 and {evex}. Replace S with Load.
1269 * i386-tbl.h: Regenerated.
1271 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1273 * i386-opc.tbl: Use CpuCET on rdsspq.
1274 * i386-tbl.h: Regenerated.
1276 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1278 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1279 <vsx>: Do not use PPC_OPCODE_VSX3;
1281 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1283 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1285 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
1287 * i386-dis.c (REG_0F1E_MOD_3): New enum.
1288 (MOD_0F1E_PREFIX_1): Likewise.
1289 (MOD_0F38F5_PREFIX_2): Likewise.
1290 (MOD_0F38F6_PREFIX_0): Likewise.
1291 (RM_0F1E_MOD_3_REG_7): Likewise.
1292 (PREFIX_MOD_0_0F01_REG_5): Likewise.
1293 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1294 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1295 (PREFIX_0F1E): Likewise.
1296 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1297 (PREFIX_0F38F5): Likewise.
1298 (dis386_twobyte): Use PREFIX_0F1E.
1299 (reg_table): Add REG_0F1E_MOD_3.
1300 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1301 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1302 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1303 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1304 (three_byte_table): Use PREFIX_0F38F5.
1305 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1306 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1307 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1308 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1309 PREFIX_MOD_3_0F01_REG_5_RM_2.
1310 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1311 (cpu_flags): Add CpuCET.
1312 * i386-opc.h (CpuCET): New enum.
1313 (CpuUnused): Commented out.
1314 (i386_cpu_flags): Add cpucet.
1315 * i386-opc.tbl: Add Intel CET instructions.
1316 * i386-init.h: Regenerated.
1317 * i386-tbl.h: Likewise.
1319 2017-03-06 Alan Modra <amodra@gmail.com>
1322 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1323 (extract_raq, extract_ras, extract_rbx): New functions.
1324 (powerpc_operands): Use opposite corresponding insert function.
1326 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1327 register restriction.
1329 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1331 * disassemble.c Include "safe-ctype.h".
1332 (disassemble_init_for_target): Handle s390 init.
1333 (remove_whitespace_and_extra_commas): New function.
1334 (disassembler_options_cmp): Likewise.
1335 * arm-dis.c: Include "libiberty.h".
1337 (regnames): Use long disassembler style names.
1338 Add force-thumb and no-force-thumb options.
1339 (NUM_ARM_REGNAMES): Rename from this...
1340 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1341 (get_arm_regname_num_options): Delete.
1342 (set_arm_regname_option): Likewise.
1343 (get_arm_regnames): Likewise.
1344 (parse_disassembler_options): Likewise.
1345 (parse_arm_disassembler_option): Rename from this...
1346 (parse_arm_disassembler_options): ...to this. Make static.
1347 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1348 (print_insn): Use parse_arm_disassembler_options.
1349 (disassembler_options_arm): New function.
1350 (print_arm_disassembler_options): Handle updated regnames.
1351 * ppc-dis.c: Include "libiberty.h".
1352 (ppc_opts): Add "32" and "64" entries.
1353 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1354 (powerpc_init_dialect): Add break to switch statement.
1355 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1356 (disassembler_options_powerpc): New function.
1357 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1358 Remove printing of "32" and "64".
1359 * s390-dis.c: Include "libiberty.h".
1360 (init_flag): Remove unneeded variable.
1361 (struct s390_options_t): New structure type.
1362 (options): New structure.
1363 (init_disasm): Rename from this...
1364 (disassemble_init_s390): ...to this. Add initializations for
1365 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1366 (print_insn_s390): Delete call to init_disasm.
1367 (disassembler_options_s390): New function.
1368 (print_s390_disassembler_options): Print using information from
1370 * po/opcodes.pot: Regenerate.
1372 2017-02-28 Jan Beulich <jbeulich@suse.com>
1374 * i386-dis.c (PCMPESTR_Fixup): New.
1375 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1376 (prefix_table): Use PCMPESTR_Fixup.
1377 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1379 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1380 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1381 Split 64-bit and non-64-bit variants.
1382 * opcodes/i386-tbl.h: Re-generate.
1384 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1386 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1387 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1388 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1389 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1390 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1391 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1392 (OP_SVE_V_HSD): New macros.
1393 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1394 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1395 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1396 (aarch64_opcode_table): Add new SVE instructions.
1397 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1398 for rotation operands. Add new SVE operands.
1399 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1400 (ins_sve_quad_index): Likewise.
1401 (ins_imm_rotate): Split into...
1402 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1403 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1404 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1406 (aarch64_ins_sve_addr_ri_s4): New function.
1407 (aarch64_ins_sve_quad_index): Likewise.
1408 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1409 * aarch64-asm-2.c: Regenerate.
1410 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1411 (ext_sve_quad_index): Likewise.
1412 (ext_imm_rotate): Split into...
1413 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1414 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1415 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1417 (aarch64_ext_sve_addr_ri_s4): New function.
1418 (aarch64_ext_sve_quad_index): Likewise.
1419 (aarch64_ext_sve_index): Allow quad indices.
1420 (do_misc_decoding): Likewise.
1421 * aarch64-dis-2.c: Regenerate.
1422 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1423 aarch64_field_kinds.
1424 (OPD_F_OD_MASK): Widen by one bit.
1425 (OPD_F_NO_ZR): Bump accordingly.
1426 (get_operand_field_width): New function.
1427 * aarch64-opc.c (fields): Add new SVE fields.
1428 (operand_general_constraint_met_p): Handle new SVE operands.
1429 (aarch64_print_operand): Likewise.
1430 * aarch64-opc-2.c: Regenerate.
1432 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1434 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1435 (aarch64_feature_compnum): ...this.
1436 (SIMD_V8_3): Replace with...
1438 (CNUM_INSN): New macro.
1439 (aarch64_opcode_table): Use it for the complex number instructions.
1441 2017-02-24 Jan Beulich <jbeulich@suse.com>
1443 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1445 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1447 Add support for associating SPARC ASIs with an architecture level.
1448 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1449 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1450 decoding of SPARC ASIs.
1452 2017-02-23 Jan Beulich <jbeulich@suse.com>
1454 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1455 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1457 2017-02-21 Jan Beulich <jbeulich@suse.com>
1459 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1460 1 (instead of to itself). Correct typo.
1462 2017-02-14 Andrew Waterman <andrew@sifive.com>
1464 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1467 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1469 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1470 (aarch64_sys_reg_supported_p): Handle them.
1472 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1474 * arc-opc.c (UIMM6_20R): Define.
1475 (SIMM12_20): Use above.
1476 (SIMM12_20R): Define.
1477 (SIMM3_5_S): Use above.
1478 (UIMM7_A32_11R_S): Define.
1479 (UIMM7_9_S): Use above.
1480 (UIMM3_13R_S): Define.
1481 (SIMM11_A32_7_S): Use above.
1483 (UIMM10_A32_8_S): Use above.
1484 (UIMM8_8R_S): Define.
1486 (arc_relax_opcodes): Use all above defines.
1488 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
1490 * arc-regs.h: Distinguish some of the registers different on
1491 ARC700 and HS38 cpus.
1493 2017-02-14 Alan Modra <amodra@gmail.com>
1496 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1497 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1499 2017-02-11 Stafford Horne <shorne@gmail.com>
1500 Alan Modra <amodra@gmail.com>
1502 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1503 Use insn_bytes_value and insn_int_value directly instead. Don't
1504 free allocated memory until function exit.
1506 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
1508 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1510 2017-02-03 Nick Clifton <nickc@redhat.com>
1513 * aarch64-opc.c (print_register_list): Ensure that the register
1514 list index will fir into the tb buffer.
1515 (print_register_offset_address): Likewise.
1516 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1518 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1521 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1522 instructions when the previous fetch packet ends with a 32-bit
1525 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1527 * pru-opc.c: Remove vague reference to a future GDB port.
1529 2017-01-20 Nick Clifton <nickc@redhat.com>
1531 * po/ga.po: Updated Irish translation.
1533 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1535 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1537 2017-01-13 Yao Qi <yao.qi@linaro.org>
1539 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1540 if FETCH_DATA returns 0.
1541 (m68k_scan_mask): Likewise.
1542 (print_insn_m68k): Update code to handle -1 return value.
1544 2017-01-13 Yao Qi <yao.qi@linaro.org>
1546 * m68k-dis.c (enum print_insn_arg_error): New.
1547 (NEXTBYTE): Replace -3 with
1548 PRINT_INSN_ARG_MEMORY_ERROR.
1549 (NEXTULONG): Likewise.
1550 (NEXTSINGLE): Likewise.
1551 (NEXTDOUBLE): Likewise.
1552 (NEXTDOUBLE): Likewise.
1553 (NEXTPACKED): Likewise.
1554 (FETCH_ARG): Likewise.
1555 (FETCH_DATA): Update comments.
1556 (print_insn_arg): Update comments. Replace magic numbers with
1558 (match_insn_m68k): Likewise.
1560 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1562 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1563 * i386-dis-evex.h (evex_table): Updated.
1564 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1565 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1566 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1567 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1568 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1569 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1570 * i386-init.h: Regenerate.
1571 * i386-tbl.h: Ditto.
1573 2017-01-12 Yao Qi <yao.qi@linaro.org>
1575 * msp430-dis.c (msp430_singleoperand): Return -1 if
1576 msp430dis_opcode_signed returns false.
1577 (msp430_doubleoperand): Likewise.
1578 (msp430_branchinstr): Return -1 if
1579 msp430dis_opcode_unsigned returns false.
1580 (msp430x_calla_instr): Likewise.
1581 (print_insn_msp430): Likewise.
1583 2017-01-05 Nick Clifton <nickc@redhat.com>
1586 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1587 could not be matched.
1588 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1591 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1593 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1594 (aarch64_opcode_table): Use RCPC_INSN.
1596 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
1598 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1600 * riscv-opcodes/all-opcodes: Likewise.
1602 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1604 * riscv-dis.c (print_insn_args): Add fall through comment.
1606 2017-01-03 Nick Clifton <nickc@redhat.com>
1608 * po/sr.po: New Serbian translation.
1609 * configure.ac (ALL_LINGUAS): Add sr.
1610 * configure: Regenerate.
1612 2017-01-02 Alan Modra <amodra@gmail.com>
1614 * epiphany-desc.h: Regenerate.
1615 * epiphany-opc.h: Regenerate.
1616 * fr30-desc.h: Regenerate.
1617 * fr30-opc.h: Regenerate.
1618 * frv-desc.h: Regenerate.
1619 * frv-opc.h: Regenerate.
1620 * ip2k-desc.h: Regenerate.
1621 * ip2k-opc.h: Regenerate.
1622 * iq2000-desc.h: Regenerate.
1623 * iq2000-opc.h: Regenerate.
1624 * lm32-desc.h: Regenerate.
1625 * lm32-opc.h: Regenerate.
1626 * m32c-desc.h: Regenerate.
1627 * m32c-opc.h: Regenerate.
1628 * m32r-desc.h: Regenerate.
1629 * m32r-opc.h: Regenerate.
1630 * mep-desc.h: Regenerate.
1631 * mep-opc.h: Regenerate.
1632 * mt-desc.h: Regenerate.
1633 * mt-opc.h: Regenerate.
1634 * or1k-desc.h: Regenerate.
1635 * or1k-opc.h: Regenerate.
1636 * xc16x-desc.h: Regenerate.
1637 * xc16x-opc.h: Regenerate.
1638 * xstormy16-desc.h: Regenerate.
1639 * xstormy16-opc.h: Regenerate.
1641 2017-01-02 Alan Modra <amodra@gmail.com>
1643 Update year range in copyright notice of all files.
1645 For older changes see ChangeLog-2016
1647 Copyright (C) 2017 Free Software Foundation, Inc.
1649 Copying and distribution of this file, with or without modification,
1650 are permitted in any medium without royalty provided the copyright
1651 notice and this notice are preserved.
1657 version-control: never