1 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
3 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
5 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
6 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
7 syncw, syncws, vm3mulu, vm0 and vmulu.
9 2008-05-30 H.J. Lu <hongjiu.lu@intel.com>
11 * i386-opc.tbl: Add vmovd with 64bit operand.
12 * i386-tbl.h: Regenerated.
14 2008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
16 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
18 2008-05-22 H.J. Lu <hongjiu.lu@intel.com>
20 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
21 * i386-tbl.h: Regenerated.
23 2008-05-22 H.J. Lu <hongjiu.lu@intel.com>
26 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
27 into 32bit and 64bit. Remove Reg64|Qword and add
28 IgnoreSize|No_qSuf on 32bit version.
29 * i386-tbl.h: Regenerated.
31 2008-05-21 H.J. Lu <hongjiu.lu@intel.com>
33 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
34 * i386-tbl.h: Regenerated.
36 2008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
38 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
40 2008-05-14 Alan Modra <amodra@bigpond.net.au>
42 * Makefile.am: Run "make dep-am".
43 * Makefile.in: Regenerate.
45 2008-05-02 H.J. Lu <hongjiu.lu@intel.com>
47 * i386-dis.c (MOVBE_Fixup): New.
49 (PREFIX_0F3880): Likewise.
50 (PREFIX_0F3881): Likewise.
51 (PREFIX_0F38F0): Updated.
52 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
53 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
54 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
56 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
58 (cpu_flags): Add CpuMovbe and CpuEPT.
60 * i386-opc.h (CpuMovbe): New.
63 (i386_cpu_flags): Add cpumovbe and cpuept.
65 * i386-opc.tbl: Add entries for movbe and EPT instructions.
66 * i386-init.h: Regenerated.
67 * i386-tbl.h: Likewise.
69 2008-04-29 Adam Nemet <anemet@caviumnetworks.com>
71 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
72 the two drem and the two dremu macros.
74 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
76 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
77 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
78 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
79 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
81 2008-04-25 David S. Miller <davem@davemloft.net>
83 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
84 instead of %sys_tick_cmpr, as suggested in architecture manuals.
86 2008-04-23 Paolo Bonzini <bonzini@gnu.org>
88 * aclocal.m4: Regenerate.
89 * configure: Regenerate.
91 2008-04-23 David S. Miller <davem@davemloft.net>
93 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
95 (prefetch_table): Add missing values.
97 2008-04-22 H.J. Lu <hongjiu.lu@intel.com>
99 * i386-gen.c (opcode_modifiers): Add NoAVX.
101 * i386-opc.h (NoAVX): New.
103 (i386_opcode_modifier): Add noavx.
105 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
106 instructions which don't have AVX equivalent.
107 * i386-tbl.h: Regenerated.
109 2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
111 * i386-dis.c (OP_VEX_FMA): New.
112 (OP_EX_VexImmW): Likewise.
114 (Vex128FMA): Likewise.
115 (EXVexImmW): Likewise.
116 (get_vex_imm8): Likewise.
117 (OP_EX_VexReg): Likewise.
118 (vex_i4_done): Renamed to ...
120 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
121 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
123 (print_insn): Updated.
124 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
125 (OP_REG_VexI4): Check invalid high registers.
127 2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
128 Michael Meissner <michael.meissner@amd.com>
130 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
131 * i386-tbl.h: Regenerate from i386-opc.tbl.
133 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
135 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
136 accept Power E500MC instructions.
137 (print_ppc_disassembler_options): Document -Me500mc.
138 * ppc-opc.c (DUIS, DUI, T): New.
139 (XRT, XRTRA): Likewise.
141 (powerpc_opcodes): Add new Power E500MC instructions.
143 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
145 * s390-dis.c (init_disasm): Evaluate disassembler_options.
146 (print_s390_disassembler_options): New function.
147 * disassemble.c (disassembler_usage): Invoke
148 print_s390_disassembler_options.
150 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
152 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
153 of local variables used for mnemonic parsing: prefix, suffix and
156 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
158 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
159 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
160 (s390_crb_extensions): New extensions table.
161 (insertExpandedMnemonic): Handle '$' tag.
162 * s390-opc.txt: Remove conditional jump variants which can now
163 be expanded automatically.
164 Replace '*' tag with '$' in the compare and branch instructions.
166 2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
168 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
169 (PREFIX_VEX_3AXX): Likewis.
171 2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
173 * i386-opc.tbl: Remove 4 extra blank lines.
175 2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
177 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
178 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
179 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
180 * i386-opc.tbl: Likewise.
182 * i386-opc.h (CpuCLMUL): Renamed to ...
185 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
187 * i386-init.h: Regenerated.
189 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
191 * i386-dis.c (OP_E_register): New.
192 (OP_E_memory): Likewise.
194 (OP_EX_Vex): Likewise.
195 (OP_EX_VexW): Likewise.
196 (OP_XMM_Vex): Likewise.
197 (OP_XMM_VexW): Likewise.
198 (OP_REG_VexI4): Likewise.
199 (PCLMUL_Fixup): Likewise.
200 (VEXI4_Fixup): Likewise.
201 (VZERO_Fixup): Likewise.
202 (VCMP_Fixup): Likewise.
203 (VPERMIL2_Fixup): Likewise.
204 (rex_original): Likewise.
205 (rex_ignored): Likewise.
226 (VPERMIL2): Likewise.
227 (xmm_mode): Likewise.
228 (xmmq_mode): Likewise.
229 (ymmq_mode): Likewise.
230 (vex_mode): Likewise.
231 (vex128_mode): Likewise.
232 (vex256_mode): Likewise.
233 (USE_VEX_C4_TABLE): Likewise.
234 (USE_VEX_C5_TABLE): Likewise.
235 (USE_VEX_LEN_TABLE): Likewise.
236 (VEX_C4_TABLE): Likewise.
237 (VEX_C5_TABLE): Likewise.
238 (VEX_LEN_TABLE): Likewise.
239 (REG_VEX_XX): Likewise.
240 (MOD_VEX_XXX): Likewise.
241 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
242 (PREFIX_0F3A44): Likewise.
243 (PREFIX_0F3ADF): Likewise.
244 (PREFIX_VEX_XXX): Likewise.
246 (VEX_OF38): Likewise.
247 (VEX_OF3A): Likewise.
248 (VEX_LEN_XXX): Likewise.
250 (need_vex): Likewise.
251 (need_vex_reg): Likewise.
252 (vex_i4_done): Likewise.
253 (vex_table): Likewise.
254 (vex_len_table): Likewise.
255 (OP_REG_VexI4): Likewise.
256 (vex_cmp_op): Likewise.
257 (pclmul_op): Likewise.
258 (vpermil2_op): Likewise.
261 (PREFIX_0F38F0): Likewise.
262 (PREFIX_0F3A60): Likewise.
263 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
264 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
265 and PREFIX_VEX_XXX entries.
266 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
267 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
269 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
270 Add MOD_VEX_XXX entries.
271 (ckprefix): Initialize rex_original and rex_ignored. Store the
272 REX byte in rex_original.
273 (get_valid_dis386): Handle the implicit prefix in VEX prefix
274 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
275 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
276 calling get_valid_dis386. Use rex_original and rex_ignored when
278 (putop): Handle "XY".
279 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
281 (OP_E_extended): Updated to use OP_E_register and
283 (OP_XMM): Handle VEX.
285 (XMM_Fixup): Likewise.
286 (CMP_Fixup): Use ARRAY_SIZE.
288 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
289 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
290 (operand_type_init): Add OPERAND_TYPE_REGYMM and
291 OPERAND_TYPE_VEX_IMM4.
292 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
293 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
294 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
295 VexImmExt and SSE2AVX.
296 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
298 * i386-opc.h (CpuAVX): New.
300 (CpuCLMUL): Likewise.
311 (Vex3Sources): Likewise.
312 (VexImmExt): Likewise.
316 (Vex_Imm4): Likewise.
317 (Implicit1stXmm0): Likewise.
320 (ByteOkIntel): Likewise.
323 (Unspecified): Likewise.
325 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
326 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
327 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
328 vex3sources, veximmext and sse2avx.
329 (i386_operand_type): Add regymm, ymmword and vex_imm4.
331 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
333 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
335 * i386-init.h: Regenerated.
336 * i386-tbl.h: Likewise.
338 2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
340 From Robin Getz <robin.getz@analog.com>
341 * bfin-dis.c (bu32): Typedef.
342 (enum const_forms_t): Add c_uimm32 and c_huimm32.
343 (constant_formats[]): Add uimm32 and huimm16.
348 (luimm16_val): Define.
349 (struct saved_state): Define.
350 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
351 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
352 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
354 (decode_LDIMMhalf_0): Print out the whole register value.
356 From Jie Zhang <jie.zhang@analog.com>
357 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
358 multiply and multiply-accumulate to data register instruction.
360 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
361 c_imm32, c_huimm32e): Define.
362 (constant_formats): Add flags for printing decimal, leading spaces, and
364 (comment, parallel): Add global flags in all disassembly.
365 (fmtconst): Take advantage of new flags, and print default in hex.
366 (fmtconst_val): Likewise.
367 (decode_macfunc): Be consistant with spaces, tabs, comments,
368 capitalization in disassembly, fix minor coding style issues.
369 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
370 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
371 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
372 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
373 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
374 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
375 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
376 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
377 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
378 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
379 _print_insn_bfin, print_insn_bfin): Likewise.
381 2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
383 * aclocal.m4: Regenerate.
384 * configure: Likewise.
385 * Makefile.in: Likewise.
387 2008-03-13 Alan Modra <amodra@bigpond.net.au>
389 * Makefile.am: Run "make dep-am".
390 * Makefile.in: Regenerate.
391 * configure: Regenerate.
393 2008-03-07 Alan Modra <amodra@bigpond.net.au>
395 * ppc-opc.c (powerpc_opcodes): Order and format.
397 2008-03-01 H.J. Lu <hongjiu.lu@intel.com>
399 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
400 * i386-tbl.h: Regenerated.
402 2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
404 * i386-opc.tbl: Disallow 16-bit near indirect branches for
406 * i386-tbl.h: Regenerated.
408 2008-02-21 Jan Beulich <jbeulich@novell.com>
410 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
411 and Fword for far indirect jmp. Allow Reg16 and Word for near
412 indirect jmp on x86-64. Disallow Fword for lcall.
413 * i386-tbl.h: Re-generate.
415 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
417 * cr16-opc.c (cr16_num_optab): Defined
419 2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
421 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
422 * i386-init.h: Regenerated.
424 2008-02-14 Nick Clifton <nickc@redhat.com>
427 * configure.in (SHARED_LIBADD): Select the correct host specific
428 file extension for shared libraries.
429 * configure: Regenerate.
431 2008-02-13 Jan Beulich <jbeulich@novell.com>
433 * i386-opc.h (RegFlat): New.
434 * i386-reg.tbl (flat): Add.
435 * i386-tbl.h: Re-generate.
437 2008-02-13 Jan Beulich <jbeulich@novell.com>
439 * i386-dis.c (a_mode): New.
440 (cond_jump_mode): Adjust.
441 (Ma): Change to a_mode.
442 (intel_operand_size): Handle a_mode.
443 * i386-opc.tbl: Allow Dword and Qword for bound.
444 * i386-tbl.h: Re-generate.
446 2008-02-13 Jan Beulich <jbeulich@novell.com>
448 * i386-gen.c (process_i386_registers): Process new fields.
449 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
450 unsigned char. Add dw2_regnum and Dw2Inval.
451 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
453 * i386-tbl.h: Re-generate.
455 2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
457 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
458 * i386-init.h: Updated.
460 2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
462 * i386-gen.c (cpu_flags): Add CpuXsave.
464 * i386-opc.h (CpuXsave): New.
466 (i386_cpu_flags): Add cpuxsave.
468 * i386-dis.c (MOD_0FAE_REG_4): New.
469 (RM_0F01_REG_2): Likewise.
470 (MOD_0FAE_REG_5): Updated.
471 (RM_0F01_REG_3): Likewise.
472 (reg_table): Use MOD_0FAE_REG_4.
473 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
475 (rm_table): Add RM_0F01_REG_2.
477 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
478 * i386-init.h: Regenerated.
479 * i386-tbl.h: Likewise.
481 2008-02-11 Jan Beulich <jbeulich@novell.com>
483 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
484 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
485 * i386-tbl.h: Re-generate.
487 2008-02-04 H.J. Lu <hongjiu.lu@intel.com>
490 * configure: Regenerated.
492 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
494 * mips-dis.c: Update copyright.
495 (mips_arch_choices): Add Octeon.
496 * mips-opc.c: Update copyright.
498 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
500 2008-01-29 Alan Modra <amodra@bigpond.net.au>
502 * ppc-opc.c: Support optional L form mtmsr.
504 2008-01-24 H.J. Lu <hongjiu.lu@intel.com>
506 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
508 2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
510 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
511 * i386-init.h: Regenerated.
513 2008-01-23 Tristan Gingold <gingold@adacore.com>
515 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
516 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
518 2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
520 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
521 (cpu_flags): Likewise.
523 * i386-opc.h (CpuMMX2): Removed.
526 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
527 * i386-init.h: Regenerated.
528 * i386-tbl.h: Likewise.
530 2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
532 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
534 * i386-init.h: Regenerated.
536 2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
538 * i386-opc.tbl: Use Qword on movddup.
539 * i386-tbl.h: Regenerated.
541 2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
543 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
544 * i386-tbl.h: Regenerated.
546 2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
548 * i386-dis.c (Mx): New.
549 (PREFIX_0FC3): Likewise.
550 (PREFIX_0FC7_REG_6): Updated.
551 (dis386_twobyte): Use PREFIX_0FC3.
552 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
553 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
556 2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
558 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
559 (operand_types): Add Mem.
561 * i386-opc.h (IntelSyntax): New.
562 * i386-opc.h (Mem): New.
564 (Opcode_Modifier_Max): Updated.
565 (i386_opcode_modifier): Add intelsyntax.
566 (i386_operand_type): Add mem.
568 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
571 * i386-reg.tbl: Add size for accumulator.
573 * i386-init.h: Regenerated.
574 * i386-tbl.h: Likewise.
576 2008-01-13 H.J. Lu <hongjiu.lu@intel.com>
578 * i386-opc.h (Byte): Fix a typo.
580 2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
583 * i386-gen.c (operand_type_init): Add Dword to
584 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
585 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
587 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
588 Xmmword, Unspecified and Anysize.
589 (set_bitfield): Make Mmword an alias of Qword. Make Oword
592 * i386-opc.h (CheckSize): Removed.
600 (i386_opcode_modifier): Remove checksize, byte, word, dword,
604 (Unspecified): Likewise.
606 (i386_operand_type): Add byte, word, dword, fword, qword,
607 tbyte xmmword, unspecified and anysize.
609 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
610 Tbyte, Xmmword, Unspecified and Anysize.
612 * i386-reg.tbl: Add size for accumulator.
614 * i386-init.h: Regenerated.
615 * i386-tbl.h: Likewise.
617 2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
619 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
621 (reg_table): Updated.
622 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
623 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
625 2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
627 * i386-gen.c (set_bitfield): Use fail () on error.
629 2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
631 * i386-gen.c (lineno): New.
632 (filename): Likewise.
633 (set_bitfield): Report filename and line numer on error.
634 (process_i386_opcodes): Set filename and update lineno.
635 (process_i386_registers): Likewise.
637 2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
639 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
642 * i386-opc.h (IntelMnemonic): Renamed to ..
644 (Opcode_Modifier_Max): Updated.
645 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
648 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
649 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
650 * i386-tbl.h: Regenerated.
652 2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
654 * i386-gen.c: Update copyright to 2008.
655 * i386-opc.h: Likewise.
656 * i386-opc.tbl: Likewise.
658 * i386-init.h: Regenerated.
659 * i386-tbl.h: Likewise.
661 2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
663 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
664 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
665 * i386-tbl.h: Regenerated.
667 2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
669 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
671 (cpu_flags): Likewise.
673 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
674 (CpuSSE4_2_Or_ABM): Likewise.
676 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
678 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
679 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
680 and CpuPadLock, respectively.
681 * i386-init.h: Regenerated.
682 * i386-tbl.h: Likewise.
684 2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
686 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
688 * i386-opc.h (No_xSuf): Removed.
689 (CheckSize): Updated.
691 * i386-tbl.h: Regenerated.
693 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
695 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
696 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
698 (cpu_flags): Add CpuSSE4_2_Or_ABM.
700 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
702 (i386_cpu_flags): Add cpusse4_2_or_abm.
704 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
705 CpuABM|CpuSSE4_2 on popcnt.
706 * i386-init.h: Regenerated.
707 * i386-tbl.h: Likewise.
709 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
711 * i386-opc.h: Update comments.
713 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
715 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
716 * i386-opc.h: Likewise.
717 * i386-opc.tbl: Likewise.
719 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
722 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
723 Byte, Word, Dword, QWord and Xmmword.
725 * i386-opc.h (No_xSuf): New.
726 (CheckSize): Likewise.
733 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
734 Dword, QWord and Xmmword.
736 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
738 * i386-tbl.h: Regenerated.
740 2008-01-02 Mark Kettenis <kettenis@gnu.org>
742 * m88k-dis.c (instructions): Fix fcvt.* instructions.
745 For older changes see ChangeLog-2007
751 version-control: never