1 2015-12-12 Alan Modra <amodra@gmail.com>
4 * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
5 (powerpc_opcodes): Remove single-operand mfcr.
7 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
9 * aarch64-asm.c (aarch64_ins_hint): New.
10 * aarch64-asm.h (aarch64_ins_hint): Declare.
11 * aarch64-dis.c (aarch64_ext_hint): New.
12 * aarch64-dis.h (aarch64_ext_hint): Declare.
13 * aarch64-opc-2.c: Regenerate.
14 * aarch64-opc.c (aarch64_hint_options): New.
15 * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
17 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
19 * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
21 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
23 * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
24 pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
25 pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
27 (aarch64_sys_reg_supported_p): Add architecture feature tests for
30 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
32 * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
33 (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
34 feature test for "s1e1rp" and "s1e1wp".
36 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
38 * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
39 (aarch64_sys_ins_reg_supported_p): New.
41 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
43 * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
44 with aarch64_sys_ins_reg_has_xt.
45 (aarch64_ext_sysins_op): Likewise.
46 * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
48 (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
49 (aarch64_sys_regs_dc): Likewise.
50 (aarch64_sys_regs_at): Likewise.
51 (aarch64_sys_regs_tlbi): Likewise.
52 (aarch64_sys_ins_reg_has_xt): New.
54 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
56 * aarch64-opc.c (aarch64_sys_regs): Add "uao".
57 (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
58 (aarch64_pstatefields): Add "uao".
59 (aarch64_pstatefield_supported_p): Add checks for "uao".
61 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
63 * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
64 "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
65 "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
66 (aarch64_sys_reg_supported_p): Add architecture feature tests for
69 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
71 * aarch64-asm-2.c: Regenerate.
72 * aarch64-dis-2.c: Regenerate.
73 * aarch64-tbl.h (aarch64_feature_ras): New.
75 (aarch64_opcode_table): Add "esb".
77 2015-12-09 H.J. Lu <hongjiu.lu@intel.com>
79 * i386-dis.c (MOD_0F01_REG_5): New.
80 (RM_0F01_REG_5): Likewise.
81 (reg_table): Use MOD_0F01_REG_5.
82 (mod_table): Add MOD_0F01_REG_5.
83 (rm_table): Add RM_0F01_REG_5.
84 * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
85 (cpu_flags): Add CpuOSPKE.
86 * i386-opc.h (CpuOSPKE): New.
87 (i386_cpu_flags): Add cpuospke.
88 * i386-opc.tbl: Add rdpkru and wrpkru instructions.
89 * i386-init.h: Regenerated.
90 * i386-tbl.h: Likewise.
92 2015-12-07 DJ Delorie <dj@redhat.com>
94 * rl78-decode.opc: Enable MULU for all ISAs.
95 * rl78-decode.c: Regenerate.
97 2015-12-07 Alan Modra <amodra@gmail.com>
99 * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
102 2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
104 * arc-dis.c (special_flag_p): Match full mnemonic.
105 * arc-opc.c (print_insn_arc): Check section size to read
106 appropriate number of bytes. Fix printing.
107 * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
110 2015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
112 * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
115 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
117 * aarch64-asm-2.c: Regenerate.
118 * aarch64-dis-2.c: Regenerate.
119 * aarch64-opc-2.c: Regenerate.
120 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
121 (QL_INT2FP_H, QL_FP2INT_H): New.
122 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
125 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
126 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
127 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
128 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
129 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
130 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
133 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
135 * aarch64-opc.c (half_conv_t): New.
136 (expand_fp_imm): Replace is_dp flag with the parameter size to
137 specify the number of bytes for the required expansion. Treat
138 a 16-bit expansion like a 32-bit expansion. Add check for an
139 unsupported size request. Update comment.
140 (aarch64_print_operand): Update to support 16-bit floating point
141 values. Update for changes to expand_fp_imm.
143 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
145 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
148 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
150 * aarch64-asm-2.c: Regenerate.
151 * aarch64-dis-2.c: Regenerate.
152 * aarch64-opc-2.c: Regenerate.
153 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
156 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
158 * aarch64-asm-2.c: Regenerate.
159 * aarch64-asm.c (convert_bfc_to_bfm): New.
160 (convert_to_real): Add case for OP_BFC.
161 * aarch64-dis-2.c: Regenerate.
162 * aarch64-dis.c: (convert_bfm_to_bfc): New.
163 (convert_to_alias): Add case for OP_BFC.
164 * aarch64-opc-2.c: Regenerate.
165 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
166 to allow width operand in three-operand instructions.
167 * aarch64-tbl.h (QL_BF1): New.
168 (aarch64_feature_v8_2): New.
170 (aarch64_opcode_table): Add "bfc".
172 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
174 * aarch64-asm-2.c: Regenerate.
175 * aarch64-dis-2.c: Regenerate.
176 * aarch64-dis.c: Weaken assert.
177 * aarch64-gen.c: Include the instruction in the list of its
180 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
182 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
183 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
186 2015-11-23 Tristan Gingold <gingold@adacore.com>
188 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
190 2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
192 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
193 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
194 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
195 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
196 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
197 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
198 cnthv_ctl_el2, cnthv_cval_el2.
199 (aarch64_sys_reg_supported_p): Update for the new system
202 2015-11-20 Nick Clifton <nickc@redhat.com>
205 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
207 2015-11-20 Nick Clifton <nickc@redhat.com>
209 * po/zh_CN.po: Updated simplified Chinese translation.
211 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
213 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
214 of MSR PAN immediate operand.
216 2015-11-16 Nick Clifton <nickc@redhat.com>
218 * rx-dis.c (condition_names): Replace always and never with
219 invalid, since the always/never conditions can never be legal.
221 2015-11-13 Tristan Gingold <gingold@adacore.com>
223 * configure: Regenerate.
225 2015-11-11 Alan Modra <amodra@gmail.com>
226 Peter Bergner <bergner@vnet.ibm.com>
228 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
229 Add PPC_OPCODE_VSX3 to the vsx entry.
230 (powerpc_init_dialect): Set default dialect to power9.
231 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
232 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
233 extract_l1 insert_xtq6, extract_xtq6): New static functions.
234 (insert_esync): Test for illegal L operand value.
235 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
236 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
237 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
238 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
239 PPCVSX3): New defines.
240 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
241 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
242 <mcrxr>: Use XBFRARB_MASK.
243 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
244 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
245 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
246 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
247 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
248 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
249 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
250 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
251 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
252 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
253 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
254 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
255 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
256 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
257 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
258 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
259 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
260 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
261 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
262 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
263 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
264 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
265 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
266 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
267 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
268 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
269 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
270 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
271 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
272 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
273 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
274 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
276 2015-11-02 Nick Clifton <nickc@redhat.com>
278 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
280 * rx-decode.c: Regenerate.
282 2015-11-02 Nick Clifton <nickc@redhat.com>
284 * rx-decode.opc (rx_disp): If the displacement is zero, set the
285 type to RX_Operand_Zero_Indirect.
286 * rx-decode.c: Regenerate.
287 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
289 2015-10-28 Yao Qi <yao.qi@linaro.org>
291 * aarch64-dis.c (aarch64_decode_insn): Add one argument
292 noaliases_p. Update comments. Pass noaliases_p rather than
293 no_aliases to aarch64_opcode_decode.
294 (print_insn_aarch64_word): Pass no_aliases to
297 2015-10-27 Vinay <Vinay.G@kpit.com>
300 * rl78-decode.opc (MOV): Added offset to DE register in index
302 * rl78-decode.c: Regenerate.
304 2015-10-27 Vinay Kumar <vinay.g@kpit.com>
307 * rl78-decode.opc: Add 's' print operator to instructions that
308 access system registers.
309 * rl78-decode.c: Regenerate.
310 * rl78-dis.c (print_insn_rl78_common): Decode all system
313 2015-10-27 Vinay Kumar <vinay.g@kpit.com>
316 * rl78-decode.opc: Add 'a' print operator to mov instructions
317 using stack pointer plus index addressing.
318 * rl78-decode.c: Regenerate.
320 2015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
322 * s390-opc.c: Fix comment.
323 * s390-opc.txt: Change instruction type for troo, trot, trto, and
324 trtt to RRF_U0RER since the second parameter does not need to be a
327 2015-10-08 Nick Clifton <nickc@redhat.com>
329 * arc-dis.c (print_insn_arc): Initiallise insn array.
331 2015-10-07 Yao Qi <yao.qi@linaro.org>
333 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
334 'name' rather than 'template'.
335 * aarch64-opc.c (aarch64_print_operand): Likewise.
337 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
339 * arc-dis.c: Revamped file for ARC support
340 * arc-dis.h: Likewise.
341 * arc-ext.c: Likewise.
342 * arc-ext.h: Likewise.
343 * arc-opc.c: Likewise.
344 * arc-fxi.h: New file.
345 * arc-regs.h: Likewise.
346 * arc-tbl.h: Likewise.
348 2015-10-02 Yao Qi <yao.qi@linaro.org>
350 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
351 argument insn type to aarch64_insn. Rename to ...
352 (aarch64_decode_insn): ... it.
353 (print_insn_aarch64_word): Caller updated.
355 2015-10-02 Yao Qi <yao.qi@linaro.org>
357 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
358 (print_insn_aarch64_word): Caller updated.
360 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
362 * s390-mkopc.c (main): Parse htm and vx flag.
363 * s390-opc.txt: Mark instructions from the hardware transactional
364 memory and vector facilities with the "htm"/"vx" flag.
366 2015-09-28 Nick Clifton <nickc@redhat.com>
368 * po/de.po: Updated German translation.
370 2015-09-28 Tom Rix <tom@bumblecow.com>
372 * ppc-opc.c (PPC500): Mark some opcodes as invalid
374 2015-09-23 Nick Clifton <nickc@redhat.com>
376 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
378 * tic30-dis.c (print_branch): Likewise.
379 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
380 value before left shifting.
381 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
382 * hppa-dis.c (print_insn_hppa): Likewise.
383 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
385 * msp430-dis.c (msp430_singleoperand): Likewise.
386 (msp430_doubleoperand): Likewise.
387 (print_insn_msp430): Likewise.
388 * nds32-asm.c (parse_operand): Likewise.
389 * sh-opc.h (MASK): Likewise.
390 * v850-dis.c (get_operand_value): Likewise.
392 2015-09-22 Nick Clifton <nickc@redhat.com>
394 * rx-decode.opc (bwl): Use RX_Bad_Size.
396 (ubwl): Likewise. Rename to ubw.
397 (uBWL): Rename to uBW.
398 Replace all references to uBWL with uBW.
399 * rx-decode.c: Regenerate.
400 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
401 (opsize_names): Likewise.
402 (print_insn_rx): Detect and report RX_Bad_Size.
404 2015-09-22 Anton Blanchard <anton@samba.org>
406 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
408 2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
410 * sparc-dis.c (print_insn_sparc): Handle the privileged register
413 2015-08-24 Jan Stancek <jstancek@redhat.com>
415 * i386-dis.c (print_insn): Fix decoding of three byte operands.
417 2015-08-21 Alexander Fomin <alexander.fomin@intel.com>
420 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
421 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
422 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
423 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
424 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
425 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
426 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
427 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
428 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
429 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
430 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
431 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
432 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
433 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
434 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
435 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
436 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
437 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
438 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
439 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
440 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
441 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
442 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
443 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
444 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
445 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
446 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
447 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
448 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
449 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
450 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
451 (vex_w_table): Replace terminals with MOD_TABLE entries for
452 most of mask instructions.
454 2015-08-17 Alan Modra <amodra@gmail.com>
456 * cgen.sh: Trim trailing space from cgen output.
457 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
458 (print_dis_table): Likewise.
459 * opc2c.c (dump_lines): Likewise.
460 (orig_filename): Warning fix.
461 * ia64-asmtab.c: Regenerate.
463 2015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
465 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
466 and higher with ARM instruction set will now mark the 26-bit
467 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
468 (arm_opcodes): Fix for unpredictable nop being recognized as a
471 2015-08-12 Simon Dardis <simon.dardis@imgtec.com>
473 * micromips-opc.c (micromips_opcodes): Re-order table so that move
474 based on 'or' is first.
475 * mips-opc.c (mips_builtin_opcodes): Ditto.
477 2015-08-11 Nick Clifton <nickc@redhat.com>
480 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
483 2015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
485 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
487 2015-08-07 Amit Pawar <Amit.Pawar@amd.com>
489 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
490 * i386-init.h: Regenerated.
492 2015-07-30 H.J. Lu <hongjiu.lu@intel.com>
495 * i386-dis.c (MOD_0FC3): New.
496 (PREFIX_0FC3): Renamed to ...
497 (PREFIX_MOD_0_0FC3): This.
498 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
499 (prefix_table): Replace Ma with Ev on movntiS.
500 (mod_table): Add MOD_0FC3.
502 2015-07-27 H.J. Lu <hongjiu.lu@intel.com>
504 * configure: Regenerated.
506 2015-07-23 Alan Modra <amodra@gmail.com>
509 * i386-dis.c (get64): Avoid signed integer overflow.
511 2015-07-22 Alexander Fomin <alexander.fomin@intel.com>
514 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
515 "EXEvexHalfBcstXmmq" for the second operand.
516 (EVEX_W_0F79_P_2): Likewise.
517 (EVEX_W_0F7A_P_2): Likewise.
518 (EVEX_W_0F7B_P_2): Likewise.
520 2015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
522 * arm-dis.c (print_insn_coprocessor): Added support for quarter
523 float bitfield format.
524 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
525 quarter float bitfield format.
527 2015-07-14 H.J. Lu <hongjiu.lu@intel.com>
529 * configure: Regenerated.
531 2015-07-03 Alan Modra <amodra@gmail.com>
533 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
534 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
535 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
537 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
538 Cesar Philippidis <cesar@codesourcery.com>
540 * nios2-dis.c (nios2_extract_opcode): New.
541 (nios2_disassembler_state): New.
542 (nios2_find_opcode_hash): Use mach parameter to select correct
544 (nios2_print_insn_arg): Extend to support new R2 argument letters
546 (print_insn_nios2): Check for 16-bit instruction at end of memory.
547 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
548 (NIOS2_NUM_OPCODES): Rename to...
549 (NIOS2_NUM_R1_OPCODES): This.
550 (nios2_r2_opcodes): New.
551 (NIOS2_NUM_R2_OPCODES): New.
552 (nios2_num_r2_opcodes): New.
553 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
554 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
555 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
556 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
557 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
559 2015-06-30 Amit Pawar <Amit.Pawar@amd.com>
561 * i386-dis.c (OP_Mwaitx): New.
562 (rm_table): Add monitorx/mwaitx.
563 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
564 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
565 (operand_type_init): Add CpuMWAITX.
566 * i386-opc.h (CpuMWAITX): New.
567 (i386_cpu_flags): Add cpumwaitx.
568 * i386-opc.tbl: Add monitorx and mwaitx.
569 * i386-init.h: Regenerated.
570 * i386-tbl.h: Likewise.
572 2015-06-22 Peter Bergner <bergner@vnet.ibm.com>
574 * ppc-opc.c (insert_ls): Test for invalid LS operands.
575 (insert_esync): New function.
576 (LS, WC): Use insert_ls.
577 (ESYNC): Use insert_esync.
579 2015-06-22 Nick Clifton <nickc@redhat.com>
581 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
582 requested region lies beyond it.
583 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
584 looking for 32-bit insns.
585 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
587 * sh-dis.c (print_insn_sh): Likewise.
588 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
589 blocks of instructions.
590 * vax-dis.c (print_insn_vax): Check that the requested address
591 does not clash with the stop_vma.
593 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
595 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
596 * ppc-opc.c (FXM4): Add non-zero optional value.
599 (insert_fxm): Handle new default operand value.
600 (extract_fxm): Likewise.
601 (insert_tbr): Likewise.
602 (extract_tbr): Likewise.
604 2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
606 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
608 2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
610 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
612 2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
614 * ppc-opc.c: Add comment accidentally removed by old commit.
617 2015-06-04 Peter Bergner <bergner@vnet.ibm.com>
619 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
621 2015-06-04 Nick Clifton <nickc@redhat.com>
624 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
626 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
628 * arm-dis.c (arm_opcodes): Add "setpan".
629 (thumb_opcodes): Add "setpan".
631 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
633 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
636 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
638 * aarch64-tbl.h (aarch64_feature_rdma): New.
640 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
641 * aarch64-asm-2.c: Regenerate.
642 * aarch64-dis-2.c: Regenerate.
643 * aarch64-opc-2.c: Regenerate.
645 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
647 * aarch64-tbl.h (aarch64_feature_lor): New.
649 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
651 * aarch64-asm-2.c: Regenerate.
652 * aarch64-dis-2.c: Regenerate.
653 * aarch64-opc-2.c: Regenerate.
655 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
657 * aarch64-opc.c (F_ARCHEXT): New.
658 (aarch64_sys_regs): Add "pan".
659 (aarch64_sys_reg_supported_p): New.
660 (aarch64_pstatefields): Add "pan".
661 (aarch64_pstatefield_supported_p): New.
663 2015-06-01 Jan Beulich <jbeulich@suse.com>
665 * i386-tbl.h: Regenerate.
667 2015-06-01 Jan Beulich <jbeulich@suse.com>
669 * i386-dis.c (print_insn): Swap rounding mode specifier and
670 general purpose register in Intel mode.
672 2015-06-01 Jan Beulich <jbeulich@suse.com>
674 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
675 * i386-tbl.h: Regenerate.
677 2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
679 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
680 * i386-init.h: Regenerated.
682 2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
685 * i386-dis.c: Add comments for '@'.
686 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
687 (enum x86_64_isa): New.
689 (print_i386_disassembler_options): Add amd64 and intel64.
690 (print_insn): Handle amd64 and intel64.
692 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
693 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
694 * i386-opc.h (AMD64): New.
695 (CpuIntel64): Likewise.
696 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
697 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
698 Mark direct call/jmp without Disp16|Disp32 as Intel64.
699 * i386-init.h: Regenerated.
700 * i386-tbl.h: Likewise.
702 2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
704 * ppc-opc.c (IH) New define.
705 (powerpc_opcodes) <wait>: Do not enable for POWER7.
706 <tlbie>: Add RS operand for POWER7.
707 <slbia>: Add IH operand for POWER6.
709 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
711 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
714 * i386-tbl.h: Regenerated.
716 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
718 * configure.ac: Support bfd_iamcu_arch.
719 * disassemble.c (disassembler): Support bfd_iamcu_arch.
720 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
721 CPU_IAMCU_COMPAT_FLAGS.
722 (cpu_flags): Add CpuIAMCU.
723 * i386-opc.h (CpuIAMCU): New.
724 (i386_cpu_flags): Add cpuiamcu.
725 * configure: Regenerated.
726 * i386-init.h: Likewise.
727 * i386-tbl.h: Likewise.
729 2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
732 * i386-dis.c (X86_64_E8): New.
733 (X86_64_E9): Likewise.
734 Update comments on 'T', 'U', 'V'. Add comments for '^'.
735 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
736 (x86_64_table): Add X86_64_E8 and X86_64_E9.
737 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
739 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
742 2015-04-30 DJ Delorie <dj@redhat.com>
744 * disassemble.c (disassembler): Choose suitable disassembler based
746 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
747 it to decode mul/div insns.
748 * rl78-decode.c: Regenerate.
749 * rl78-dis.c (print_insn_rl78): Rename to...
750 (print_insn_rl78_common): ...this, take ISA parameter.
751 (print_insn_rl78): New.
752 (print_insn_rl78_g10): New.
753 (print_insn_rl78_g13): New.
754 (print_insn_rl78_g14): New.
755 (rl78_get_disassembler): New.
757 2015-04-29 Nick Clifton <nickc@redhat.com>
759 * po/fr.po: Updated French translation.
761 2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
763 * ppc-opc.c (DCBT_EO): New define.
764 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
768 <waitrsv>: Do not enable for POWER7 and later.
769 <waitimpl>: Likewise.
770 <dcbt>: Default to the two operand form of the instruction for all
771 "old" cpus. For "new" cpus, use the operand ordering that matches
772 whether the cpu is server or embedded.
775 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
777 * s390-opc.c: New instruction type VV0UU2.
778 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
781 2015-04-23 Jan Beulich <jbeulich@suse.com>
783 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
784 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
785 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
786 (vfpclasspd, vfpclassps): Add %XZ.
788 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
790 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
791 (PREFIX_UD_REPZ): Likewise.
792 (PREFIX_UD_REPNZ): Likewise.
793 (PREFIX_UD_DATA): Likewise.
794 (PREFIX_UD_ADDR): Likewise.
795 (PREFIX_UD_LOCK): Likewise.
797 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
799 * i386-dis.c (prefix_requirement): Removed.
800 (print_insn): Don't set prefix_requirement. Check
801 dp->prefix_requirement instead of prefix_requirement.
803 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
806 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
807 (PREFIX_MOD_0_0FC7_REG_6): This.
808 (PREFIX_MOD_3_0FC7_REG_6): New.
809 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
810 (prefix_table): Replace PREFIX_0FC7_REG_6 with
811 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
812 PREFIX_MOD_3_0FC7_REG_7.
813 (mod_table): Replace PREFIX_0FC7_REG_6 with
814 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
815 PREFIX_MOD_3_0FC7_REG_7.
817 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
819 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
820 (PREFIX_MANDATORY_REPNZ): Likewise.
821 (PREFIX_MANDATORY_DATA): Likewise.
822 (PREFIX_MANDATORY_ADDR): Likewise.
823 (PREFIX_MANDATORY_LOCK): Likewise.
824 (PREFIX_MANDATORY): Likewise.
825 (PREFIX_UD_SHIFT): Set to 8
826 (PREFIX_UD_REPZ): Updated.
827 (PREFIX_UD_REPNZ): Likewise.
828 (PREFIX_UD_DATA): Likewise.
829 (PREFIX_UD_ADDR): Likewise.
830 (PREFIX_UD_LOCK): Likewise.
831 (PREFIX_IGNORED_SHIFT): New.
832 (PREFIX_IGNORED_REPZ): Likewise.
833 (PREFIX_IGNORED_REPNZ): Likewise.
834 (PREFIX_IGNORED_DATA): Likewise.
835 (PREFIX_IGNORED_ADDR): Likewise.
836 (PREFIX_IGNORED_LOCK): Likewise.
837 (PREFIX_OPCODE): Likewise.
838 (PREFIX_IGNORED): Likewise.
839 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
840 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
841 (three_byte_table): Likewise.
842 (mod_table): Likewise.
843 (mandatory_prefix): Renamed to ...
844 (prefix_requirement): This.
845 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
846 Update PREFIX_90 entry.
847 (get_valid_dis386): Check prefix_requirement to see if a prefix
849 (print_insn): Replace mandatory_prefix with prefix_requirement.
851 2015-04-15 Renlin Li <renlin.li@arm.com>
853 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
854 use it for ssat and ssat16.
855 (print_insn_thumb32): Add handle case for 'D' control code.
857 2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
858 H.J. Lu <hongjiu.lu@intel.com>
860 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
861 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
862 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
863 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
864 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
865 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
866 Fill prefix_requirement field.
867 (struct dis386): Add prefix_requirement field.
868 (dis386): Fill prefix_requirement field.
869 (dis386_twobyte): Ditto.
870 (twobyte_has_mandatory_prefix_: Remove.
871 (reg_table): Fill prefix_requirement field.
872 (prefix_table): Ditto.
873 (x86_64_table): Ditto.
874 (three_byte_table): Ditto.
877 (vex_len_table): Ditto.
878 (vex_w_table): Ditto.
881 (print_insn): Use prefix_requirement.
882 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
883 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
886 2015-03-30 Mike Frysinger <vapier@gentoo.org>
888 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
890 2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
892 * Makefile.in: Regenerated.
894 2015-03-25 Anton Blanchard <anton@samba.org>
896 * ppc-dis.c (disassemble_init_powerpc): Only initialise
897 powerpc_opcd_indices and vle_opcd_indices once.
899 2015-03-25 Anton Blanchard <anton@samba.org>
901 * ppc-opc.c (powerpc_opcodes): Add slbfee.
903 2015-03-24 Terry Guo <terry.guo@arm.com>
905 * arm-dis.c (opcode32): Updated to use new arm feature struct.
906 (opcode16): Likewise.
907 (coprocessor_opcodes): Replace bit with feature struct.
908 (neon_opcodes): Likewise.
909 (arm_opcodes): Likewise.
910 (thumb_opcodes): Likewise.
911 (thumb32_opcodes): Likewise.
912 (print_insn_coprocessor): Likewise.
913 (print_insn_arm): Likewise.
914 (select_arm_features): Follow new feature struct.
916 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
918 * i386-dis.c (rm_table): Add clzero.
919 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
920 Add CPU_CLZERO_FLAGS.
921 (cpu_flags): Add CpuCLZERO.
922 * i386-opc.h: Add CpuCLZERO.
923 * i386-opc.tbl: Add clzero.
924 * i386-init.h: Re-generated.
925 * i386-tbl.h: Re-generated.
927 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
929 * mips-opc.c (decode_mips_operand): Fix constraint issues
930 with u and y operands.
932 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
934 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
936 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
938 * s390-opc.c: Add new IBM z13 instructions.
939 * s390-opc.txt: Likewise.
941 2015-03-10 Renlin Li <renlin.li@arm.com>
943 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
944 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
946 * aarch64-asm-2.c: Regenerate.
947 * aarch64-dis-2.c: Likewise.
948 * aarch64-opc-2.c: Likewise.
950 2015-03-03 Jiong Wang <jiong.wang@arm.com>
952 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
954 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
956 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
958 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
959 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
961 2015-02-23 Vinay <Vinay.G@kpit.com>
963 * rl78-decode.opc (MOV): Added space between two operands for
964 'mov' instruction in index addressing mode.
965 * rl78-decode.c: Regenerate.
967 2015-02-19 Pedro Alves <palves@redhat.com>
969 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
971 2015-02-10 Pedro Alves <palves@redhat.com>
972 Tom Tromey <tromey@redhat.com>
974 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
975 microblaze_and, microblaze_xor.
976 * microblaze-opc.h (opcodes): Adjust.
978 2015-01-28 James Bowman <james.bowman@ftdichip.com>
980 * Makefile.am: Add FT32 files.
981 * configure.ac: Handle FT32.
982 * disassemble.c (disassembler): Call print_insn_ft32.
983 * ft32-dis.c: New file.
984 * ft32-opc.c: New file.
985 * Makefile.in: Regenerate.
986 * configure: Regenerate.
987 * po/POTFILES.in: Regenerate.
989 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
991 * nds32-asm.c (keyword_sr): Add new system registers.
993 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
995 * s390-dis.c (s390_extract_operand): Support vector register
997 (s390_print_insn_with_opcode): Support new operands types and add
998 new handling of optional operands.
999 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
1000 and include opcode/s390.h instead.
1001 (struct op_struct): New field `flags'.
1002 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
1003 (dumpTable): Dump flags.
1004 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
1006 * s390-opc.c: Add new operands types, instruction formats, and
1008 (s390_opformats): Add new formats for .insn.
1009 * s390-opc.txt: Add new instructions.
1011 2015-01-01 Alan Modra <amodra@gmail.com>
1013 Update year range in copyright notice of all files.
1015 For older changes see ChangeLog-2014
1017 Copyright (C) 2015 Free Software Foundation, Inc.
1019 Copying and distribution of this file, with or without modification,
1020 are permitted in any medium without royalty provided the copyright
1021 notice and this notice are preserved.
1027 version-control: never