1 2013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
3 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
6 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
8 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
10 * Makefile.in: Regenerate.
11 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
14 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
16 * mips16-opc.c: Include mips-formats.h.
17 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
19 (decode_mips16_operand): New function.
20 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
21 (print_insn_arg): Handle OP_ENTRY_EXIT list.
22 Abort for OP_SAVE_RESTORE_LIST.
23 (print_mips16_insn_arg): Change interface. Use mips_operand
24 structures. Delete GET_OP_S. Move GET_OP definition to...
25 (print_insn_mips16): ...here. Call init_print_arg_state.
26 Update the call to print_mips16_insn_arg.
28 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
30 * mips-formats.h: New file.
31 * mips-opc.c: Include mips-formats.h.
32 (reg_0_map): New static array.
33 (decode_mips_operand): New function.
34 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
35 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
36 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
37 (int_c_map): New static arrays.
38 (decode_micromips_operand): New function.
39 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
40 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
41 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
42 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
43 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
44 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
45 (micromips_imm_b_map, micromips_imm_c_map): Delete.
46 (print_reg): New function.
47 (mips_print_arg_state): New structure.
48 (init_print_arg_state, print_insn_arg): New functions.
49 (print_insn_args): Change interface and use mips_operand structures.
50 Delete GET_OP_S. Move GET_OP definition to...
51 (print_insn_mips): ...here. Update the call to print_insn_args.
52 (print_insn_micromips): Use print_insn_args.
54 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
56 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
59 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
61 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
62 ADDA.S, MULA.S and SUBA.S.
64 2013-07-08 H.J. Lu <hongjiu.lu@intel.com>
67 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
68 * i386-tbl.h: Regenerated.
70 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
72 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
73 and SD A(B) macros up.
74 * micromips-opc.c (micromips_opcodes): Likewise.
76 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
78 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
81 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
83 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
84 MDMX-like instructions.
85 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
86 printing "Q" operands for INSN_5400 instructions.
88 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
90 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
92 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
95 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
97 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
99 * mips16-opc.c (mips16_opcodes): Likewise.
100 * micromips-opc.c (micromips_opcodes): Likewise.
101 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
102 (print_insn_mips16): Handle "+i".
103 (print_insn_micromips): Likewise. Conditionally preserve the
104 ISA bit for "a" but not for "+i".
106 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
108 * micromips-opc.c (WR_mhi): Rename to..
110 (micromips_opcodes): Update "movep" entry accordingly. Replace
112 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
113 (micromips_to_32_reg_h_map1): ...this.
114 (micromips_to_32_reg_i_map): Rename to...
115 (micromips_to_32_reg_h_map2): ...this.
116 (print_micromips_insn): Remove "mi" case. Print both registers
117 in the pair for "mh".
119 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
121 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
122 * micromips-opc.c (micromips_opcodes): Likewise.
123 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
124 and "+T" handling. Check for a "0" suffix when deciding whether to
125 use coprocessor 0 names. In that case, also check for ",H" selectors.
127 2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
129 * s390-opc.c (J12_12, J24_24): New macros.
130 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
131 (MASK_MII_UPI): Rename to MASK_MII_UPP.
132 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
134 2013-07-04 Alan Modra <amodra@gmail.com>
136 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
138 2013-06-26 Nick Clifton <nickc@redhat.com>
140 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
141 field when checking for type 2 nop.
142 * rx-decode.c: Regenerate.
144 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
146 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
149 2013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
151 * mips-dis.c (is_mips16_plt_tail): New function.
152 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
154 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
156 2013-06-21 DJ Delorie <dj@redhat.com>
158 * msp430-decode.opc: New.
159 * msp430-decode.c: New/generated.
160 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
161 (MAINTAINER_CLEANFILES): Likewise.
162 Add rule to build msp430-decode.c frommsp430decode.opc
163 using the opc2c program.
164 * Makefile.in: Regenerate.
165 * configure.in: Add msp430-decode.lo to msp430 architecture files.
166 * configure: Regenerate.
168 2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
170 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
171 (SYMTAB_AVAILABLE): Removed.
172 (#include "elf/aarch64.h): Ditto.
174 2013-06-17 Catherine Moore <clm@codesourcery.com>
175 Maciej W. Rozycki <macro@codesourcery.com>
176 Chao-Ying Fu <fu@mips.com>
178 * micromips-opc.c (EVA): Define.
180 (micromips_opcodes): Add EVA opcodes.
181 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
182 (print_insn_args): Handle EVA offsets.
183 (print_insn_micromips): Likewise.
184 * mips-opc.c (EVA): Define.
186 (mips_builtin_opcodes): Add EVA opcodes.
188 2013-06-17 Alan Modra <amodra@gmail.com>
190 * Makefile.am (mips-opc.lo): Add rules to create automatic
191 dependency files. Pass archdefs.
192 (micromips-opc.lo, mips16-opc.lo): Likewise.
193 * Makefile.in: Regenerate.
195 2013-06-14 DJ Delorie <dj@redhat.com>
197 * rx-decode.opc (rx_decode_opcode): Bit operations on
198 registers are 32-bit operations, not 8-bit operations.
199 * rx-decode.c: Regenerate.
201 2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
203 * micromips-opc.c (IVIRT): New define.
204 (IVIRT64): New define.
205 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
206 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
208 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
209 dmtgc0 to print cp0 names.
211 2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
213 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
216 2013-06-08 Catherine Moore <clm@codesourcery.com>
217 Richard Sandiford <rdsandiford@googlemail.com>
219 * micromips-opc.c (D32, D33, MC): Update definitions.
220 (micromips_opcodes): Initialize ase field.
221 * mips-dis.c (mips_arch_choice): Add ase field.
222 (mips_arch_choices): Initialize ase field.
223 (set_default_mips_dis_options): Declare and setup mips_ase.
224 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
225 MT32, MC): Update definitions.
226 (mips_builtin_opcodes): Initialize ase field.
228 2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
230 * s390-opc.txt (flogr): Require a register pair destination.
232 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
234 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
237 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
239 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
241 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
243 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
244 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
245 XLS_MASK, PPCVSX2): New defines.
246 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
247 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
248 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
249 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
250 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
251 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
252 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
253 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
254 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
255 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
256 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
257 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
258 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
259 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
260 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
261 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
262 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
263 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
264 <lxvx, stxvx>: New extended mnemonics.
266 2013-05-17 Alan Modra <amodra@gmail.com>
268 * ia64-raw.tbl: Replace non-ASCII char.
269 * ia64-waw.tbl: Likewise.
270 * ia64-asmtab.c: Regenerate.
272 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
274 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
275 * i386-init.h: Regenerated.
277 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
279 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
280 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
281 check from [0, 255] to [-128, 255].
283 2013-05-09 Andrew Pinski <apinski@cavium.com>
285 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
286 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
287 (parse_mips_dis_option): Handle the virt option.
288 (print_insn_args): Handle "+J".
289 (print_mips_disassembler_options): Print out message about virt64.
290 * mips-opc.c (IVIRT): New define.
291 (IVIRT64): New define.
292 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
293 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
294 Move rfe to the bottom as it conflicts with tlbgp.
296 2013-05-09 Alan Modra <amodra@gmail.com>
298 * ppc-opc.c (extract_vlesi): Properly sign extend.
299 (extract_vlensi): Likewise. Comment reason for setting invalid.
301 2013-05-02 Nick Clifton <nickc@redhat.com>
303 * msp430-dis.c: Add support for MSP430X instructions.
305 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
307 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
310 2013-04-17 Wei-chen Wang <cole945@gmail.com>
313 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
315 (hash_insns_list): Likewise.
317 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
319 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
322 2013-04-08 Jan Beulich <jbeulich@suse.com>
324 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
325 * i386-tbl.h: Re-generate.
327 2013-04-06 David S. Miller <davem@davemloft.net>
329 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
330 of an opcode, prefer the one with F_PREFERRED set.
331 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
332 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
333 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
334 mark existing mnenomics as aliases. Add "cc" suffix to edge
335 instructions generating condition codes, mark existing mnenomics
336 as aliases. Add "fp" prefix to VIS compare instructions, mark
337 existing mnenomics as aliases.
339 2013-04-03 Nick Clifton <nickc@redhat.com>
341 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
342 destination address by subtracting the operand from the current
344 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
345 a positive value in the insn.
346 (extract_u16_loop): Do not negate the returned value.
347 (D16_LOOP): Add V850_INVERSE_PCREL flag.
349 (ceilf.sw): Remove duplicate entry.
350 (cvtf.hs): New entry.
356 (maddf.s): Restrict to E3V5 architectures.
358 (nmaddf.s): Likewise.
359 (nmsubf.s): Likewise.
361 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
363 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
365 (print_insn): Pass sizeflag to get_sib.
367 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
370 * tic6x-dis.c: Add support for displaying 16-bit insns.
372 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
375 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
376 individual msb and lsb halves in src1 & src2 fields. Discard the
377 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
378 follow what Ti SDK does in that case as any value in the src1
379 field yields the same output with SDK disassembler.
381 2013-03-12 Michael Eager <eager@eagercon.com>
383 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
385 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
387 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
389 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
391 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
393 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
395 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
397 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
399 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
400 (thumb32_opcodes): Likewise.
401 (print_insn_thumb32): Handle 'S' control char.
403 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
405 * lm32-desc.c: Regenerate.
407 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
409 * i386-reg.tbl (riz): Add RegRex64.
410 * i386-tbl.h: Regenerated.
412 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
414 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
415 (aarch64_feature_crc): New static.
417 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
418 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
419 * aarch64-asm-2.c: Re-generate.
420 * aarch64-dis-2.c: Ditto.
421 * aarch64-opc-2.c: Ditto.
423 2013-02-27 Alan Modra <amodra@gmail.com>
425 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
426 * rl78-decode.c: Regenerate.
428 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
430 * rl78-decode.opc: Fix encoding of DIVWU insn.
431 * rl78-decode.c: Regenerate.
433 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
436 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
438 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
439 (cpu_flags): Add CpuSMAP.
441 * i386-opc.h (CpuSMAP): New.
442 (i386_cpu_flags): Add cpusmap.
444 * i386-opc.tbl: Add clac and stac.
446 * i386-init.h: Regenerated.
447 * i386-tbl.h: Likewise.
449 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
451 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
452 which also makes the disassembler output be in little
453 endian like it should be.
455 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
457 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
459 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
461 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
463 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
464 section disassembled.
466 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
468 * arm-dis.c: Update strht pattern.
470 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
472 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
473 single-float. Disable ll, lld, sc and scd for EE. Disable the
474 trunc.w.s macro for EE.
476 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
477 Andrew Jenner <andrew@codesourcery.com>
479 Based on patches from Altera Corporation.
481 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
483 * Makefile.in: Regenerated.
484 * configure.in: Add case for bfd_nios2_arch.
485 * configure: Regenerated.
486 * disassemble.c (ARCH_nios2): Define.
487 (disassembler): Add case for bfd_arch_nios2.
488 * nios2-dis.c: New file.
489 * nios2-opc.c: New file.
491 2013-02-04 Alan Modra <amodra@gmail.com>
493 * po/POTFILES.in: Regenerate.
494 * rl78-decode.c: Regenerate.
495 * rx-decode.c: Regenerate.
497 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
499 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
500 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
501 * aarch64-asm.c (convert_xtl_to_shll): New function.
502 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
503 calling convert_xtl_to_shll.
504 * aarch64-dis.c (convert_shll_to_xtl): New function.
505 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
506 calling convert_shll_to_xtl.
507 * aarch64-gen.c: Update copyright year.
508 * aarch64-asm-2.c: Re-generate.
509 * aarch64-dis-2.c: Re-generate.
510 * aarch64-opc-2.c: Re-generate.
512 2013-01-24 Nick Clifton <nickc@redhat.com>
514 * v850-dis.c: Add support for e3v5 architecture.
515 * v850-opc.c: Likewise.
517 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
519 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
520 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
521 * aarch64-opc.c (operand_general_constraint_met_p): For
522 AARCH64_MOD_LSL, move the range check on the shift amount before the
523 alignment check; change to call set_sft_amount_out_of_range_error
524 instead of set_imm_out_of_range_error.
525 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
526 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
527 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
530 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
532 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
534 * i386-init.h: Regenerated.
535 * i386-tbl.h: Likewise.
537 2013-01-15 Nick Clifton <nickc@redhat.com>
539 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
541 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
543 2013-01-14 Will Newton <will.newton@imgtec.com>
545 * metag-dis.c (REG_WIDTH): Increase to 64.
547 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
549 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
550 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
551 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
553 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
554 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
555 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
556 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
558 2013-01-10 Will Newton <will.newton@imgtec.com>
560 * Makefile.am: Add Meta.
561 * configure.in: Add Meta.
562 * disassemble.c: Add Meta support.
563 * metag-dis.c: New file.
564 * Makefile.in: Regenerate.
565 * configure: Regenerate.
567 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
569 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
570 (match_opcode): Rename to cr16_match_opcode.
572 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
574 * mips-dis.c: Add names for CP0 registers of r5900.
575 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
576 instructions sq and lq.
577 Add support for MIPS r5900 CPU.
578 Add support for 128 bit MMI (Multimedia Instructions).
579 Add support for EE instructions (Emotion Engine).
580 Disable unsupported floating point instructions (64 bit and
581 undefined compare operations).
582 Enable instructions of MIPS ISA IV which are supported by r5900.
583 Disable 64 bit co processor instructions.
584 Disable 64 bit multiplication and division instructions.
585 Disable instructions for co-processor 2 and 3, because these are
586 not supported (preparation for later VU0 support (Vector Unit)).
587 Disable cvt.w.s because this behaves like trunc.w.s and the
588 correct execution can't be ensured on r5900.
589 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
590 will confuse less developers and compilers.
592 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
594 * aarch64-opc.c (aarch64_print_operand): Change to print
595 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
597 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
598 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
601 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
603 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
604 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
606 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
608 * i386-gen.c (process_copyright): Update copyright year to 2013.
610 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
612 * cr16-dis.c (match_opcode,make_instruction): Remove static
614 (dwordU,wordU): Moved typedefs to opcode/cr16.h
615 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
617 For older changes see ChangeLog-2012
619 Copyright (C) 2013 Free Software Foundation, Inc.
621 Copying and distribution of this file, with or without modification,
622 are permitted in any medium without royalty provided the copyright
623 notice and this notice are preserved.
629 version-control: never