1 2018-07-31 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.h (ZEROING_MASKING) Rename to ...
4 (DYNAMIC_MASKING): ... this. Adjust comment.
5 * i386-opc.tbl (MaskingMorZ): Define.
6 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
7 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
8 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
9 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
10 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
11 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
12 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
13 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
14 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
16 2018-07-31 Jan Beulich <jbeulich@suse.com>
18 * i386-opc.tbl: Use element rather than vector size for AVX512*
20 * i386-tbl.h: Re-generate.
22 2018-07-31 Jan Beulich <jbeulich@suse.com>
24 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
25 (cpu_flags): Drop CpuVREX.
26 * i386-opc.h (CpuVREX): Delete.
27 (union i386_cpu_flags): Remove cpuvrex.
28 * i386-init.h, i386-tbl.h: Re-generate.
30 2018-07-30 Jim Wilson <jimw@sifive.com>
32 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
34 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
36 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
38 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
39 * Makefile.in: Regenerated.
40 * configure.ac: Add C-SKY.
41 * configure: Regenerated.
42 * csky-dis.c: New file.
43 * csky-opc.h: New file.
44 * disassemble.c (ARCH_csky): Define.
45 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
46 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
48 2018-07-27 Alan Modra <amodra@gmail.com>
50 * ppc-opc.c (insert_sprbat): Correct function parameter and
52 (extract_sprbat): Likewise, variable too.
54 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
55 Alan Modra <amodra@gmail.com>
57 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
58 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
59 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
60 support disjointed BAT.
61 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
62 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
63 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
65 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
66 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
68 * i386-gen.c (adjust_broadcast_modifier): New function.
69 (process_i386_opcode_modifier): Add an argument for operands.
70 Adjust the Broadcast value based on operands.
71 (output_i386_opcode): Pass operand_types to
72 process_i386_opcode_modifier.
73 (process_i386_opcodes): Pass NULL as operands to
74 process_i386_opcode_modifier.
75 * i386-opc.h (BYTE_BROADCAST): New.
76 (WORD_BROADCAST): Likewise.
77 (DWORD_BROADCAST): Likewise.
78 (QWORD_BROADCAST): Likewise.
79 (i386_opcode_modifier): Expand broadcast to 3 bits.
80 * i386-tbl.h: Regenerated.
82 2018-07-24 Alan Modra <amodra@gmail.com>
85 * or1k-desc.h: Regenerate.
87 2018-07-24 Jan Beulich <jbeulich@suse.com>
89 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
90 vcvtusi2ss, and vcvtusi2sd.
91 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
92 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
93 * i386-tbl.h: Re-generate.
95 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
97 * arc-opc.c (extract_w6): Fix extending the sign.
99 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
101 * arc-tbl.h (vewt): Allow it for ARC EM family.
103 2018-07-23 Alan Modra <amodra@gmail.com>
106 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
107 opcode variants for mtspr/mfspr encodings.
109 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
110 Maciej W. Rozycki <macro@mips.com>
112 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
113 loongson3a descriptors.
114 (parse_mips_ase_option): Handle -M loongson-mmi option.
115 (print_mips_disassembler_options): Document -M loongson-mmi.
116 * mips-opc.c (LMMI): New macro.
117 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
120 2018-07-19 Jan Beulich <jbeulich@suse.com>
122 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
123 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
124 IgnoreSize and [XYZ]MMword where applicable.
125 * i386-tbl.h: Re-generate.
127 2018-07-19 Jan Beulich <jbeulich@suse.com>
129 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
130 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
131 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
132 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
133 * i386-tbl.h: Re-generate.
135 2018-07-19 Jan Beulich <jbeulich@suse.com>
137 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
138 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
139 VPCLMULQDQ templates into their respective AVX512VL counterparts
140 where possible, using Disp8ShiftVL and CheckRegSize instead of
141 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
142 * i386-tbl.h: Re-generate.
144 2018-07-19 Jan Beulich <jbeulich@suse.com>
146 * i386-opc.tbl: Fold AVX512DQ templates into their respective
147 AVX512VL counterparts where possible, using Disp8ShiftVL and
148 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
149 IgnoreSize) as appropriate.
150 * i386-tbl.h: Re-generate.
152 2018-07-19 Jan Beulich <jbeulich@suse.com>
154 * i386-opc.tbl: Fold AVX512BW templates into their respective
155 AVX512VL counterparts where possible, using Disp8ShiftVL and
156 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
157 IgnoreSize) as appropriate.
158 * i386-tbl.h: Re-generate.
160 2018-07-19 Jan Beulich <jbeulich@suse.com>
162 * i386-opc.tbl: Fold AVX512CD templates into their respective
163 AVX512VL counterparts where possible, using Disp8ShiftVL and
164 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
165 IgnoreSize) as appropriate.
166 * i386-tbl.h: Re-generate.
168 2018-07-19 Jan Beulich <jbeulich@suse.com>
170 * i386-opc.h (DISP8_SHIFT_VL): New.
171 * i386-opc.tbl (Disp8ShiftVL): Define.
172 (various): Fold AVX512VL templates into their respective
173 AVX512F counterparts where possible, using Disp8ShiftVL and
174 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
175 IgnoreSize) as appropriate.
176 * i386-tbl.h: Re-generate.
178 2018-07-19 Jan Beulich <jbeulich@suse.com>
180 * Makefile.am: Change dependencies and rule for
181 $(srcdir)/i386-init.h.
182 * Makefile.in: Re-generate.
183 * i386-gen.c (process_i386_opcodes): New local variable
184 "marker". Drop opening of input file. Recognize marker and line
186 * i386-opc.tbl (OPCODE_I386_H): Define.
187 (i386-opc.h): Include it.
190 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
193 * i386-opc.h (Byte): Update comments.
202 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
204 * i386-tbl.h: Regenerated.
206 2018-07-12 Sudakshina Das <sudi.das@arm.com>
208 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
209 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
210 * aarch64-asm-2.c: Regenerate.
211 * aarch64-dis-2.c: Regenerate.
212 * aarch64-opc-2.c: Regenerate.
214 2018-07-12 Tamar Christina <tamar.christina@arm.com>
217 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
218 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
219 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
220 sqdmulh, sqrdmulh): Use Em16.
222 2018-07-11 Sudakshina Das <sudi.das@arm.com>
224 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
225 csdb together with them.
226 (thumb32_opcodes): Likewise.
228 2018-07-11 Jan Beulich <jbeulich@suse.com>
230 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
231 requiring 32-bit registers as operands 2 and 3. Improve
233 (mwait, mwaitx): Fold templates. Improve comments.
234 OPERAND_TYPE_INOUTPORTREG.
235 * i386-tbl.h: Re-generate.
237 2018-07-11 Jan Beulich <jbeulich@suse.com>
239 * i386-gen.c (operand_type_init): Remove
240 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
241 OPERAND_TYPE_INOUTPORTREG.
242 * i386-init.h: Re-generate.
244 2018-07-11 Jan Beulich <jbeulich@suse.com>
246 * i386-opc.tbl (wrssd, wrussd): Add Dword.
247 (wrssq, wrussq): Add Qword.
248 * i386-tbl.h: Re-generate.
250 2018-07-11 Jan Beulich <jbeulich@suse.com>
252 * i386-opc.h: Rename OTMax to OTNum.
253 (OTNumOfUints): Adjust calculation.
254 (OTUnused): Directly alias to OTNum.
256 2018-07-09 Maciej W. Rozycki <macro@mips.com>
258 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
260 (lea_reg_xys): Likewise.
261 (print_insn_loop_primitive): Rename `reg' local variable to
264 2018-07-06 Tamar Christina <tamar.christina@arm.com>
267 * aarch64-tbl.h (ldarh): Fix disassembly mask.
269 2018-07-06 Tamar Christina <tamar.christina@arm.com>
272 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
273 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
275 2018-07-02 Maciej W. Rozycki <macro@mips.com>
278 * mips-dis.c (mips_option_arg_t): New enumeration.
279 (mips_options): New variable.
280 (disassembler_options_mips): New function.
281 (print_mips_disassembler_options): Reimplement in terms of
282 `disassembler_options_mips'.
283 * arm-dis.c (disassembler_options_arm): Adapt to using the
284 `disasm_options_and_args_t' structure.
285 * ppc-dis.c (disassembler_options_powerpc): Likewise.
286 * s390-dis.c (disassembler_options_s390): Likewise.
288 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
290 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
292 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
293 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
294 * testsuite/ld-arm/tls-longplt.d: Likewise.
296 2018-06-29 Tamar Christina <tamar.christina@arm.com>
299 * aarch64-asm-2.c: Regenerate.
300 * aarch64-dis-2.c: Likewise.
301 * aarch64-opc-2.c: Likewise.
302 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
303 * aarch64-opc.c (operand_general_constraint_met_p,
304 aarch64_print_operand): Likewise.
305 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
306 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
308 (AARCH64_OPERANDS): Add Em2.
310 2018-06-26 Nick Clifton <nickc@redhat.com>
312 * po/uk.po: Updated Ukranian translation.
313 * po/de.po: Updated German translation.
314 * po/pt_BR.po: Updated Brazilian Portuguese translation.
316 2018-06-26 Nick Clifton <nickc@redhat.com>
318 * nfp-dis.c: Fix spelling mistake.
320 2018-06-24 Nick Clifton <nickc@redhat.com>
322 * configure: Regenerate.
323 * po/opcodes.pot: Regenerate.
325 2018-06-24 Nick Clifton <nickc@redhat.com>
329 2018-06-19 Tamar Christina <tamar.christina@arm.com>
331 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
332 * aarch64-asm-2.c: Regenerate.
333 * aarch64-dis-2.c: Likewise.
335 2018-06-21 Maciej W. Rozycki <macro@mips.com>
337 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
338 `-M ginv' option description.
340 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
343 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
346 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
348 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
349 * configure.ac: Remove AC_PREREQ.
350 * Makefile.in: Re-generate.
351 * aclocal.m4: Re-generate.
352 * configure: Re-generate.
354 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
356 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
357 mips64r6 descriptors.
358 (parse_mips_ase_option): Handle -Mginv option.
359 (print_mips_disassembler_options): Document -Mginv.
360 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
362 (mips_opcodes): Define ginvi and ginvt.
364 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
365 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
367 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
368 * mips-opc.c (CRC, CRC64): New macros.
369 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
370 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
373 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
376 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
377 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
379 2018-06-06 Alan Modra <amodra@gmail.com>
381 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
382 setjmp. Move init for some other vars later too.
384 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
386 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
387 (dis_private): Add new fields for property section tracking.
388 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
389 (xtensa_instruction_fits): New functions.
390 (fetch_data): Bump minimal fetch size to 4.
391 (print_insn_xtensa): Make struct dis_private static.
392 Load and prepare property table on section change.
393 Don't disassemble literals. Don't disassemble instructions that
394 cross property table boundaries.
396 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
398 * configure: Regenerated.
400 2018-06-01 Jan Beulich <jbeulich@suse.com>
402 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
403 * i386-tbl.h: Re-generate.
405 2018-06-01 Jan Beulich <jbeulich@suse.com>
407 * i386-opc.tbl (sldt, str): Add NoRex64.
408 * i386-tbl.h: Re-generate.
410 2018-06-01 Jan Beulich <jbeulich@suse.com>
412 * i386-opc.tbl (invpcid): Add Oword.
413 * i386-tbl.h: Re-generate.
415 2018-06-01 Alan Modra <amodra@gmail.com>
417 * sysdep.h (_bfd_error_handler): Don't declare.
418 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
419 * rl78-decode.opc: Likewise.
420 * msp430-decode.c: Regenerate.
421 * rl78-decode.c: Regenerate.
423 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
425 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
426 * i386-init.h : Regenerated.
428 2018-05-25 Alan Modra <amodra@gmail.com>
430 * Makefile.in: Regenerate.
431 * po/POTFILES.in: Regenerate.
433 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
435 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
436 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
437 (insert_bab, extract_bab, insert_btab, extract_btab,
438 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
439 (BAT, BBA VBA RBS XB6S): Delete macros.
440 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
441 (BB, BD, RBX, XC6): Update for new macros.
442 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
443 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
444 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
445 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
447 2018-05-18 John Darrington <john@darrington.wattle.id.au>
449 * Makefile.am: Add support for s12z architecture.
450 * configure.ac: Likewise.
451 * disassemble.c: Likewise.
452 * disassemble.h: Likewise.
453 * Makefile.in: Regenerate.
454 * configure: Regenerate.
455 * s12z-dis.c: New file.
458 2018-05-18 Alan Modra <amodra@gmail.com>
460 * nfp-dis.c: Don't #include libbfd.h.
461 (init_nfp3200_priv): Use bfd_get_section_contents.
462 (nit_nfp6000_mecsr_sec): Likewise.
464 2018-05-17 Nick Clifton <nickc@redhat.com>
466 * po/zh_CN.po: Updated simplified Chinese translation.
468 2018-05-16 Tamar Christina <tamar.christina@arm.com>
471 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
472 * aarch64-dis-2.c: Regenerate.
474 2018-05-15 Tamar Christina <tamar.christina@arm.com>
477 * aarch64-asm.c (opintl.h): Include.
478 (aarch64_ins_sysreg): Enforce read/write constraints.
479 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
480 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
481 (F_REG_READ, F_REG_WRITE): New.
482 * aarch64-opc.c (aarch64_print_operand): Generate notes for
484 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
485 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
486 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
487 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
488 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
489 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
490 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
491 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
492 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
493 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
494 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
495 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
496 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
497 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
498 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
499 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
500 msr (F_SYS_WRITE), mrs (F_SYS_READ).
502 2018-05-15 Tamar Christina <tamar.christina@arm.com>
505 * aarch64-dis.c (no_notes: New.
506 (parse_aarch64_dis_option): Support notes.
507 (aarch64_decode_insn, print_operands): Likewise.
508 (print_aarch64_disassembler_options): Document notes.
509 * aarch64-opc.c (aarch64_print_operand): Support notes.
511 2018-05-15 Tamar Christina <tamar.christina@arm.com>
514 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
515 and take error struct.
516 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
517 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
518 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
519 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
520 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
521 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
522 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
523 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
524 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
525 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
526 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
527 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
528 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
529 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
530 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
531 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
532 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
533 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
534 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
535 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
536 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
537 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
538 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
539 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
540 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
541 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
542 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
543 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
544 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
545 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
546 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
547 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
548 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
549 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
550 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
551 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
552 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
553 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
554 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
555 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
556 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
557 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
558 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
559 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
560 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
561 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
562 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
563 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
564 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
565 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
566 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
567 (determine_disassembling_preference, aarch64_decode_insn,
568 print_insn_aarch64_word, print_insn_data): Take errors struct.
569 (print_insn_aarch64): Use errors.
570 * aarch64-asm-2.c: Regenerate.
571 * aarch64-dis-2.c: Regenerate.
572 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
573 boolean in aarch64_insert_operan.
574 (print_operand_extractor): Likewise.
575 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
577 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
579 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
581 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
583 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
585 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
587 * cr16-opc.c (cr16_instruction): Comment typo fix.
588 * hppa-dis.c (print_insn_hppa): Likewise.
590 2018-05-08 Jim Wilson <jimw@sifive.com>
592 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
593 (match_c_slli64, match_srxi_as_c_srxi): New.
594 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
595 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
596 <c.slli, c.srli, c.srai>: Use match_s_slli.
597 <c.slli64, c.srli64, c.srai64>: New.
599 2018-05-08 Alan Modra <amodra@gmail.com>
601 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
602 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
603 partition opcode space for index lookup.
605 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
607 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
608 <insn_length>: ...with this. Update usage.
609 Remove duplicate call to *info->memory_error_func.
611 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
612 H.J. Lu <hongjiu.lu@intel.com>
614 * i386-dis.c (Gva): New.
615 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
616 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
617 (prefix_table): New instructions (see prefix above).
618 (mod_table): New instructions (see prefix above).
619 (OP_G): Handle va_mode.
620 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
622 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
623 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
624 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
625 * i386-opc.tbl: Add movidir{i,64b}.
626 * i386-init.h: Regenerated.
627 * i386-tbl.h: Likewise.
629 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
631 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
633 * i386-opc.h (AddrPrefixOp0): Renamed to ...
634 (AddrPrefixOpReg): This.
635 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
636 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
638 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
640 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
641 (vle_num_opcodes): Likewise.
642 (spe2_num_opcodes): Likewise.
643 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
645 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
646 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
649 2018-05-01 Tamar Christina <tamar.christina@arm.com>
651 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
653 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
655 Makefile.am: Added nfp-dis.c.
656 configure.ac: Added bfd_nfp_arch.
657 disassemble.h: Added print_insn_nfp prototype.
658 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
659 nfp-dis.c: New, for NFP support.
660 po/POTFILES.in: Added nfp-dis.c to the list.
661 Makefile.in: Regenerate.
662 configure: Regenerate.
664 2018-04-26 Jan Beulich <jbeulich@suse.com>
666 * i386-opc.tbl: Fold various non-memory operand AVX512VL
667 templates into their base ones.
668 * i386-tlb.h: Re-generate.
670 2018-04-26 Jan Beulich <jbeulich@suse.com>
672 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
673 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
674 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
675 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
676 * i386-init.h: Re-generate.
678 2018-04-26 Jan Beulich <jbeulich@suse.com>
680 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
681 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
682 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
683 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
685 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
687 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
689 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
690 cpuregzmm, and cpuregmask.
691 * i386-init.h: Re-generate.
692 * i386-tbl.h: Re-generate.
694 2018-04-26 Jan Beulich <jbeulich@suse.com>
696 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
697 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
698 * i386-init.h: Re-generate.
700 2018-04-26 Jan Beulich <jbeulich@suse.com>
702 * i386-gen.c (VexImmExt): Delete.
703 * i386-opc.h (VexImmExt, veximmext): Delete.
704 * i386-opc.tbl: Drop all VexImmExt uses.
705 * i386-tlb.h: Re-generate.
707 2018-04-25 Jan Beulich <jbeulich@suse.com>
709 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
711 * i386-tlb.h: Re-generate.
713 2018-04-25 Tamar Christina <tamar.christina@arm.com>
715 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
717 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
719 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
721 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
722 (cpu_flags): Add CpuCLDEMOTE.
723 * i386-init.h: Regenerate.
724 * i386-opc.h (enum): Add CpuCLDEMOTE,
725 (i386_cpu_flags): Add cpucldemote.
726 * i386-opc.tbl: Add cldemote.
727 * i386-tbl.h: Regenerate.
729 2018-04-16 Alan Modra <amodra@gmail.com>
731 * Makefile.am: Remove sh5 and sh64 support.
732 * configure.ac: Likewise.
733 * disassemble.c: Likewise.
734 * disassemble.h: Likewise.
735 * sh-dis.c: Likewise.
736 * sh64-dis.c: Delete.
737 * sh64-opc.c: Delete.
738 * sh64-opc.h: Delete.
739 * Makefile.in: Regenerate.
740 * configure: Regenerate.
741 * po/POTFILES.in: Regenerate.
743 2018-04-16 Alan Modra <amodra@gmail.com>
745 * Makefile.am: Remove w65 support.
746 * configure.ac: Likewise.
747 * disassemble.c: Likewise.
748 * disassemble.h: Likewise.
751 * Makefile.in: Regenerate.
752 * configure: Regenerate.
753 * po/POTFILES.in: Regenerate.
755 2018-04-16 Alan Modra <amodra@gmail.com>
757 * configure.ac: Remove we32k support.
758 * configure: Regenerate.
760 2018-04-16 Alan Modra <amodra@gmail.com>
762 * Makefile.am: Remove m88k support.
763 * configure.ac: Likewise.
764 * disassemble.c: Likewise.
765 * disassemble.h: Likewise.
766 * m88k-dis.c: Delete.
767 * Makefile.in: Regenerate.
768 * configure: Regenerate.
769 * po/POTFILES.in: Regenerate.
771 2018-04-16 Alan Modra <amodra@gmail.com>
773 * Makefile.am: Remove i370 support.
774 * configure.ac: Likewise.
775 * disassemble.c: Likewise.
776 * disassemble.h: Likewise.
777 * i370-dis.c: Delete.
778 * i370-opc.c: Delete.
779 * Makefile.in: Regenerate.
780 * configure: Regenerate.
781 * po/POTFILES.in: Regenerate.
783 2018-04-16 Alan Modra <amodra@gmail.com>
785 * Makefile.am: Remove h8500 support.
786 * configure.ac: Likewise.
787 * disassemble.c: Likewise.
788 * disassemble.h: Likewise.
789 * h8500-dis.c: Delete.
790 * h8500-opc.h: Delete.
791 * Makefile.in: Regenerate.
792 * configure: Regenerate.
793 * po/POTFILES.in: Regenerate.
795 2018-04-16 Alan Modra <amodra@gmail.com>
797 * configure.ac: Remove tahoe support.
798 * configure: Regenerate.
800 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
802 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
804 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
806 * i386-tbl.h: Regenerated.
808 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
810 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
811 PREFIX_MOD_1_0FAE_REG_6.
813 (OP_E_register): Use va_mode.
814 * i386-dis-evex.h (prefix_table):
815 New instructions (see prefixes above).
816 * i386-gen.c (cpu_flag_init): Add WAITPKG.
817 (cpu_flags): Likewise.
818 * i386-opc.h (enum): Likewise.
819 (i386_cpu_flags): Likewise.
820 * i386-opc.tbl: Add umonitor, umwait, tpause.
821 * i386-init.h: Regenerate.
822 * i386-tbl.h: Likewise.
824 2018-04-11 Alan Modra <amodra@gmail.com>
826 * opcodes/i860-dis.c: Delete.
827 * opcodes/i960-dis.c: Delete.
828 * Makefile.am: Remove i860 and i960 support.
829 * configure.ac: Likewise.
830 * disassemble.c: Likewise.
831 * disassemble.h: Likewise.
832 * Makefile.in: Regenerate.
833 * configure: Regenerate.
834 * po/POTFILES.in: Regenerate.
836 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
839 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
841 (print_insn): Clear vex instead of vex.evex.
843 2018-04-04 Nick Clifton <nickc@redhat.com>
845 * po/es.po: Updated Spanish translation.
847 2018-03-28 Jan Beulich <jbeulich@suse.com>
849 * i386-gen.c (opcode_modifiers): Delete VecESize.
850 * i386-opc.h (VecESize): Delete.
851 (struct i386_opcode_modifier): Delete vecesize.
852 * i386-opc.tbl: Drop VecESize.
853 * i386-tlb.h: Re-generate.
855 2018-03-28 Jan Beulich <jbeulich@suse.com>
857 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
858 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
859 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
860 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
861 * i386-tlb.h: Re-generate.
863 2018-03-28 Jan Beulich <jbeulich@suse.com>
865 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
867 * i386-tlb.h: Re-generate.
869 2018-03-28 Jan Beulich <jbeulich@suse.com>
871 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
872 (vex_len_table): Drop Y for vcvt*2si.
873 (putop): Replace plain 'Y' handling by abort().
875 2018-03-28 Nick Clifton <nickc@redhat.com>
878 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
879 instructions with only a base address register.
880 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
881 handle AARHC64_OPND_SVE_ADDR_R.
882 (aarch64_print_operand): Likewise.
883 * aarch64-asm-2.c: Regenerate.
884 * aarch64_dis-2.c: Regenerate.
885 * aarch64-opc-2.c: Regenerate.
887 2018-03-22 Jan Beulich <jbeulich@suse.com>
889 * i386-opc.tbl: Drop VecESize from register only insn forms and
890 memory forms not allowing broadcast.
891 * i386-tlb.h: Re-generate.
893 2018-03-22 Jan Beulich <jbeulich@suse.com>
895 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
896 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
897 sha256*): Drop Disp<N>.
899 2018-03-22 Jan Beulich <jbeulich@suse.com>
901 * i386-dis.c (EbndS, bnd_swap_mode): New.
902 (prefix_table): Use EbndS.
903 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
904 * i386-opc.tbl (bndmov): Move misplaced Load.
905 * i386-tlb.h: Re-generate.
907 2018-03-22 Jan Beulich <jbeulich@suse.com>
909 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
910 templates allowing memory operands and folded ones for register
912 * i386-tlb.h: Re-generate.
914 2018-03-22 Jan Beulich <jbeulich@suse.com>
916 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
917 256-bit templates. Drop redundant leftover Disp<N>.
918 * i386-tlb.h: Re-generate.
920 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
922 * riscv-opc.c (riscv_insn_types): New.
924 2018-03-13 Nick Clifton <nickc@redhat.com>
926 * po/pt_BR.po: Updated Brazilian Portuguese translation.
928 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
930 * i386-opc.tbl: Add Optimize to clr.
931 * i386-tbl.h: Regenerated.
933 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
935 * i386-gen.c (opcode_modifiers): Remove OldGcc.
936 * i386-opc.h (OldGcc): Removed.
937 (i386_opcode_modifier): Remove oldgcc.
938 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
939 instructions for old (<= 2.8.1) versions of gcc.
940 * i386-tbl.h: Regenerated.
942 2018-03-08 Jan Beulich <jbeulich@suse.com>
944 * i386-opc.h (EVEXDYN): New.
945 * i386-opc.tbl: Fold various AVX512VL templates.
946 * i386-tlb.h: Re-generate.
948 2018-03-08 Jan Beulich <jbeulich@suse.com>
950 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
951 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
952 vpexpandd, vpexpandq): Fold AFX512VF templates.
953 * i386-tlb.h: Re-generate.
955 2018-03-08 Jan Beulich <jbeulich@suse.com>
957 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
958 Fold 128- and 256-bit VEX-encoded templates.
959 * i386-tlb.h: Re-generate.
961 2018-03-08 Jan Beulich <jbeulich@suse.com>
963 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
964 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
965 vpexpandd, vpexpandq): Fold AVX512F templates.
966 * i386-tlb.h: Re-generate.
968 2018-03-08 Jan Beulich <jbeulich@suse.com>
970 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
971 64-bit templates. Drop Disp<N>.
972 * i386-tlb.h: Re-generate.
974 2018-03-08 Jan Beulich <jbeulich@suse.com>
976 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
977 and 256-bit templates.
978 * i386-tlb.h: Re-generate.
980 2018-03-08 Jan Beulich <jbeulich@suse.com>
982 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
983 * i386-tlb.h: Re-generate.
985 2018-03-08 Jan Beulich <jbeulich@suse.com>
987 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
989 * i386-tlb.h: Re-generate.
991 2018-03-08 Jan Beulich <jbeulich@suse.com>
993 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
994 * i386-tlb.h: Re-generate.
996 2018-03-08 Jan Beulich <jbeulich@suse.com>
998 * i386-gen.c (opcode_modifiers): Delete FloatD.
999 * i386-opc.h (FloatD): Delete.
1000 (struct i386_opcode_modifier): Delete floatd.
1001 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1003 * i386-tlb.h: Re-generate.
1005 2018-03-08 Jan Beulich <jbeulich@suse.com>
1007 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1009 2018-03-08 Jan Beulich <jbeulich@suse.com>
1011 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1012 * i386-tlb.h: Re-generate.
1014 2018-03-08 Jan Beulich <jbeulich@suse.com>
1016 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1018 * i386-tlb.h: Re-generate.
1020 2018-03-07 Alan Modra <amodra@gmail.com>
1022 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1024 * disassemble.h (print_insn_rs6000): Delete.
1025 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1026 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1027 (print_insn_rs6000): Delete.
1029 2018-03-03 Alan Modra <amodra@gmail.com>
1031 * sysdep.h (opcodes_error_handler): Define.
1032 (_bfd_error_handler): Declare.
1033 * Makefile.am: Remove stray #.
1034 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1036 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1037 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1038 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1039 opcodes_error_handler to print errors. Standardize error messages.
1040 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1041 and include opintl.h.
1042 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1043 * i386-gen.c: Standardize error messages.
1044 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1045 * Makefile.in: Regenerate.
1046 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1047 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1048 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1049 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1050 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1051 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1052 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1053 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1054 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1055 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1056 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1057 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1058 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1060 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1062 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1063 vpsub[bwdq] instructions.
1064 * i386-tbl.h: Regenerated.
1066 2018-03-01 Alan Modra <amodra@gmail.com>
1068 * configure.ac (ALL_LINGUAS): Sort.
1069 * configure: Regenerate.
1071 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1073 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1074 macro by assignements.
1076 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1079 * i386-gen.c (opcode_modifiers): Add Optimize.
1080 * i386-opc.h (Optimize): New enum.
1081 (i386_opcode_modifier): Add optimize.
1082 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1083 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1084 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1085 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1086 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1088 * i386-tbl.h: Regenerated.
1090 2018-02-26 Alan Modra <amodra@gmail.com>
1092 * crx-dis.c (getregliststring): Allocate a large enough buffer
1093 to silence false positive gcc8 warning.
1095 2018-02-22 Shea Levy <shea@shealevy.com>
1097 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1099 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1101 * i386-opc.tbl: Add {rex},
1102 * i386-tbl.h: Regenerated.
1104 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1106 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1107 (mips16_opcodes): Replace `M' with `m' for "restore".
1109 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1111 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1113 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1115 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1116 variable to `function_index'.
1118 2018-02-13 Nick Clifton <nickc@redhat.com>
1121 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1122 about truncation of printing.
1124 2018-02-12 Henry Wong <henry@stuffedcow.net>
1126 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1128 2018-02-05 Nick Clifton <nickc@redhat.com>
1130 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1132 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1134 * i386-dis.c (enum): Add pconfig.
1135 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1136 (cpu_flags): Add CpuPCONFIG.
1137 * i386-opc.h (enum): Add CpuPCONFIG.
1138 (i386_cpu_flags): Add cpupconfig.
1139 * i386-opc.tbl: Add PCONFIG instruction.
1140 * i386-init.h: Regenerate.
1141 * i386-tbl.h: Likewise.
1143 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1145 * i386-dis.c (enum): Add PREFIX_0F09.
1146 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1147 (cpu_flags): Add CpuWBNOINVD.
1148 * i386-opc.h (enum): Add CpuWBNOINVD.
1149 (i386_cpu_flags): Add cpuwbnoinvd.
1150 * i386-opc.tbl: Add WBNOINVD instruction.
1151 * i386-init.h: Regenerate.
1152 * i386-tbl.h: Likewise.
1154 2018-01-17 Jim Wilson <jimw@sifive.com>
1156 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1158 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1160 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1161 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1162 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1163 (cpu_flags): Add CpuIBT, CpuSHSTK.
1164 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1165 (i386_cpu_flags): Add cpuibt, cpushstk.
1166 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1167 * i386-init.h: Regenerate.
1168 * i386-tbl.h: Likewise.
1170 2018-01-16 Nick Clifton <nickc@redhat.com>
1172 * po/pt_BR.po: Updated Brazilian Portugese translation.
1173 * po/de.po: Updated German translation.
1175 2018-01-15 Jim Wilson <jimw@sifive.com>
1177 * riscv-opc.c (match_c_nop): New.
1178 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1180 2018-01-15 Nick Clifton <nickc@redhat.com>
1182 * po/uk.po: Updated Ukranian translation.
1184 2018-01-13 Nick Clifton <nickc@redhat.com>
1186 * po/opcodes.pot: Regenerated.
1188 2018-01-13 Nick Clifton <nickc@redhat.com>
1190 * configure: Regenerate.
1192 2018-01-13 Nick Clifton <nickc@redhat.com>
1194 2.30 branch created.
1196 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1198 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1199 * i386-tbl.h: Regenerate.
1201 2018-01-10 Jan Beulich <jbeulich@suse.com>
1203 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1204 * i386-tbl.h: Re-generate.
1206 2018-01-10 Jan Beulich <jbeulich@suse.com>
1208 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1209 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1210 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1211 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1212 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1213 Disp8MemShift of AVX512VL forms.
1214 * i386-tbl.h: Re-generate.
1216 2018-01-09 Jim Wilson <jimw@sifive.com>
1218 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1219 then the hi_addr value is zero.
1221 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1223 * arm-dis.c (arm_opcodes): Add csdb.
1224 (thumb32_opcodes): Add csdb.
1226 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1228 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1229 * aarch64-asm-2.c: Regenerate.
1230 * aarch64-dis-2.c: Regenerate.
1231 * aarch64-opc-2.c: Regenerate.
1233 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1236 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1237 Remove AVX512 vmovd with 64-bit operands.
1238 * i386-tbl.h: Regenerated.
1240 2018-01-05 Jim Wilson <jimw@sifive.com>
1242 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1245 2018-01-03 Alan Modra <amodra@gmail.com>
1247 Update year range in copyright notice of all files.
1249 2018-01-02 Jan Beulich <jbeulich@suse.com>
1251 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1252 and OPERAND_TYPE_REGZMM entries.
1254 For older changes see ChangeLog-2017
1256 Copyright (C) 2018 Free Software Foundation, Inc.
1258 Copying and distribution of this file, with or without modification,
1259 are permitted in any medium without royalty provided the copyright
1260 notice and this notice are preserved.
1266 version-control: never