1 2019-09-16 Phil Blundell <pb@pbcl.net>
3 * configure: Regenerated.
5 2019-09-09 Phil Blundell <pb@pbcl.net>
7 binutils 2.33 branch created.
9 2019-09-03 Nick Clifton <nickc@redhat.com>
12 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
13 greater than zero before indexing via (bufcnt -1).
15 2019-09-03 Nick Clifton <nickc@redhat.com>
18 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
19 (MAX_SPEC_REG_NAME_LEN): Define.
20 (struct mmix_dis_info): Use defined constants for array lengths.
21 (get_reg_name): New function.
22 (get_sprec_reg_name): New function.
23 (print_insn_mmix): Use new functions.
25 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
27 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
28 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
29 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
31 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
33 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
34 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
35 (aarch64_sys_reg_supported_p): Update checks for the above.
37 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
39 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
40 cases MVE_SQRSHRL and MVE_UQRSHLL.
41 (print_insn_mve): Add case for specifier 'k' to check
42 specific bit of the instruction.
44 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
47 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
48 encountering an unknown machine type.
49 (print_insn_arc): Handle arc_insn_length returning 0. In error
50 cases return -1 rather than calling abort.
52 2019-08-07 Jan Beulich <jbeulich@suse.com>
54 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
55 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
57 * i386-tbl.h: Re-generate.
59 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
61 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
64 2019-07-30 Mel Chen <mel.chen@sifive.com>
66 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
67 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
69 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
72 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
74 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
75 and MPY class instructions.
76 (parse_option): Add nps400 option.
77 (print_arc_disassembler_options): Add nps400 info.
79 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
81 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
84 * arc-opc.c (RAD_CHK): Add.
85 * arc-tbl.h: Regenerate.
87 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
89 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
90 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
92 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
94 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
95 instructions as UNPREDICTABLE.
97 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
99 * bpf-desc.c: Regenerated.
101 2019-07-17 Jan Beulich <jbeulich@suse.com>
103 * i386-gen.c (static_assert): Define.
105 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
106 (Opcode_Modifier_Num): ... this.
109 2019-07-16 Jan Beulich <jbeulich@suse.com>
111 * i386-gen.c (operand_types): Move RegMem ...
112 (opcode_modifiers): ... here.
113 * i386-opc.h (RegMem): Move to opcode modifer enum.
114 (union i386_operand_type): Move regmem field ...
115 (struct i386_opcode_modifier): ... here.
116 * i386-opc.tbl (RegMem): Define.
117 (mov, movq): Move RegMem on segment, control, debug, and test
119 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
120 to non-SSE2AVX flavor.
121 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
122 Move RegMem on register only flavors. Drop IgnoreSize from
123 legacy encoding flavors.
124 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
126 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
127 register only flavors.
128 (vmovd): Move RegMem and drop IgnoreSize on register only
129 flavor. Change opcode and operand order to store form.
130 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
132 2019-07-16 Jan Beulich <jbeulich@suse.com>
134 * i386-gen.c (operand_type_init, operand_types): Replace SReg
136 * i386-opc.h (SReg2, SReg3): Replace by ...
138 (union i386_operand_type): Replace sreg fields.
139 * i386-opc.tbl (mov, ): Use SReg.
140 (push, pop): Likewies. Drop i386 and x86-64 specific segment
142 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
143 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
145 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
147 * bpf-desc.c: Regenerate.
148 * bpf-opc.c: Likewise.
149 * bpf-opc.h: Likewise.
151 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
153 * bpf-desc.c: Regenerate.
154 * bpf-opc.c: Likewise.
156 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
158 * arm-dis.c (print_insn_coprocessor): Rename index to
161 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
163 * riscv-opc.c (riscv_insn_types): Add r4 type.
165 * riscv-opc.c (riscv_insn_types): Add b and j type.
167 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
168 format for sb type and correct s type.
170 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
172 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
173 SVE FMOV alias of FCPY.
175 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
177 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
178 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
180 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
182 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
183 registers in an instruction prefixed by MOVPRFX.
185 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
187 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
188 sve_size_13 icode to account for variant behaviour of
190 * aarch64-dis-2.c: Regenerate.
191 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
192 sve_size_13 icode to account for variant behaviour of
194 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
195 (OP_SVE_VVV_Q_D): Add new qualifier.
196 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
197 (struct aarch64_opcode): Split pmull{t,b} into those requiring
200 2019-07-01 Jan Beulich <jbeulich@suse.com>
202 * opcodes/i386-gen.c (operand_type_init): Remove
203 OPERAND_TYPE_VEC_IMM4 entry.
204 (operand_types): Remove Vec_Imm4.
205 * opcodes/i386-opc.h (Vec_Imm4): Delete.
206 (union i386_operand_type): Remove vec_imm4.
207 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
208 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
210 2019-07-01 Jan Beulich <jbeulich@suse.com>
212 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
213 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
214 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
215 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
216 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
217 monitorx, mwaitx): Drop ImmExt from operand-less forms.
218 * i386-tbl.h: Re-generate.
220 2019-07-01 Jan Beulich <jbeulich@suse.com>
222 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
224 * i386-tbl.h: Re-generate.
226 2019-07-01 Jan Beulich <jbeulich@suse.com>
228 * i386-opc.tbl (C): New.
229 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
230 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
231 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
232 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
233 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
234 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
235 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
236 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
237 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
238 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
239 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
240 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
241 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
242 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
243 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
244 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
245 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
246 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
247 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
248 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
249 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
250 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
251 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
252 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
253 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
254 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
256 * i386-tbl.h: Re-generate.
258 2019-07-01 Jan Beulich <jbeulich@suse.com>
260 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
262 * i386-tbl.h: Re-generate.
264 2019-07-01 Jan Beulich <jbeulich@suse.com>
266 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
267 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
268 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
269 * i386-tbl.h: Re-generate.
271 2019-07-01 Jan Beulich <jbeulich@suse.com>
273 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
274 Disp8MemShift from register only templates.
275 * i386-tbl.h: Re-generate.
277 2019-07-01 Jan Beulich <jbeulich@suse.com>
279 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
280 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
281 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
282 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
283 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
284 EVEX_W_0F11_P_3_M_1): Delete.
285 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
286 EVEX_W_0F11_P_3): New.
287 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
288 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
289 MOD_EVEX_0F11_PREFIX_3 table entries.
290 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
291 PREFIX_EVEX_0F11 table entries.
292 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
293 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
294 EVEX_W_0F11_P_3_M_{0,1} table entries.
296 2019-07-01 Jan Beulich <jbeulich@suse.com>
298 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
301 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
304 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
305 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
306 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
307 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
308 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
309 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
310 EVEX_LEN_0F38C7_R_6_P_2_W_1.
311 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
312 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
313 PREFIX_EVEX_0F38C6_REG_6 entries.
314 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
315 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
316 EVEX_W_0F38C7_R_6_P_2 entries.
317 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
318 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
319 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
320 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
321 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
322 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
323 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
325 2019-06-27 Jan Beulich <jbeulich@suse.com>
327 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
328 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
329 VEX_LEN_0F2D_P_3): Delete.
330 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
331 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
332 (prefix_table): ... here.
334 2019-06-27 Jan Beulich <jbeulich@suse.com>
336 * i386-dis.c (Iq): Delete.
338 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
340 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
341 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
342 (OP_E_memory): Also honor needindex when deciding whether an
343 address size prefix needs printing.
344 (OP_I): Remove handling of q_mode. Add handling of d_mode.
346 2019-06-26 Jim Wilson <jimw@sifive.com>
349 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
350 Set info->display_endian to info->endian_code.
352 2019-06-25 Jan Beulich <jbeulich@suse.com>
354 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
355 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
356 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
357 OPERAND_TYPE_ACC64 entries.
358 * i386-init.h: Re-generate.
360 2019-06-25 Jan Beulich <jbeulich@suse.com>
362 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
364 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
366 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
368 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
369 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
371 2019-06-25 Jan Beulich <jbeulich@suse.com>
373 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
376 2019-06-25 Jan Beulich <jbeulich@suse.com>
378 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
379 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
381 * i386-opc.tbl (movnti): Add IgnoreSize.
382 * i386-tbl.h: Re-generate.
384 2019-06-25 Jan Beulich <jbeulich@suse.com>
386 * i386-opc.tbl (and): Mark Imm8S form for optimization.
387 * i386-tbl.h: Re-generate.
389 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
391 * i386-dis-evex.h: Break into ...
392 * i386-dis-evex-len.h: New file.
393 * i386-dis-evex-mod.h: Likewise.
394 * i386-dis-evex-prefix.h: Likewise.
395 * i386-dis-evex-reg.h: Likewise.
396 * i386-dis-evex-w.h: Likewise.
397 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
398 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
401 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
404 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
405 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
407 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
408 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
409 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
410 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
411 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
412 EVEX_LEN_0F385B_P_2_W_1.
413 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
414 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
415 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
416 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
417 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
418 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
419 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
420 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
421 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
422 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
424 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
427 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
428 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
429 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
430 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
431 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
432 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
433 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
434 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
435 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
436 EVEX_LEN_0F3A43_P_2_W_1.
437 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
438 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
439 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
440 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
441 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
442 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
443 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
444 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
445 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
446 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
447 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
448 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
450 2019-06-14 Nick Clifton <nickc@redhat.com>
452 * po/fr.po; Updated French translation.
454 2019-06-13 Stafford Horne <shorne@gmail.com>
456 * or1k-asm.c: Regenerated.
457 * or1k-desc.c: Regenerated.
458 * or1k-desc.h: Regenerated.
459 * or1k-dis.c: Regenerated.
460 * or1k-ibld.c: Regenerated.
461 * or1k-opc.c: Regenerated.
462 * or1k-opc.h: Regenerated.
463 * or1k-opinst.c: Regenerated.
465 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
467 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
469 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
472 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
473 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
474 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
475 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
476 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
477 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
478 EVEX_LEN_0F3A1B_P_2_W_1.
479 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
480 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
481 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
482 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
483 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
484 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
485 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
486 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
488 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
491 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
492 EVEX.vvvv when disassembling VEX and EVEX instructions.
493 (OP_VEX): Set vex.register_specifier to 0 after readding
494 vex.register_specifier.
495 (OP_Vex_2src_1): Likewise.
496 (OP_Vex_2src_2): Likewise.
497 (OP_LWP_E): Likewise.
498 (OP_EX_Vex): Don't check vex.register_specifier.
499 (OP_XMM_Vex): Likewise.
501 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
502 Lili Cui <lili.cui@intel.com>
504 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
505 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
507 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
508 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
509 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
510 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
511 (i386_cpu_flags): Add cpuavx512_vp2intersect.
512 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
513 * i386-init.h: Regenerated.
514 * i386-tbl.h: Likewise.
516 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
517 Lili Cui <lili.cui@intel.com>
519 * doc/c-i386.texi: Document enqcmd.
520 * testsuite/gas/i386/enqcmd-intel.d: New file.
521 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
522 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
523 * testsuite/gas/i386/enqcmd.d: Likewise.
524 * testsuite/gas/i386/enqcmd.s: Likewise.
525 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
526 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
527 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
528 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
529 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
530 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
531 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
534 2019-06-04 Alan Hayward <alan.hayward@arm.com>
536 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
538 2019-06-03 Alan Modra <amodra@gmail.com>
540 * ppc-dis.c (prefix_opcd_indices): Correct size.
542 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
545 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
547 * i386-tbl.h: Regenerated.
549 2019-05-24 Alan Modra <amodra@gmail.com>
551 * po/POTFILES.in: Regenerate.
553 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
554 Alan Modra <amodra@gmail.com>
556 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
557 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
558 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
559 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
560 XTOP>): Define and add entries.
561 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
562 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
563 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
564 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
566 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
567 Alan Modra <amodra@gmail.com>
569 * ppc-dis.c (ppc_opts): Add "future" entry.
570 (PREFIX_OPCD_SEGS): Define.
571 (prefix_opcd_indices): New array.
572 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
573 (lookup_prefix): New function.
574 (print_insn_powerpc): Handle 64-bit prefix instructions.
575 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
576 (PMRR, POWERXX): Define.
577 (prefix_opcodes): New instruction table.
578 (prefix_num_opcodes): New constant.
580 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
582 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
583 * configure: Regenerated.
584 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
586 (HFILES): Add bpf-desc.h and bpf-opc.h.
587 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
588 bpf-ibld.c and bpf-opc.c.
590 * Makefile.in: Regenerated.
591 * disassemble.c (ARCH_bpf): Define.
592 (disassembler): Add case for bfd_arch_bpf.
593 (disassemble_init_for_target): Likewise.
594 (enum epbf_isa_attr): Define.
595 * disassemble.h: extern print_insn_bpf.
596 * bpf-asm.c: Generated.
597 * bpf-opc.h: Likewise.
598 * bpf-opc.c: Likewise.
599 * bpf-ibld.c: Likewise.
600 * bpf-dis.c: Likewise.
601 * bpf-desc.h: Likewise.
602 * bpf-desc.c: Likewise.
604 2019-05-21 Sudakshina Das <sudi.das@arm.com>
606 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
607 and VMSR with the new operands.
609 2019-05-21 Sudakshina Das <sudi.das@arm.com>
611 * arm-dis.c (enum mve_instructions): New enum
612 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
614 (mve_opcodes): New instructions as above.
615 (is_mve_encoding_conflict): Add cases for csinc, csinv,
617 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
619 2019-05-21 Sudakshina Das <sudi.das@arm.com>
621 * arm-dis.c (emun mve_instructions): Updated for new instructions.
622 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
623 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
624 uqshl, urshrl and urshr.
625 (is_mve_okay_in_it): Add new instructions to TRUE list.
626 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
627 (print_insn_mve): Updated to accept new %j,
628 %<bitfield>m and %<bitfield>n patterns.
630 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
632 * mips-opc.c (mips_builtin_opcodes): Change source register
635 2019-05-20 Nick Clifton <nickc@redhat.com>
637 * po/fr.po: Updated French translation.
639 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
640 Michael Collison <michael.collison@arm.com>
642 * arm-dis.c (thumb32_opcodes): Add new instructions.
643 (enum mve_instructions): Likewise.
644 (enum mve_undefined): Add new reasons.
645 (is_mve_encoding_conflict): Handle new instructions.
646 (is_mve_undefined): Likewise.
647 (is_mve_unpredictable): Likewise.
648 (print_mve_undefined): Likewise.
649 (print_mve_size): Likewise.
651 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
652 Michael Collison <michael.collison@arm.com>
654 * arm-dis.c (thumb32_opcodes): Add new instructions.
655 (enum mve_instructions): Likewise.
656 (is_mve_encoding_conflict): Handle new instructions.
657 (is_mve_undefined): Likewise.
658 (is_mve_unpredictable): Likewise.
659 (print_mve_size): Likewise.
661 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
662 Michael Collison <michael.collison@arm.com>
664 * arm-dis.c (thumb32_opcodes): Add new instructions.
665 (enum mve_instructions): Likewise.
666 (is_mve_encoding_conflict): Likewise.
667 (is_mve_unpredictable): Likewise.
668 (print_mve_size): Likewise.
670 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
671 Michael Collison <michael.collison@arm.com>
673 * arm-dis.c (thumb32_opcodes): Add new instructions.
674 (enum mve_instructions): Likewise.
675 (is_mve_encoding_conflict): Handle new instructions.
676 (is_mve_undefined): Likewise.
677 (is_mve_unpredictable): Likewise.
678 (print_mve_size): Likewise.
680 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
681 Michael Collison <michael.collison@arm.com>
683 * arm-dis.c (thumb32_opcodes): Add new instructions.
684 (enum mve_instructions): Likewise.
685 (is_mve_encoding_conflict): Handle new instructions.
686 (is_mve_undefined): Likewise.
687 (is_mve_unpredictable): Likewise.
688 (print_mve_size): Likewise.
689 (print_insn_mve): Likewise.
691 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
692 Michael Collison <michael.collison@arm.com>
694 * arm-dis.c (thumb32_opcodes): Add new instructions.
695 (print_insn_thumb32): Handle new instructions.
697 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
698 Michael Collison <michael.collison@arm.com>
700 * arm-dis.c (enum mve_instructions): Add new instructions.
701 (enum mve_undefined): Add new reasons.
702 (is_mve_encoding_conflict): Handle new instructions.
703 (is_mve_undefined): Likewise.
704 (is_mve_unpredictable): Likewise.
705 (print_mve_undefined): Likewise.
706 (print_mve_size): Likewise.
707 (print_mve_shift_n): Likewise.
708 (print_insn_mve): Likewise.
710 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
711 Michael Collison <michael.collison@arm.com>
713 * arm-dis.c (enum mve_instructions): Add new instructions.
714 (is_mve_encoding_conflict): Handle new instructions.
715 (is_mve_unpredictable): Likewise.
716 (print_mve_rotate): Likewise.
717 (print_mve_size): Likewise.
718 (print_insn_mve): Likewise.
720 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
721 Michael Collison <michael.collison@arm.com>
723 * arm-dis.c (enum mve_instructions): Add new instructions.
724 (is_mve_encoding_conflict): Handle new instructions.
725 (is_mve_unpredictable): Likewise.
726 (print_mve_size): Likewise.
727 (print_insn_mve): Likewise.
729 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
730 Michael Collison <michael.collison@arm.com>
732 * arm-dis.c (enum mve_instructions): Add new instructions.
733 (enum mve_undefined): Add new reasons.
734 (is_mve_encoding_conflict): Handle new instructions.
735 (is_mve_undefined): Likewise.
736 (is_mve_unpredictable): Likewise.
737 (print_mve_undefined): Likewise.
738 (print_mve_size): Likewise.
739 (print_insn_mve): Likewise.
741 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
742 Michael Collison <michael.collison@arm.com>
744 * arm-dis.c (enum mve_instructions): Add new instructions.
745 (is_mve_encoding_conflict): Handle new instructions.
746 (is_mve_undefined): Likewise.
747 (is_mve_unpredictable): Likewise.
748 (print_mve_size): Likewise.
749 (print_insn_mve): Likewise.
751 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
752 Michael Collison <michael.collison@arm.com>
754 * arm-dis.c (enum mve_instructions): Add new instructions.
755 (enum mve_unpredictable): Add new reasons.
756 (enum mve_undefined): Likewise.
757 (is_mve_okay_in_it): Handle new isntructions.
758 (is_mve_encoding_conflict): Likewise.
759 (is_mve_undefined): Likewise.
760 (is_mve_unpredictable): Likewise.
761 (print_mve_vmov_index): Likewise.
762 (print_simd_imm8): Likewise.
763 (print_mve_undefined): Likewise.
764 (print_mve_unpredictable): Likewise.
765 (print_mve_size): Likewise.
766 (print_insn_mve): Likewise.
768 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
769 Michael Collison <michael.collison@arm.com>
771 * arm-dis.c (enum mve_instructions): Add new instructions.
772 (enum mve_unpredictable): Add new reasons.
773 (enum mve_undefined): Likewise.
774 (is_mve_encoding_conflict): Handle new instructions.
775 (is_mve_undefined): Likewise.
776 (is_mve_unpredictable): Likewise.
777 (print_mve_undefined): Likewise.
778 (print_mve_unpredictable): Likewise.
779 (print_mve_rounding_mode): Likewise.
780 (print_mve_vcvt_size): Likewise.
781 (print_mve_size): Likewise.
782 (print_insn_mve): Likewise.
784 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
785 Michael Collison <michael.collison@arm.com>
787 * arm-dis.c (enum mve_instructions): Add new instructions.
788 (enum mve_unpredictable): Add new reasons.
789 (enum mve_undefined): Likewise.
790 (is_mve_undefined): Handle new instructions.
791 (is_mve_unpredictable): Likewise.
792 (print_mve_undefined): Likewise.
793 (print_mve_unpredictable): Likewise.
794 (print_mve_size): Likewise.
795 (print_insn_mve): Likewise.
797 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
798 Michael Collison <michael.collison@arm.com>
800 * arm-dis.c (enum mve_instructions): Add new instructions.
801 (enum mve_undefined): Add new reasons.
802 (insns): Add new instructions.
803 (is_mve_encoding_conflict):
804 (print_mve_vld_str_addr): New print function.
805 (is_mve_undefined): Handle new instructions.
806 (is_mve_unpredictable): Likewise.
807 (print_mve_undefined): Likewise.
808 (print_mve_size): Likewise.
809 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
810 (print_insn_mve): Handle new operands.
812 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
813 Michael Collison <michael.collison@arm.com>
815 * arm-dis.c (enum mve_instructions): Add new instructions.
816 (enum mve_unpredictable): Add new reasons.
817 (is_mve_encoding_conflict): Handle new instructions.
818 (is_mve_unpredictable): Likewise.
819 (mve_opcodes): Add new instructions.
820 (print_mve_unpredictable): Handle new reasons.
821 (print_mve_register_blocks): New print function.
822 (print_mve_size): Handle new instructions.
823 (print_insn_mve): Likewise.
825 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
826 Michael Collison <michael.collison@arm.com>
828 * arm-dis.c (enum mve_instructions): Add new instructions.
829 (enum mve_unpredictable): Add new reasons.
830 (enum mve_undefined): Likewise.
831 (is_mve_encoding_conflict): Handle new instructions.
832 (is_mve_undefined): Likewise.
833 (is_mve_unpredictable): Likewise.
834 (coprocessor_opcodes): Move NEON VDUP from here...
835 (neon_opcodes): ... to here.
836 (mve_opcodes): Add new instructions.
837 (print_mve_undefined): Handle new reasons.
838 (print_mve_unpredictable): Likewise.
839 (print_mve_size): Handle new instructions.
840 (print_insn_neon): Handle vdup.
841 (print_insn_mve): Handle new operands.
843 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
844 Michael Collison <michael.collison@arm.com>
846 * arm-dis.c (enum mve_instructions): Add new instructions.
847 (enum mve_unpredictable): Add new values.
848 (mve_opcodes): Add new instructions.
849 (vec_condnames): New array with vector conditions.
850 (mve_predicatenames): New array with predicate suffixes.
851 (mve_vec_sizename): New array with vector sizes.
852 (enum vpt_pred_state): New enum with vector predication states.
853 (struct vpt_block): New struct type for vpt blocks.
854 (vpt_block_state): Global struct to keep track of state.
855 (mve_extract_pred_mask): New helper function.
856 (num_instructions_vpt_block): Likewise.
857 (mark_outside_vpt_block): Likewise.
858 (mark_inside_vpt_block): Likewise.
859 (invert_next_predicate_state): Likewise.
860 (update_next_predicate_state): Likewise.
861 (update_vpt_block_state): Likewise.
862 (is_vpt_instruction): Likewise.
863 (is_mve_encoding_conflict): Add entries for new instructions.
864 (is_mve_unpredictable): Likewise.
865 (print_mve_unpredictable): Handle new cases.
866 (print_instruction_predicate): Likewise.
867 (print_mve_size): New function.
868 (print_vec_condition): New function.
869 (print_insn_mve): Handle vpt blocks and new print operands.
871 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
873 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
874 8, 14 and 15 for Armv8.1-M Mainline.
876 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
877 Michael Collison <michael.collison@arm.com>
879 * arm-dis.c (enum mve_instructions): New enum.
880 (enum mve_unpredictable): Likewise.
881 (enum mve_undefined): Likewise.
882 (struct mopcode32): New struct.
883 (is_mve_okay_in_it): New function.
884 (is_mve_architecture): Likewise.
885 (arm_decode_field): Likewise.
886 (arm_decode_field_multiple): Likewise.
887 (is_mve_encoding_conflict): Likewise.
888 (is_mve_undefined): Likewise.
889 (is_mve_unpredictable): Likewise.
890 (print_mve_undefined): Likewise.
891 (print_mve_unpredictable): Likewise.
892 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
893 (print_insn_mve): New function.
894 (print_insn_thumb32): Handle MVE architecture.
895 (select_arm_features): Force thumb for Armv8.1-m Mainline.
897 2019-05-10 Nick Clifton <nickc@redhat.com>
900 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
901 end of the table prematurely.
903 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
905 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
908 2019-05-11 Alan Modra <amodra@gmail.com>
910 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
911 when -Mraw is in effect.
913 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
915 * aarch64-dis-2.c: Regenerate.
916 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
917 (OP_SVE_BBB): New variant set.
918 (OP_SVE_DDDD): New variant set.
919 (OP_SVE_HHH): New variant set.
920 (OP_SVE_HHHU): New variant set.
921 (OP_SVE_SSS): New variant set.
922 (OP_SVE_SSSU): New variant set.
923 (OP_SVE_SHH): New variant set.
924 (OP_SVE_SBBU): New variant set.
925 (OP_SVE_DSS): New variant set.
926 (OP_SVE_DHHU): New variant set.
927 (OP_SVE_VMV_HSD_BHS): New variant set.
928 (OP_SVE_VVU_HSD_BHS): New variant set.
929 (OP_SVE_VVVU_SD_BH): New variant set.
930 (OP_SVE_VVVU_BHSD): New variant set.
931 (OP_SVE_VVV_QHD_DBS): New variant set.
932 (OP_SVE_VVV_HSD_BHS): New variant set.
933 (OP_SVE_VVV_HSD_BHS2): New variant set.
934 (OP_SVE_VVV_BHS_HSD): New variant set.
935 (OP_SVE_VV_BHS_HSD): New variant set.
936 (OP_SVE_VVV_SD): New variant set.
937 (OP_SVE_VVU_BHS_HSD): New variant set.
938 (OP_SVE_VZVV_SD): New variant set.
939 (OP_SVE_VZVV_BH): New variant set.
940 (OP_SVE_VZV_SD): New variant set.
941 (aarch64_opcode_table): Add sve2 instructions.
943 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
945 * aarch64-asm-2.c: Regenerated.
946 * aarch64-dis-2.c: Regenerated.
947 * aarch64-opc-2.c: Regenerated.
948 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
949 for SVE_SHLIMM_UNPRED_22.
950 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
951 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
954 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
956 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
957 sve_size_tsz_bhs iclass encode.
958 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
959 sve_size_tsz_bhs iclass decode.
961 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
963 * aarch64-asm-2.c: Regenerated.
964 * aarch64-dis-2.c: Regenerated.
965 * aarch64-opc-2.c: Regenerated.
966 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
967 for SVE_Zm4_11_INDEX.
968 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
969 (fields): Handle SVE_i2h field.
970 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
971 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
973 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
975 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
976 sve_shift_tsz_bhsd iclass encode.
977 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
978 sve_shift_tsz_bhsd iclass decode.
980 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
982 * aarch64-asm-2.c: Regenerated.
983 * aarch64-dis-2.c: Regenerated.
984 * aarch64-opc-2.c: Regenerated.
985 * aarch64-asm.c (aarch64_ins_sve_shrimm):
986 (aarch64_encode_variant_using_iclass): Handle
987 sve_shift_tsz_hsd iclass encode.
988 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
989 sve_shift_tsz_hsd iclass decode.
990 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
991 for SVE_SHRIMM_UNPRED_22.
992 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
993 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
996 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
998 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
999 sve_size_013 iclass encode.
1000 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1001 sve_size_013 iclass decode.
1003 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1005 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1006 sve_size_bh iclass encode.
1007 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1008 sve_size_bh iclass decode.
1010 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1012 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1013 sve_size_sd2 iclass encode.
1014 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1015 sve_size_sd2 iclass decode.
1016 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1017 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1019 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1021 * aarch64-asm-2.c: Regenerated.
1022 * aarch64-dis-2.c: Regenerated.
1023 * aarch64-opc-2.c: Regenerated.
1024 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1026 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1027 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1029 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1031 * aarch64-asm-2.c: Regenerated.
1032 * aarch64-dis-2.c: Regenerated.
1033 * aarch64-opc-2.c: Regenerated.
1034 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1035 for SVE_Zm3_11_INDEX.
1036 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1037 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1038 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1040 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1042 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1044 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1045 sve_size_hsd2 iclass encode.
1046 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1047 sve_size_hsd2 iclass decode.
1048 * aarch64-opc.c (fields): Handle SVE_size field.
1049 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1051 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1053 * aarch64-asm-2.c: Regenerated.
1054 * aarch64-dis-2.c: Regenerated.
1055 * aarch64-opc-2.c: Regenerated.
1056 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1058 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1059 (fields): Handle SVE_rot3 field.
1060 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1061 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1063 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1065 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1068 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1071 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1072 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1073 aarch64_feature_sve2bitperm): New feature sets.
1074 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1075 for feature set addresses.
1076 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1077 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1079 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1080 Faraz Shahbazker <fshahbazker@wavecomp.com>
1082 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1083 argument and set ASE_EVA_R6 appropriately.
1084 (set_default_mips_dis_options): Pass ISA to above.
1085 (parse_mips_dis_option): Likewise.
1086 * mips-opc.c (EVAR6): New macro.
1087 (mips_builtin_opcodes): Add llwpe, scwpe.
1089 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1091 * aarch64-asm-2.c: Regenerated.
1092 * aarch64-dis-2.c: Regenerated.
1093 * aarch64-opc-2.c: Regenerated.
1094 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1095 AARCH64_OPND_TME_UIMM16.
1096 (aarch64_print_operand): Likewise.
1097 * aarch64-tbl.h (QL_IMM_NIL): New.
1100 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1102 2019-04-29 John Darrington <john@darrington.wattle.id.au>
1104 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1106 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1107 Faraz Shahbazker <fshahbazker@wavecomp.com>
1109 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1111 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1113 * s12z-opc.h: Add extern "C" bracketing to help
1114 users who wish to use this interface in c++ code.
1116 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1118 * s12z-opc.c (bm_decode): Handle bit map operations with the
1121 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1123 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1124 specifier. Add entries for VLDR and VSTR of system registers.
1125 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1126 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1127 of %J and %K format specifier.
1129 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1131 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1132 Add new entries for VSCCLRM instruction.
1133 (print_insn_coprocessor): Handle new %C format control code.
1135 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1137 * arm-dis.c (enum isa): New enum.
1138 (struct sopcode32): New structure.
1139 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1140 set isa field of all current entries to ANY.
1141 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1142 Only match an entry if its isa field allows the current mode.
1144 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1146 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1148 (print_insn_thumb32): Add logic to print %n CLRM register list.
1150 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1152 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1155 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1157 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1158 (print_insn_thumb32): Edit the switch case for %Z.
1160 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1162 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1164 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1166 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1168 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1170 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1172 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1174 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1175 Arm register with r13 and r15 unpredictable.
1176 (thumb32_opcodes): New instructions for bfx and bflx.
1178 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1180 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1182 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1184 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1186 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1188 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1190 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1192 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1194 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1196 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1197 "optr". ("operator" is a reserved word in c++).
1199 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1201 * aarch64-opc.c (aarch64_print_operand): Add case for
1203 (verify_constraints): Likewise.
1204 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1205 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1206 to accept Rt|SP as first operand.
1207 (AARCH64_OPERANDS): Add new Rt_SP.
1208 * aarch64-asm-2.c: Regenerated.
1209 * aarch64-dis-2.c: Regenerated.
1210 * aarch64-opc-2.c: Regenerated.
1212 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1214 * aarch64-asm-2.c: Regenerated.
1215 * aarch64-dis-2.c: Likewise.
1216 * aarch64-opc-2.c: Likewise.
1217 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1219 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1221 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1223 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1225 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1226 * i386-init.h: Regenerated.
1228 2019-04-07 Alan Modra <amodra@gmail.com>
1230 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1231 op_separator to control printing of spaces, comma and parens
1232 rather than need_comma, need_paren and spaces vars.
1234 2019-04-07 Alan Modra <amodra@gmail.com>
1237 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1238 (print_insn_neon, print_insn_arm): Likewise.
1240 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1242 * i386-dis-evex.h (evex_table): Updated to support BF16
1244 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1245 and EVEX_W_0F3872_P_3.
1246 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1247 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1248 * i386-opc.h (enum): Add CpuAVX512_BF16.
1249 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1250 * i386-opc.tbl: Add AVX512 BF16 instructions.
1251 * i386-init.h: Regenerated.
1252 * i386-tbl.h: Likewise.
1254 2019-04-05 Alan Modra <amodra@gmail.com>
1256 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1257 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1258 to favour printing of "-" branch hint when using the "y" bit.
1259 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1261 2019-04-05 Alan Modra <amodra@gmail.com>
1263 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1264 opcode until first operand is output.
1266 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1269 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1270 (valid_bo_post_v2): Add support for 'at' branch hints.
1271 (insert_bo): Only error on branch on ctr.
1272 (get_bo_hint_mask): New function.
1273 (insert_boe): Add new 'branch_taken' formal argument. Add support
1274 for inserting 'at' branch hints.
1275 (extract_boe): Add new 'branch_taken' formal argument. Add support
1276 for extracting 'at' branch hints.
1277 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1278 (BOE): Delete operand.
1279 (BOM, BOP): New operands.
1281 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1282 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1283 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1284 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1285 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1286 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1287 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1288 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1289 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1290 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1291 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1292 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1293 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1294 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1295 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1296 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1297 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1298 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1299 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1300 bttarl+>: New extended mnemonics.
1302 2019-03-28 Alan Modra <amodra@gmail.com>
1305 * ppc-opc.c (BTF): Define.
1306 (powerpc_opcodes): Use for mtfsb*.
1307 * ppc-dis.c (print_insn_powerpc): Print fields with both
1308 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1310 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1312 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1313 (mapping_symbol_for_insn): Implement new algorithm.
1314 (print_insn): Remove duplicate code.
1316 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1318 * aarch64-dis.c (print_insn_aarch64):
1321 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1323 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1326 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1328 * aarch64-dis.c (last_stop_offset): New.
1329 (print_insn_aarch64): Use stop_offset.
1331 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1334 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1336 * i386-init.h: Regenerated.
1338 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1341 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1342 vmovdqu16, vmovdqu32 and vmovdqu64.
1343 * i386-tbl.h: Regenerated.
1345 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1347 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1348 from vstrszb, vstrszh, and vstrszf.
1350 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1352 * s390-opc.txt: Add instruction descriptions.
1354 2019-02-08 Jim Wilson <jimw@sifive.com>
1356 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1359 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1361 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1363 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1366 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1367 * aarch64-opc.c (verify_elem_sd): New.
1368 (fields): Add FLD_sz entr.
1369 * aarch64-tbl.h (_SIMD_INSN): New.
1370 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1371 fmulx scalar and vector by element isns.
1373 2019-02-07 Nick Clifton <nickc@redhat.com>
1375 * po/sv.po: Updated Swedish translation.
1377 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1379 * s390-mkopc.c (main): Accept arch13 as cpu string.
1380 * s390-opc.c: Add new instruction formats and instruction opcode
1382 * s390-opc.txt: Add new arch13 instructions.
1384 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1386 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1387 (aarch64_opcode): Change encoding for stg, stzg
1389 * aarch64-asm-2.c: Regenerated.
1390 * aarch64-dis-2.c: Regenerated.
1391 * aarch64-opc-2.c: Regenerated.
1393 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1395 * aarch64-asm-2.c: Regenerated.
1396 * aarch64-dis-2.c: Likewise.
1397 * aarch64-opc-2.c: Likewise.
1398 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1400 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1401 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1403 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1404 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1405 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1406 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1407 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1408 case for ldstgv_indexed.
1409 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1410 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1411 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1412 * aarch64-asm-2.c: Regenerated.
1413 * aarch64-dis-2.c: Regenerated.
1414 * aarch64-opc-2.c: Regenerated.
1416 2019-01-23 Nick Clifton <nickc@redhat.com>
1418 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1420 2019-01-21 Nick Clifton <nickc@redhat.com>
1422 * po/de.po: Updated German translation.
1423 * po/uk.po: Updated Ukranian translation.
1425 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1426 * mips-dis.c (mips_arch_choices): Fix typo in
1427 gs464, gs464e and gs264e descriptors.
1429 2019-01-19 Nick Clifton <nickc@redhat.com>
1431 * configure: Regenerate.
1432 * po/opcodes.pot: Regenerate.
1434 2018-06-24 Nick Clifton <nickc@redhat.com>
1436 2.32 branch created.
1438 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1440 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1442 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1445 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1447 * configure: Regenerate.
1449 2019-01-07 Alan Modra <amodra@gmail.com>
1451 * configure: Regenerate.
1452 * po/POTFILES.in: Regenerate.
1454 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1456 * s12z-opc.c: New file.
1457 * s12z-opc.h: New file.
1458 * s12z-dis.c: Removed all code not directly related to display
1459 of instructions. Used the interface provided by the new files
1461 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1462 * Makefile.in: Regenerate.
1463 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1464 * configure: Regenerate.
1466 2019-01-01 Alan Modra <amodra@gmail.com>
1468 Update year range in copyright notice of all files.
1470 For older changes see ChangeLog-2018
1472 Copyright (C) 2019 Free Software Foundation, Inc.
1474 Copying and distribution of this file, with or without modification,
1475 are permitted in any medium without royalty provided the copyright
1476 notice and this notice are preserved.
1482 version-control: never