1 2011-10-27 Peter Bergner <bergner@vnet.ibm.com>
3 * ppc-opc.c (powerpc_opcodes) <drrndq, drrndq., dtstexq, dctqpq,
4 dctqpq., dctfixq, dctfixq., dxexq, dxexq., dtstsfq, dcffixq, dcffixq.,
5 diexq, diexq.>: Use FRT, FRA, FRB and FRBp repsectively on DFP quad
8 2011-10-26 Nick Clifton <nickc@redhat.com>
11 * i386-dis.c (print_insn): Fix testing of array subscript.
13 2011-10-26 Joern Rennecke <joern.rennecke@embecosm.com>
15 * disassemble.c (ARCH_epiphany): Move into alphasorted spot.
16 * epiphany-asm.c, epiphany-opc.h: Regenerate.
18 2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
20 * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
21 (TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c,
22 epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
23 (CLEANFILES): Add stamp-epiphany.
24 (EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it.
25 (stamp-epiphany): New rule.
26 * configure.in: Handle bfd_epiphany_arch.
27 * disassemble.c (ARCH_epiphany): Define.
28 (disassembler): Handle bfd_arch_epiphany.
29 * epiphany-asm.c: New file.
30 * epiphany-desc.c: New file.
31 * epiphany-desc.h: New file.
32 * epiphany-dis.c: New file.
33 * epiphany-ibld.c: New file.
34 * epiphany-opc.c: New file.
35 * epiphany-opc.h: New file.
36 * Makefile.in: Regenerate.
37 * configure: Regenerate.
38 * po/POTFILES.in: Regenerate.
39 * po/opcodes.pot: Regenerate.
41 2011-10-24 Julian Brown <julian@codesourcery.com>
43 * m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml.
45 2011-10-21 Jan Glauber <jang@linux.vnet.ibm.com>
47 * s390-opc.txt: Add CPUMF instructions.
49 2011-10-18 Jie Zhang <jie@codesourcery.com>
50 Julian Brown <julian@codesourcery.com>
52 * arm-dis.c (print_insn_arm): Explicitly specify rotation if needed.
54 2011-10-10 Nick Clifton <nickc@redhat.com>
56 * po/es.po: Updated Spanish translation.
57 * po/fi.po: Updated Finnish translation.
59 2011-09-28 Jan Beulich <jbeulich@suse.com>
61 * ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX,
63 (insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset.
64 (powerpc_opcodes): Use RAX for second and RBXC for third operand of
65 lswx. Use NBI for third operand of lswi. Use FRTp for first operand of
66 lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and
67 mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively
68 on DFP quad instructions.
70 2011-09-27 David S. Miller <davem@davemloft.net>
72 * sparc-opc.c (sparc_opcodes): Fix random instruction to write
73 to a float instead of an integer register.
75 2011-09-26 David S. Miller <davem@davemloft.net>
77 * sparc-opc.c (sparc_opcodes): Add integer multiply-add
80 2011-09-21 David S. Miller <davem@davemloft.net>
82 * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
83 bits. Fix "fchksm16" mnemonic.
85 2011-09-08 Mark Fortescue <mark@mtfhpc.demon.co.uk>
87 The changes below bring 'mov' and 'ticc' instructions into line
88 with the V8 SPARC Architecture Manual.
89 * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
90 * sparc-opc.c (sparc_opcodes): Add alias entries for
91 'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
92 'mov regrs2,%wim' and 'mov regrs2,%tbr'.
93 * sparc-opc.c (sparc_opcodes): Move/Change entries for
94 'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
96 * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
99 * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
100 This has been reported as being accepted by the Sun assmebler.
102 2011-09-08 David S. Miller <davem@davemloft.net>
104 * sparc-opc.c (pdistn): Destination is integer not float register.
106 2011-09-07 Andreas Schwab <schwab@linux-m68k.org>
109 * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
111 2011-08-26 Nick Clifton <nickc@redhat.com>
113 * po/es.po: Updated Spanish translation.
115 2011-08-22 Nick Clifton <nickc@redhat.com>
117 * Makefile.am (CPUDIR): Redfine to point to top level cpu
119 (stamp-frv): Use CPUDIR.
120 (stamp-iq2000): Likewise.
121 (stamp-lm32): Likewise.
122 (stamp-m32c): Likewise.
123 (stamp-mt): Likewise.
124 (stamp-xc16x): Likewise.
125 * Makefile.in: Regenerate.
127 2011-08-09 Chao-ying Fu <fu@mips.com>
128 Maciej W. Rozycki <macro@codesourcery.com>
130 * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
132 (print_insn_args, print_insn_micromips): Handle MCU.
133 * micromips-opc.c (MC): New macro.
134 (micromips_opcodes): Add "aclr", "aset" and "iret".
135 * mips-opc.c (MC): New macro.
136 (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
138 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
140 * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
141 (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
142 (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
143 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
144 (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
145 (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
146 (WR_s): Update macro.
147 (micromips_opcodes): Update register use flags of: "addiu",
148 "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
149 "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
150 "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
151 "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
152 "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
153 "swm" and "xor" instructions.
155 2011-08-05 David S. Miller <davem@davemloft.net>
157 * sparc-dis.c (v9a_ast_reg_names): Add "cps".
159 (print_insn_sparc): Handle '4', '5', and '(' format codes.
160 Accept %asr numbers below 28.
161 * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
164 2011-08-02 Quentin Neill <quentin.neill@amd.com>
166 * i386-dis.c (xop_table): Remove spurious bextr insn.
168 2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
171 * i386-dis.c (print_insn): Optimize info->mach check.
173 2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
176 * i386-opc.tbl: Add Disp32S to 64bit call.
177 * i386-tbl.h: Regenerated.
179 2011-07-24 Chao-ying Fu <fu@mips.com>
180 Maciej W. Rozycki <macro@codesourcery.com>
182 * micromips-opc.c: New file.
183 * mips-dis.c (micromips_to_32_reg_b_map): New array.
184 (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
185 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
186 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
187 (micromips_to_32_reg_q_map): Likewise.
188 (micromips_imm_b_map, micromips_imm_c_map): Likewise.
189 (micromips_ase): New variable.
190 (is_micromips): New function.
191 (set_default_mips_dis_options): Handle microMIPS ASE.
192 (print_insn_micromips): New function.
193 (is_compressed_mode_p): Likewise.
194 (_print_insn_mips): Handle microMIPS instructions.
195 * Makefile.am (CFILES): Add micromips-opc.c.
196 * configure.in (bfd_mips_arch): Add micromips-opc.lo.
197 * Makefile.in: Regenerate.
198 * configure: Regenerate.
200 * mips-dis.c (micromips_to_32_reg_h_map): New variable.
201 (micromips_to_32_reg_i_map): Likewise.
202 (micromips_to_32_reg_m_map): Likewise.
203 (micromips_to_32_reg_n_map): New macro.
205 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
207 * mips-opc.c (NODS): New macro.
208 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
209 (DSP_VOLA): Likewise.
210 (mips_builtin_opcodes): Add NODS annotation to "deret" and
211 "eret". Replace INSN_SYNC with NODS throughout. Use NODS in
212 place of TRAP for "wait", "waiti" and "yield".
213 * mips16-opc.c (NODS): New macro.
214 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
215 (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
216 "restore" and "save".
218 2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
220 * configure.in: Handle bfd_k1om_arch.
221 * configure: Regenerated.
223 * disassemble.c (disassembler): Handle bfd_k1om_arch.
225 * i386-dis.c (print_insn): Handle bfd_mach_k1om and
226 bfd_mach_k1om_intel_syntax.
228 * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
229 ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
230 (cpu_flags): Add CpuK1OM.
232 * i386-opc.h (CpuK1OM): New.
233 (i386_cpu_flags): Add cpuk1om.
235 * i386-init.h: Regenerated.
236 * i386-tbl.h: Likewise.
238 2011-07-12 Nick Clifton <nickc@redhat.com>
240 * arm-dis.c (print_insn_arm): Revert previous, undocumented,
243 2011-07-01 Nick Clifton <nickc@redhat.com>
246 * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
247 insns using post-increment addressing.
249 2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
251 * i386-dis.c (vex_len_table): Update rorxS.
253 2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
255 AVX Programming Reference (June, 2011)
256 * i386-dis.c (vex_len_table): Correct rorxS.
258 * i386-opc.tbl: Correct rorx.
259 * i386-tbl.h: Regenerated.
261 2011-06-29 H.J. Lu <hongjiu.lu@intel.com>
263 * tilegx-opc.c (find_opcode): Replace "index" with "i".
264 * tilepro-opc.c (find_opcode): Likewise.
266 2011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
268 * mips16-opc.c (jalrc, jrc): Move earlier in file.
270 2011-06-21 H.J. Lu <hongjiu.lu@intel.com>
272 * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
275 2011-06-17 Andreas Schwab <schwab@redhat.com>
277 * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
278 (MOSTLYCLEANFILES): ... here.
279 * Makefile.in: Regenerate.
281 2011-06-14 Alan Modra <amodra@gmail.com>
283 * Makefile.in: Regenerate.
285 2011-06-13 Walter Lee <walt@tilera.com>
287 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
288 tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
289 * Makefile.in: Regenerate.
290 * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
291 * configure: Regenerate.
292 * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
293 * po/POTFILES.in: Regenerate.
294 * tilegx-dis.c: New file.
295 * tilegx-opc.c: New file.
296 * tilepro-dis.c: New file.
297 * tilepro-opc.c: New file.
299 2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
301 AVX Programming Reference (June, 2011)
302 * i386-dis.c (XMGatherQ): New.
303 * i386-dis.c (EXxmm_mb): New.
304 (EXxmm_mb): Likewise.
305 (EXxmm_mw): Likewise.
306 (EXxmm_md): Likewise.
307 (EXxmm_mq): Likewise.
310 (VexGatherQ): Likewise.
311 (MVexVSIBDWpX): Likewise.
312 (MVexVSIBQWpX): Likewise.
313 (xmm_mb_mode): Likewise.
314 (xmm_mw_mode): Likewise.
315 (xmm_md_mode): Likewise.
316 (xmm_mq_mode): Likewise.
317 (xmmdw_mode): Likewise.
318 (xmmqd_mode): Likewise.
319 (ymmxmm_mode): Likewise.
320 (vex_vsib_d_w_dq_mode): Likewise.
321 (vex_vsib_q_w_dq_mode): Likewise.
322 (MOD_VEX_0F385A_PREFIX_2): Likewise.
323 (MOD_VEX_0F388C_PREFIX_2): Likewise.
324 (MOD_VEX_0F388E_PREFIX_2): Likewise.
325 (PREFIX_0F3882): Likewise.
326 (PREFIX_VEX_0F3816): Likewise.
327 (PREFIX_VEX_0F3836): Likewise.
328 (PREFIX_VEX_0F3845): Likewise.
329 (PREFIX_VEX_0F3846): Likewise.
330 (PREFIX_VEX_0F3847): Likewise.
331 (PREFIX_VEX_0F3858): Likewise.
332 (PREFIX_VEX_0F3859): Likewise.
333 (PREFIX_VEX_0F385A): Likewise.
334 (PREFIX_VEX_0F3878): Likewise.
335 (PREFIX_VEX_0F3879): Likewise.
336 (PREFIX_VEX_0F388C): Likewise.
337 (PREFIX_VEX_0F388E): Likewise.
338 (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
339 (PREFIX_VEX_0F38F5): Likewise.
340 (PREFIX_VEX_0F38F6): Likewise.
341 (PREFIX_VEX_0F3A00): Likewise.
342 (PREFIX_VEX_0F3A01): Likewise.
343 (PREFIX_VEX_0F3A02): Likewise.
344 (PREFIX_VEX_0F3A38): Likewise.
345 (PREFIX_VEX_0F3A39): Likewise.
346 (PREFIX_VEX_0F3A46): Likewise.
347 (PREFIX_VEX_0F3AF0): Likewise.
348 (VEX_LEN_0F3816_P_2): Likewise.
349 (VEX_LEN_0F3819_P_2): Likewise.
350 (VEX_LEN_0F3836_P_2): Likewise.
351 (VEX_LEN_0F385A_P_2_M_0): Likewise.
352 (VEX_LEN_0F38F5_P_0): Likewise.
353 (VEX_LEN_0F38F5_P_1): Likewise.
354 (VEX_LEN_0F38F5_P_3): Likewise.
355 (VEX_LEN_0F38F6_P_3): Likewise.
356 (VEX_LEN_0F38F7_P_1): Likewise.
357 (VEX_LEN_0F38F7_P_2): Likewise.
358 (VEX_LEN_0F38F7_P_3): Likewise.
359 (VEX_LEN_0F3A00_P_2): Likewise.
360 (VEX_LEN_0F3A01_P_2): Likewise.
361 (VEX_LEN_0F3A38_P_2): Likewise.
362 (VEX_LEN_0F3A39_P_2): Likewise.
363 (VEX_LEN_0F3A46_P_2): Likewise.
364 (VEX_LEN_0F3AF0_P_3): Likewise.
365 (VEX_W_0F3816_P_2): Likewise.
366 (VEX_W_0F3818_P_2): Likewise.
367 (VEX_W_0F3819_P_2): Likewise.
368 (VEX_W_0F3836_P_2): Likewise.
369 (VEX_W_0F3846_P_2): Likewise.
370 (VEX_W_0F3858_P_2): Likewise.
371 (VEX_W_0F3859_P_2): Likewise.
372 (VEX_W_0F385A_P_2_M_0): Likewise.
373 (VEX_W_0F3878_P_2): Likewise.
374 (VEX_W_0F3879_P_2): Likewise.
375 (VEX_W_0F3A00_P_2): Likewise.
376 (VEX_W_0F3A01_P_2): Likewise.
377 (VEX_W_0F3A02_P_2): Likewise.
378 (VEX_W_0F3A38_P_2): Likewise.
379 (VEX_W_0F3A39_P_2): Likewise.
380 (VEX_W_0F3A46_P_2): Likewise.
381 (MOD_VEX_0F3818_PREFIX_2): Removed.
382 (MOD_VEX_0F3819_PREFIX_2): Likewise.
383 (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
384 (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
385 (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
386 (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
387 (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
388 (VEX_LEN_0F3A0E_P_2): Likewise.
389 (VEX_LEN_0F3A0F_P_2): Likewise.
390 (VEX_LEN_0F3A42_P_2): Likewise.
391 (VEX_LEN_0F3A4C_P_2): Likewise.
392 (VEX_W_0F3818_P_2_M_0): Likewise.
393 (VEX_W_0F3819_P_2_M_0): Likewise.
394 (prefix_table): Updated.
395 (three_byte_table): Likewise.
396 (vex_table): Likewise.
397 (vex_len_table): Likewise.
398 (vex_w_table): Likewise.
399 (mod_table): Likewise.
400 (putop): Handle "LW".
401 (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
402 xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
403 vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
405 (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
406 vex_vsib_q_w_dq_mode.
407 (OP_XMM): Handle vex_vsib_q_w_dq_mode.
410 * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
411 and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
412 CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
413 (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
414 (opcode_modifiers): Add VecSIB.
416 * i386-opc.h (CpuAVX2): New.
418 (CpuLZCNT): Likewise.
419 (CpuINVPCID): Likewise.
420 (VecSIB128): Likewise.
421 (VecSIB256): Likewise.
423 (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
424 (i386_opcode_modifier): Add vecsib.
426 * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
427 * i386-init.h: Regenerated.
428 * i386-tbl.h: Likewise.
430 2011-06-03 Quentin Neill <quentin.neill@amd.com>
432 * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
433 * i386-init.h: Regenerated.
435 2011-06-03 Nick Clifton <nickc@redhat.com>
438 * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
439 computing address offsets.
440 (print_arm_address): Likewise.
441 (print_insn_arm): Likewise.
442 (print_insn_thumb16): Likewise.
443 (print_insn_thumb32): Likewise.
445 2011-06-02 Jie Zhang <jie@codesourcery.com>
446 Nathan Sidwell <nathan@codesourcery.com>
447 Maciej Rozycki <macro@codesourcery.com>
449 * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
451 (print_arm_address): Likewise. Elide positive #0 appropriately.
452 (print_insn_arm): Likewise.
454 2011-06-02 Nick Clifton <nickc@redhat.com>
457 * arm-dis.c (print_insn_thumb32): Do not sign extend addresses
458 passed to print_address_func.
460 2011-06-02 Nick Clifton <nickc@redhat.com>
462 * arm-dis.c: Fix spelling mistakes.
463 * op/opcodes.pot: Regenerate.
465 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
467 * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
468 S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
469 * s390-opc.txt: Fix cxr instruction type.
471 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
473 * s390-opc.c: Add new instruction types marking register pair
475 * s390-opc.txt: Match instructions having register pair operands
476 to the new instruction types.
478 2011-05-19 Nick Clifton <nickc@redhat.com>
480 * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
483 2011-05-10 Quentin Neill <quentin.neill@amd.com>
485 * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
486 * i386-init.h: Regenerated.
488 2011-04-27 Nick Clifton <nickc@redhat.com>
490 * po/da.po: Updated Danish translation.
492 2011-04-26 Anton Blanchard <anton@samba.org>
494 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
496 2011-04-21 DJ Delorie <dj@redhat.com>
498 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
499 * rx-decode.c: Regenerate.
501 2011-04-20 H.J. Lu <hongjiu.lu@intel.com>
503 * i386-init.h: Regenerated.
505 2011-04-19 Quentin Neill <quentin.neill@amd.com>
507 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
510 2011-04-13 Nick Clifton <nickc@redhat.com>
512 * v850-dis.c (disassemble): Always print a closing square brace if
513 an opening square brace was printed.
515 2011-04-12 Nick Clifton <nickc@redhat.com>
518 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
520 (print_insn_thumb32): Handle %L.
522 2011-04-11 Julian Brown <julian@codesourcery.com>
524 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
525 (print_insn_thumb32): Add APSR bitmask support.
527 2011-04-07 Paul Carroll<pcarroll@codesourcery.com>
529 * arm-dis.c (print_insn): init vars moved into private_data structure.
531 2011-03-24 Mike Frysinger <vapier@gentoo.org>
533 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
535 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
537 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
538 post-increment to support LPM Z+ instruction. Add support for 'E'
539 constraint for DES instruction.
540 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
542 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
544 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
546 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
548 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
549 Use branch types instead.
550 (print_insn): Likewise.
552 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
554 * mips-opc.c (mips_builtin_opcodes): Correct register use
555 annotation of "alnv.ps".
557 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
559 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
561 2011-02-22 Mike Frysinger <vapier@gentoo.org>
563 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
565 2011-02-22 Mike Frysinger <vapier@gentoo.org>
567 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
569 2011-02-19 Mike Frysinger <vapier@gentoo.org>
571 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
572 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
573 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
574 exception, end_of_registers, msize, memory, bfd_mach.
575 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
576 LB0REG, LC1REG, LT1REG, LB1REG): Delete
577 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
578 (get_allreg): Change to new defines. Fallback to abort().
580 2011-02-14 Mike Frysinger <vapier@gentoo.org>
582 * bfin-dis.c: Add whitespace/parenthesis where needed.
584 2011-02-14 Mike Frysinger <vapier@gentoo.org>
586 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
589 2011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
591 * configure: Regenerate.
593 2011-02-13 Mike Frysinger <vapier@gentoo.org>
595 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
597 2011-02-13 Mike Frysinger <vapier@gentoo.org>
599 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
600 dregs only when P is set, and dregs_lo otherwise.
602 2011-02-13 Mike Frysinger <vapier@gentoo.org>
604 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
606 2011-02-12 Mike Frysinger <vapier@gentoo.org>
608 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
610 2011-02-12 Mike Frysinger <vapier@gentoo.org>
612 * bfin-dis.c (machine_registers): Delete REG_GP.
613 (reg_names): Delete "GP".
614 (decode_allregs): Change REG_GP to REG_LASTREG.
616 2011-02-12 Mike Frysinger <vapier@gentoo.org>
618 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
621 2011-02-11 Mike Frysinger <vapier@gentoo.org>
623 * bfin-dis.c (reg_names): Add const.
624 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
625 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
626 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
627 decode_counters, decode_allregs): Likewise.
629 2011-02-09 Michael Snyder <msnyder@vmware.com>
631 * i386-dis.c (OP_J): Parenthesize expression to prevent
633 (print_insn): Fix indentation off-by-one.
635 2011-02-01 Nick Clifton <nickc@redhat.com>
637 * po/da.po: Updated Danish translation.
639 2011-01-21 Dave Murphy <davem@devkitpro.org>
641 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
643 2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
645 * i386-dis.c (sIbT): New.
646 (b_T_mode): Likewise.
647 (dis386): Replace sIb with sIbT on "pushT".
648 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
649 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
651 2011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
653 * i386-init.h: Regenerated.
654 * i386-tbl.h: Regenerated
656 2011-01-17 Quentin Neill <quentin.neill@amd.com>
658 * i386-dis.c (REG_XOP_TBM_01): New.
659 (REG_XOP_TBM_02): New.
660 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
661 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
662 entries, and add bextr instruction.
664 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
665 (cpu_flags): Add CpuTBM.
667 * i386-opc.h (CpuTBM) New.
668 (i386_cpu_flags): Add bit cputbm.
670 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
671 blcs, blsfill, blsic, t1mskc, and tzmsk.
673 2011-01-12 DJ Delorie <dj@redhat.com>
675 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
677 2011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
679 * mips-dis.c (print_insn_args): Adjust the value to print the real
680 offset for "+c" argument.
682 2011-01-10 Nick Clifton <nickc@redhat.com>
684 * po/da.po: Updated Danish translation.
686 2011-01-05 Nathan Sidwell <nathan@codesourcery.com>
688 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
690 2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
692 * i386-dis.c (REG_VEX_38F3): New.
693 (PREFIX_0FBC): Likewise.
694 (PREFIX_VEX_38F2): Likewise.
695 (PREFIX_VEX_38F3_REG_1): Likewise.
696 (PREFIX_VEX_38F3_REG_2): Likewise.
697 (PREFIX_VEX_38F3_REG_3): Likewise.
698 (PREFIX_VEX_38F7): Likewise.
699 (VEX_LEN_38F2_P_0): Likewise.
700 (VEX_LEN_38F3_R_1_P_0): Likewise.
701 (VEX_LEN_38F3_R_2_P_0): Likewise.
702 (VEX_LEN_38F3_R_3_P_0): Likewise.
703 (VEX_LEN_38F7_P_0): Likewise.
704 (dis386_twobyte): Use PREFIX_0FBC.
705 (reg_table): Add REG_VEX_38F3.
706 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
707 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
708 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
709 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
711 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
712 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
715 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
716 (cpu_flags): Add CpuBMI.
718 * i386-opc.h (CpuBMI): New.
719 (i386_cpu_flags): Add cpubmi.
721 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
722 * i386-init.h: Regenerated.
723 * i386-tbl.h: Likewise.
725 2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
727 * i386-dis.c (VexGdq): New.
728 (OP_VEX): Handle dq_mode.
730 2011-01-01 H.J. Lu <hongjiu.lu@intel.com>
732 * i386-gen.c (process_copyright): Update copyright to 2011.
734 For older changes see ChangeLog-2010
740 version-control: never