1 2011-10-21 Jan Glauber <jang@linux.vnet.ibm.com>
3 * s390-opc.txt: Add CPUMF instructions.
5 2011-10-18 Jie Zhang <jie@codesourcery.com>
6 Julian Brown <julian@codesourcery.com>
8 * arm-dis.c (print_insn_arm): Explicitly specify rotation if needed.
10 2011-10-10 Nick Clifton <nickc@redhat.com>
12 * po/es.po: Updated Spanish translation.
13 * po/fi.po: Updated Finnish translation.
15 2011-09-28 Jan Beulich <jbeulich@suse.com>
17 * ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX,
19 (insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset.
20 (powerpc_opcodes): Use RAX for second and RBXC for third operand of
21 lswx. Use NBI for third operand of lswi. Use FRTp for first operand of
22 lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and
23 mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively
24 on DFP quad instructions.
26 2011-09-27 David S. Miller <davem@davemloft.net>
28 * sparc-opc.c (sparc_opcodes): Fix random instruction to write
29 to a float instead of an integer register.
31 2011-09-26 David S. Miller <davem@davemloft.net>
33 * sparc-opc.c (sparc_opcodes): Add integer multiply-add
36 2011-09-21 David S. Miller <davem@davemloft.net>
38 * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
39 bits. Fix "fchksm16" mnemonic.
41 2011-09-08 Mark Fortescue <mark@mtfhpc.demon.co.uk>
43 The changes below bring 'mov' and 'ticc' instructions into line
44 with the V8 SPARC Architecture Manual.
45 * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
46 * sparc-opc.c (sparc_opcodes): Add alias entries for
47 'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
48 'mov regrs2,%wim' and 'mov regrs2,%tbr'.
49 * sparc-opc.c (sparc_opcodes): Move/Change entries for
50 'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
52 * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
55 * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
56 This has been reported as being accepted by the Sun assmebler.
58 2011-09-08 David S. Miller <davem@davemloft.net>
60 * sparc-opc.c (pdistn): Destination is integer not float register.
62 2011-09-07 Andreas Schwab <schwab@linux-m68k.org>
65 * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
67 2011-08-26 Nick Clifton <nickc@redhat.com>
69 * po/es.po: Updated Spanish translation.
71 2011-08-22 Nick Clifton <nickc@redhat.com>
73 * Makefile.am (CPUDIR): Redfine to point to top level cpu
75 (stamp-frv): Use CPUDIR.
76 (stamp-iq2000): Likewise.
77 (stamp-lm32): Likewise.
78 (stamp-m32c): Likewise.
80 (stamp-xc16x): Likewise.
81 * Makefile.in: Regenerate.
83 2011-08-09 Chao-ying Fu <fu@mips.com>
84 Maciej W. Rozycki <macro@codesourcery.com>
86 * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
88 (print_insn_args, print_insn_micromips): Handle MCU.
89 * micromips-opc.c (MC): New macro.
90 (micromips_opcodes): Add "aclr", "aset" and "iret".
91 * mips-opc.c (MC): New macro.
92 (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
94 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
96 * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
97 (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
98 (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
99 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
100 (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
101 (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
102 (WR_s): Update macro.
103 (micromips_opcodes): Update register use flags of: "addiu",
104 "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
105 "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
106 "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
107 "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
108 "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
109 "swm" and "xor" instructions.
111 2011-08-05 David S. Miller <davem@davemloft.net>
113 * sparc-dis.c (v9a_ast_reg_names): Add "cps".
115 (print_insn_sparc): Handle '4', '5', and '(' format codes.
116 Accept %asr numbers below 28.
117 * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
120 2011-08-02 Quentin Neill <quentin.neill@amd.com>
122 * i386-dis.c (xop_table): Remove spurious bextr insn.
124 2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
127 * i386-dis.c (print_insn): Optimize info->mach check.
129 2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
132 * i386-opc.tbl: Add Disp32S to 64bit call.
133 * i386-tbl.h: Regenerated.
135 2011-07-24 Chao-ying Fu <fu@mips.com>
136 Maciej W. Rozycki <macro@codesourcery.com>
138 * micromips-opc.c: New file.
139 * mips-dis.c (micromips_to_32_reg_b_map): New array.
140 (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
141 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
142 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
143 (micromips_to_32_reg_q_map): Likewise.
144 (micromips_imm_b_map, micromips_imm_c_map): Likewise.
145 (micromips_ase): New variable.
146 (is_micromips): New function.
147 (set_default_mips_dis_options): Handle microMIPS ASE.
148 (print_insn_micromips): New function.
149 (is_compressed_mode_p): Likewise.
150 (_print_insn_mips): Handle microMIPS instructions.
151 * Makefile.am (CFILES): Add micromips-opc.c.
152 * configure.in (bfd_mips_arch): Add micromips-opc.lo.
153 * Makefile.in: Regenerate.
154 * configure: Regenerate.
156 * mips-dis.c (micromips_to_32_reg_h_map): New variable.
157 (micromips_to_32_reg_i_map): Likewise.
158 (micromips_to_32_reg_m_map): Likewise.
159 (micromips_to_32_reg_n_map): New macro.
161 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
163 * mips-opc.c (NODS): New macro.
164 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
165 (DSP_VOLA): Likewise.
166 (mips_builtin_opcodes): Add NODS annotation to "deret" and
167 "eret". Replace INSN_SYNC with NODS throughout. Use NODS in
168 place of TRAP for "wait", "waiti" and "yield".
169 * mips16-opc.c (NODS): New macro.
170 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
171 (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
172 "restore" and "save".
174 2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
176 * configure.in: Handle bfd_k1om_arch.
177 * configure: Regenerated.
179 * disassemble.c (disassembler): Handle bfd_k1om_arch.
181 * i386-dis.c (print_insn): Handle bfd_mach_k1om and
182 bfd_mach_k1om_intel_syntax.
184 * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
185 ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
186 (cpu_flags): Add CpuK1OM.
188 * i386-opc.h (CpuK1OM): New.
189 (i386_cpu_flags): Add cpuk1om.
191 * i386-init.h: Regenerated.
192 * i386-tbl.h: Likewise.
194 2011-07-12 Nick Clifton <nickc@redhat.com>
196 * arm-dis.c (print_insn_arm): Revert previous, undocumented,
199 2011-07-01 Nick Clifton <nickc@redhat.com>
202 * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
203 insns using post-increment addressing.
205 2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
207 * i386-dis.c (vex_len_table): Update rorxS.
209 2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
211 AVX Programming Reference (June, 2011)
212 * i386-dis.c (vex_len_table): Correct rorxS.
214 * i386-opc.tbl: Correct rorx.
215 * i386-tbl.h: Regenerated.
217 2011-06-29 H.J. Lu <hongjiu.lu@intel.com>
219 * tilegx-opc.c (find_opcode): Replace "index" with "i".
220 * tilepro-opc.c (find_opcode): Likewise.
222 2011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
224 * mips16-opc.c (jalrc, jrc): Move earlier in file.
226 2011-06-21 H.J. Lu <hongjiu.lu@intel.com>
228 * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
231 2011-06-17 Andreas Schwab <schwab@redhat.com>
233 * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
234 (MOSTLYCLEANFILES): ... here.
235 * Makefile.in: Regenerate.
237 2011-06-14 Alan Modra <amodra@gmail.com>
239 * Makefile.in: Regenerate.
241 2011-06-13 Walter Lee <walt@tilera.com>
243 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
244 tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
245 * Makefile.in: Regenerate.
246 * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
247 * configure: Regenerate.
248 * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
249 * po/POTFILES.in: Regenerate.
250 * tilegx-dis.c: New file.
251 * tilegx-opc.c: New file.
252 * tilepro-dis.c: New file.
253 * tilepro-opc.c: New file.
255 2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
257 AVX Programming Reference (June, 2011)
258 * i386-dis.c (XMGatherQ): New.
259 * i386-dis.c (EXxmm_mb): New.
260 (EXxmm_mb): Likewise.
261 (EXxmm_mw): Likewise.
262 (EXxmm_md): Likewise.
263 (EXxmm_mq): Likewise.
266 (VexGatherQ): Likewise.
267 (MVexVSIBDWpX): Likewise.
268 (MVexVSIBQWpX): Likewise.
269 (xmm_mb_mode): Likewise.
270 (xmm_mw_mode): Likewise.
271 (xmm_md_mode): Likewise.
272 (xmm_mq_mode): Likewise.
273 (xmmdw_mode): Likewise.
274 (xmmqd_mode): Likewise.
275 (ymmxmm_mode): Likewise.
276 (vex_vsib_d_w_dq_mode): Likewise.
277 (vex_vsib_q_w_dq_mode): Likewise.
278 (MOD_VEX_0F385A_PREFIX_2): Likewise.
279 (MOD_VEX_0F388C_PREFIX_2): Likewise.
280 (MOD_VEX_0F388E_PREFIX_2): Likewise.
281 (PREFIX_0F3882): Likewise.
282 (PREFIX_VEX_0F3816): Likewise.
283 (PREFIX_VEX_0F3836): Likewise.
284 (PREFIX_VEX_0F3845): Likewise.
285 (PREFIX_VEX_0F3846): Likewise.
286 (PREFIX_VEX_0F3847): Likewise.
287 (PREFIX_VEX_0F3858): Likewise.
288 (PREFIX_VEX_0F3859): Likewise.
289 (PREFIX_VEX_0F385A): Likewise.
290 (PREFIX_VEX_0F3878): Likewise.
291 (PREFIX_VEX_0F3879): Likewise.
292 (PREFIX_VEX_0F388C): Likewise.
293 (PREFIX_VEX_0F388E): Likewise.
294 (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
295 (PREFIX_VEX_0F38F5): Likewise.
296 (PREFIX_VEX_0F38F6): Likewise.
297 (PREFIX_VEX_0F3A00): Likewise.
298 (PREFIX_VEX_0F3A01): Likewise.
299 (PREFIX_VEX_0F3A02): Likewise.
300 (PREFIX_VEX_0F3A38): Likewise.
301 (PREFIX_VEX_0F3A39): Likewise.
302 (PREFIX_VEX_0F3A46): Likewise.
303 (PREFIX_VEX_0F3AF0): Likewise.
304 (VEX_LEN_0F3816_P_2): Likewise.
305 (VEX_LEN_0F3819_P_2): Likewise.
306 (VEX_LEN_0F3836_P_2): Likewise.
307 (VEX_LEN_0F385A_P_2_M_0): Likewise.
308 (VEX_LEN_0F38F5_P_0): Likewise.
309 (VEX_LEN_0F38F5_P_1): Likewise.
310 (VEX_LEN_0F38F5_P_3): Likewise.
311 (VEX_LEN_0F38F6_P_3): Likewise.
312 (VEX_LEN_0F38F7_P_1): Likewise.
313 (VEX_LEN_0F38F7_P_2): Likewise.
314 (VEX_LEN_0F38F7_P_3): Likewise.
315 (VEX_LEN_0F3A00_P_2): Likewise.
316 (VEX_LEN_0F3A01_P_2): Likewise.
317 (VEX_LEN_0F3A38_P_2): Likewise.
318 (VEX_LEN_0F3A39_P_2): Likewise.
319 (VEX_LEN_0F3A46_P_2): Likewise.
320 (VEX_LEN_0F3AF0_P_3): Likewise.
321 (VEX_W_0F3816_P_2): Likewise.
322 (VEX_W_0F3818_P_2): Likewise.
323 (VEX_W_0F3819_P_2): Likewise.
324 (VEX_W_0F3836_P_2): Likewise.
325 (VEX_W_0F3846_P_2): Likewise.
326 (VEX_W_0F3858_P_2): Likewise.
327 (VEX_W_0F3859_P_2): Likewise.
328 (VEX_W_0F385A_P_2_M_0): Likewise.
329 (VEX_W_0F3878_P_2): Likewise.
330 (VEX_W_0F3879_P_2): Likewise.
331 (VEX_W_0F3A00_P_2): Likewise.
332 (VEX_W_0F3A01_P_2): Likewise.
333 (VEX_W_0F3A02_P_2): Likewise.
334 (VEX_W_0F3A38_P_2): Likewise.
335 (VEX_W_0F3A39_P_2): Likewise.
336 (VEX_W_0F3A46_P_2): Likewise.
337 (MOD_VEX_0F3818_PREFIX_2): Removed.
338 (MOD_VEX_0F3819_PREFIX_2): Likewise.
339 (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
340 (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
341 (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
342 (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
343 (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
344 (VEX_LEN_0F3A0E_P_2): Likewise.
345 (VEX_LEN_0F3A0F_P_2): Likewise.
346 (VEX_LEN_0F3A42_P_2): Likewise.
347 (VEX_LEN_0F3A4C_P_2): Likewise.
348 (VEX_W_0F3818_P_2_M_0): Likewise.
349 (VEX_W_0F3819_P_2_M_0): Likewise.
350 (prefix_table): Updated.
351 (three_byte_table): Likewise.
352 (vex_table): Likewise.
353 (vex_len_table): Likewise.
354 (vex_w_table): Likewise.
355 (mod_table): Likewise.
356 (putop): Handle "LW".
357 (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
358 xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
359 vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
361 (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
362 vex_vsib_q_w_dq_mode.
363 (OP_XMM): Handle vex_vsib_q_w_dq_mode.
366 * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
367 and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
368 CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
369 (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
370 (opcode_modifiers): Add VecSIB.
372 * i386-opc.h (CpuAVX2): New.
374 (CpuLZCNT): Likewise.
375 (CpuINVPCID): Likewise.
376 (VecSIB128): Likewise.
377 (VecSIB256): Likewise.
379 (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
380 (i386_opcode_modifier): Add vecsib.
382 * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
383 * i386-init.h: Regenerated.
384 * i386-tbl.h: Likewise.
386 2011-06-03 Quentin Neill <quentin.neill@amd.com>
388 * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
389 * i386-init.h: Regenerated.
391 2011-06-03 Nick Clifton <nickc@redhat.com>
394 * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
395 computing address offsets.
396 (print_arm_address): Likewise.
397 (print_insn_arm): Likewise.
398 (print_insn_thumb16): Likewise.
399 (print_insn_thumb32): Likewise.
401 2011-06-02 Jie Zhang <jie@codesourcery.com>
402 Nathan Sidwell <nathan@codesourcery.com>
403 Maciej Rozycki <macro@codesourcery.com>
405 * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
407 (print_arm_address): Likewise. Elide positive #0 appropriately.
408 (print_insn_arm): Likewise.
410 2011-06-02 Nick Clifton <nickc@redhat.com>
413 * arm-dis.c (print_insn_thumb32): Do not sign extend addresses
414 passed to print_address_func.
416 2011-06-02 Nick Clifton <nickc@redhat.com>
418 * arm-dis.c: Fix spelling mistakes.
419 * op/opcodes.pot: Regenerate.
421 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
423 * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
424 S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
425 * s390-opc.txt: Fix cxr instruction type.
427 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
429 * s390-opc.c: Add new instruction types marking register pair
431 * s390-opc.txt: Match instructions having register pair operands
432 to the new instruction types.
434 2011-05-19 Nick Clifton <nickc@redhat.com>
436 * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
439 2011-05-10 Quentin Neill <quentin.neill@amd.com>
441 * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
442 * i386-init.h: Regenerated.
444 2011-04-27 Nick Clifton <nickc@redhat.com>
446 * po/da.po: Updated Danish translation.
448 2011-04-26 Anton Blanchard <anton@samba.org>
450 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
452 2011-04-21 DJ Delorie <dj@redhat.com>
454 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
455 * rx-decode.c: Regenerate.
457 2011-04-20 H.J. Lu <hongjiu.lu@intel.com>
459 * i386-init.h: Regenerated.
461 2011-04-19 Quentin Neill <quentin.neill@amd.com>
463 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
466 2011-04-13 Nick Clifton <nickc@redhat.com>
468 * v850-dis.c (disassemble): Always print a closing square brace if
469 an opening square brace was printed.
471 2011-04-12 Nick Clifton <nickc@redhat.com>
474 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
476 (print_insn_thumb32): Handle %L.
478 2011-04-11 Julian Brown <julian@codesourcery.com>
480 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
481 (print_insn_thumb32): Add APSR bitmask support.
483 2011-04-07 Paul Carroll<pcarroll@codesourcery.com>
485 * arm-dis.c (print_insn): init vars moved into private_data structure.
487 2011-03-24 Mike Frysinger <vapier@gentoo.org>
489 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
491 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
493 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
494 post-increment to support LPM Z+ instruction. Add support for 'E'
495 constraint for DES instruction.
496 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
498 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
500 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
502 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
504 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
505 Use branch types instead.
506 (print_insn): Likewise.
508 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
510 * mips-opc.c (mips_builtin_opcodes): Correct register use
511 annotation of "alnv.ps".
513 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
515 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
517 2011-02-22 Mike Frysinger <vapier@gentoo.org>
519 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
521 2011-02-22 Mike Frysinger <vapier@gentoo.org>
523 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
525 2011-02-19 Mike Frysinger <vapier@gentoo.org>
527 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
528 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
529 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
530 exception, end_of_registers, msize, memory, bfd_mach.
531 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
532 LB0REG, LC1REG, LT1REG, LB1REG): Delete
533 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
534 (get_allreg): Change to new defines. Fallback to abort().
536 2011-02-14 Mike Frysinger <vapier@gentoo.org>
538 * bfin-dis.c: Add whitespace/parenthesis where needed.
540 2011-02-14 Mike Frysinger <vapier@gentoo.org>
542 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
545 2011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
547 * configure: Regenerate.
549 2011-02-13 Mike Frysinger <vapier@gentoo.org>
551 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
553 2011-02-13 Mike Frysinger <vapier@gentoo.org>
555 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
556 dregs only when P is set, and dregs_lo otherwise.
558 2011-02-13 Mike Frysinger <vapier@gentoo.org>
560 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
562 2011-02-12 Mike Frysinger <vapier@gentoo.org>
564 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
566 2011-02-12 Mike Frysinger <vapier@gentoo.org>
568 * bfin-dis.c (machine_registers): Delete REG_GP.
569 (reg_names): Delete "GP".
570 (decode_allregs): Change REG_GP to REG_LASTREG.
572 2011-02-12 Mike Frysinger <vapier@gentoo.org>
574 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
577 2011-02-11 Mike Frysinger <vapier@gentoo.org>
579 * bfin-dis.c (reg_names): Add const.
580 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
581 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
582 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
583 decode_counters, decode_allregs): Likewise.
585 2011-02-09 Michael Snyder <msnyder@vmware.com>
587 * i386-dis.c (OP_J): Parenthesize expression to prevent
589 (print_insn): Fix indentation off-by-one.
591 2011-02-01 Nick Clifton <nickc@redhat.com>
593 * po/da.po: Updated Danish translation.
595 2011-01-21 Dave Murphy <davem@devkitpro.org>
597 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
599 2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
601 * i386-dis.c (sIbT): New.
602 (b_T_mode): Likewise.
603 (dis386): Replace sIb with sIbT on "pushT".
604 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
605 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
607 2011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
609 * i386-init.h: Regenerated.
610 * i386-tbl.h: Regenerated
612 2011-01-17 Quentin Neill <quentin.neill@amd.com>
614 * i386-dis.c (REG_XOP_TBM_01): New.
615 (REG_XOP_TBM_02): New.
616 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
617 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
618 entries, and add bextr instruction.
620 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
621 (cpu_flags): Add CpuTBM.
623 * i386-opc.h (CpuTBM) New.
624 (i386_cpu_flags): Add bit cputbm.
626 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
627 blcs, blsfill, blsic, t1mskc, and tzmsk.
629 2011-01-12 DJ Delorie <dj@redhat.com>
631 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
633 2011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
635 * mips-dis.c (print_insn_args): Adjust the value to print the real
636 offset for "+c" argument.
638 2011-01-10 Nick Clifton <nickc@redhat.com>
640 * po/da.po: Updated Danish translation.
642 2011-01-05 Nathan Sidwell <nathan@codesourcery.com>
644 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
646 2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
648 * i386-dis.c (REG_VEX_38F3): New.
649 (PREFIX_0FBC): Likewise.
650 (PREFIX_VEX_38F2): Likewise.
651 (PREFIX_VEX_38F3_REG_1): Likewise.
652 (PREFIX_VEX_38F3_REG_2): Likewise.
653 (PREFIX_VEX_38F3_REG_3): Likewise.
654 (PREFIX_VEX_38F7): Likewise.
655 (VEX_LEN_38F2_P_0): Likewise.
656 (VEX_LEN_38F3_R_1_P_0): Likewise.
657 (VEX_LEN_38F3_R_2_P_0): Likewise.
658 (VEX_LEN_38F3_R_3_P_0): Likewise.
659 (VEX_LEN_38F7_P_0): Likewise.
660 (dis386_twobyte): Use PREFIX_0FBC.
661 (reg_table): Add REG_VEX_38F3.
662 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
663 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
664 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
665 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
667 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
668 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
671 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
672 (cpu_flags): Add CpuBMI.
674 * i386-opc.h (CpuBMI): New.
675 (i386_cpu_flags): Add cpubmi.
677 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
678 * i386-init.h: Regenerated.
679 * i386-tbl.h: Likewise.
681 2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
683 * i386-dis.c (VexGdq): New.
684 (OP_VEX): Handle dq_mode.
686 2011-01-01 H.J. Lu <hongjiu.lu@intel.com>
688 * i386-gen.c (process_copyright): Update copyright to 2011.
690 For older changes see ChangeLog-2010
696 version-control: never