1 2012-11-20 Kirill Yukhin <kirill.yukhin@intel.com>
2 H.J. Lu <hongjiu.lu@intel.com>
5 * i386-opc.tbl: Fix opcode for 64-bit jecxz.
6 * i386-tbl.h: Regenerated.
8 2012-11-20 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
10 * s390-opc.txt: Fix srstu and strag opcodes.
12 2012-11-14 David Holsgrove <david.holsgrove@xilinx.com>
14 * microblaze-opc.h: Define new instruction type INST_TYPE_IMM5,
15 update OPCODE_MASK_H13S, add OPCODE_MASK_HN, define MIN_IMM5 / MAX_IMM5,
16 and increase MAX_OPCODES.
17 (op_code_struct): add mbar and sleep
18 * microblaze-opcm.h (microblaze_instr): add mbar
19 Define IMM_MBAR and IMM5_MBAR_MASK
20 * microblaze-dis.c: Add get_field_imm5_mbar
21 (print_insn_microblaze): Add support for INST_TYPE_IMM5 and INST_TYPE_NONE
23 2012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com>
25 * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add clz insn
26 * microblaze-opcm.h (microblaze_instr): add clz
28 2012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com>
30 * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add lbur,
31 lhur, lwr, sbr, shr, swr
32 * microblaze-opcm.h (microblaze_instr): add lbur, lhur, lwr, sbr, shr,
35 2012-11-09 Nick Clifton <nickc@redhat.com>
37 * configure.in: Add bfd_v850_rh850_arch.
38 * configure: Regenerate.
39 * disassemble.c (disassembler): Likewise.
41 2012-11-09 H.J. Lu <hongjiu.lu@intel.com>
43 * aarch64-opc.h (gen_mask): Remove trailing redundant `;'.
44 * ia64-gen.c (fetch_insn_class): Likewise.
46 2012-11-08 Alan Modra <amodra@gmail.com>
48 * po/POTFILES.in: Regenerate.
50 2012-11-05 Alan Modra <amodra@gmail.com>
52 * configure.in: Apply 2012-09-10 change to config.in here.
54 2012-10-26 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
56 * s390-mkopc.c: Accept empty lines in s390-opc.txt.
57 * s390-opc.c: Add M_20OPT field. New instruction formats RRF_RURR2
59 * s390-opc.txt: Add new instructions. New instruction type for lptea.
61 2012-10-26 Christian Groessler <chris@groessler.org>
63 * z8kgen.c (struct op): Fix encoding for translate opcodes (trdb,
64 trdrb, trib, trirb, trtdb, trtdrb, trtib, trtirb). Remove
65 non-existing opcode trtrb.
66 * z8k-opc.h: Regenerate.
68 2012-10-26 Alan Modra <amodra@gmail.com>
70 * ppc-opc (powerpc_opcodes): "lfdp" and "stfdp" use DS offset.
72 2012-10-24 Roland McGrath <mcgrathr@google.com>
74 * i386-dis.c (ckprefix): When bailing out for fwait with prefixes,
77 2012-10-22 Peter Bergner <bergner@vnet.ibm.com>
79 * ppc-opc.c (powerpc_opcodes) <vcfpsxws>: Fix opcode spelling.
81 2012-10-18 Tom Tromey <tromey@redhat.com>
83 * tic54x-dis.c (print_instruction): Don't use K&R style.
84 (print_parallel_instruction, sprint_dual_address)
85 (sprint_indirect_address, sprint_direct_address, sprint_mmr)
86 (sprint_cc2, sprint_condition): Likewise.
88 2012-10-18 Kai Tietz <ktietz@redhat.com>
90 * aarch64-asm.c (aarch64_ins_ldst_reglist): Initialize
92 (do_special_encoding): Likewise.
93 (aarch64_ins_ldst_elemlist): Pre-initialize QSsize, and opcodeh2
94 variables with default.
95 * arc-dis.c (write_comments_): Don't use strncat due
96 size of state->commentBuffer pointer isn't predictable.
98 2012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
100 * aarch64-opc.c (aarch64_sys_regs): Add rmr_el1, rmr_el2 and
101 rmr_el3; remove daifset and daifclr.
103 2012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
105 * aarch64-opc.c (operand_general_constraint_met_p): Change to check
106 the alignment of addr.offset.imm instead of that of shifter.amount for
107 operand type AARCH64_OPND_ADDR_UIMM12.
109 2012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
111 * arm-dis.c: Use preferred form of vrint instruction variants
114 2012-10-09 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
116 * i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS.
117 * i386-init.h: Regenerated.
119 2012-10-05 Peter Bergner <bergner@vnet.ibm.com>
121 * ppc-dis.c (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2;
122 * ppc-opc.c (VBA): New define.
123 (powerpc_opcodes) <vcuxwfp, vcsxwfp, vcfpuxws, vcfpsxsw, vmr, vnot,
124 mfppr, mfppr32, mtppr, mtppr32>: New extended mnemonics.
126 2012-10-04 Nick Clifton <nickc@redhat.com>
128 * v850-dis.c (disassemble): Place square parentheses around second
129 register operand of clr1, not1, set1 and tst1 instructions.
131 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
133 * s390-mkopc.c: Support new option zEC12.
134 * s390-opc.c: Add new instruction formats.
135 * s390-opc.txt: Add new instructions for zEC12.
137 2012-09-27 Anthony Green <green@moxielogic.com>
139 * moxie-dis.c (print_insn_moxie): Print 'bad' instructions.
140 * moxie-opc.c: All 'bad' instructions have the itype MOXIE_BAD.
142 2012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
144 * i386-gen.c (cpu_flag_init): Add missing Cpu flags in
145 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS
146 and CPU_BTVER2_FLAGS.
147 * i386-init.h: Regenerated.
149 2012-09-20 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
151 * i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS,
152 CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS,
153 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS,
154 CPU_BTVER2_FLAGS. Add CPU_CX16_FLAGS.
155 (cpu_flags): Add CpuCX16.
156 * i386-opc.h (CpuCX16): New.
157 (i386_cpu_flags): Add cpucx16.
158 * i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b.
159 * i386-tbl.h: Regenerate.
160 * i386-init.h: Likewise.
162 2012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
164 * arm-dis.c: Changed ldra and strl-form mnemonics
167 2012-09-18 Chao-ying Fu <fu@mips.com>
169 * micromips-opc.c (micromips_opcodes): Correct the encoding of
170 the "swxc1" instruction.
172 2012-09-17 Yufeng Zhang <yufeng.zhang@arm.com>
174 * aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from
175 the parameter 'inst'.
176 (aarch64_ins_addr_simm): Add ATTRIBUTE_UNUSED to the parameter 'inst'.
177 (convert_mov_to_movewide): Change to assert (0) when
178 aarch64_wide_constant_p returns FALSE.
180 2012-09-14 David Edelsohn <dje.gcc@gmail.com>
182 * configure: Regenerate.
184 2012-09-14 Anthony Green <green@moxielogic.com>
186 * moxie-dis.c (print_insn_moxie): Branch targets are relative to
187 the address after the branch instruction.
189 2012-09-13 Anthony Green <green@moxielogic.com>
191 * moxie-dis.c (print_insn_moxie): Handle bi-endian encodings.
193 2012-09-10 Matthias Klose <doko@ubuntu.com>
195 * config.in: Disable sanity check for kfreebsd.
197 2012-09-10 H.J. Lu <hongjiu.lu@intel.com>
199 * configure: Regenerated.
201 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
203 * ia64-asmtab.h (completer_index): Extend bitfield to full uint.
204 * ia64-gen.c: Promote completer index type to longlong.
205 (irf_operand): Add new register recognition.
206 (in_iclass_mov_x): Add an entry for the new mov_* instruction type.
207 (lookup_specifier): Add new resource recognition.
208 (insert_bit_table_ent): Relax abort condition according to the
209 changed completer index type.
210 (print_dis_table): Fix printf format for completer index.
211 * ia64-ic.tbl: Add a new instruction class.
212 * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
213 * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
214 * ia64-opc.h: Define short names for new operand types.
215 * ia64-raw.tbl: Add new RAW resource for DAHR register.
216 * ia64-waw.tbl: Add new WAW resource for DAHR register.
217 * ia64-asmtab.c: Regenerate.
219 2012-08-29 Peter Bergner <bergner@vnet.ibm.com>
221 * ppc-opc.c (VXASHB_MASK): New define.
222 (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK.
224 2012-08-28 Peter Bergner <bergner@vnet.ibm.com>
226 * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
227 VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
228 (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
229 vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
230 vupklsh>: Use VXVA_MASK.
231 <vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
232 <mfvscr>: Use VXVAVB_MASK.
233 <mtvscr>: Use VXVDVA_MASK.
234 <vspltb>: Use VXUIMM4_MASK.
235 <vsplth>: Use VXUIMM3_MASK.
236 <vspltw>: Use VXUIMM2_MASK.
238 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
240 * arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
242 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
244 * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
246 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
248 * arm-dis.c (neon_opcodes): Handle VMULL.P64.
250 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
252 * arm-dis.c (neon_opcodes): Add support for AES instructions.
254 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
256 * arm-dis.c (coprocessor_opcodes): Add support for HP/DP
259 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
261 * arm-dis.c (coprocessor_opcodes): Add VRINT.
262 (neon_opcodes): Likewise.
264 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
266 * arm-dis.c (coprocessor_opcodes): Add support for new VCVT
268 (neon_opcodes): Likewise.
270 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
272 * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
273 (neon_opcodes): Likewise.
275 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
277 * arm-dis.c (coprocessor_opcodes): Add VSEL.
278 (print_insn_coprocessor): Add new %<>c bitfield format
281 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
283 * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
284 (thumb32_opcodes): Likewise.
285 (print_arm_insn): Add support for %<>T formatter.
287 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
289 * arm-dis.c (arm_opcodes): Add HLT.
290 (thumb_opcodes): Likewise.
292 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
294 * arm-dis.c (thumb32_opcodes): Add DCPS instruction.
296 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
298 * arm-dis.c (arm_opcodes): Add SEVL.
299 (thumb_opcodes): Likewise.
300 (thumb32_opcodes): Likewise.
302 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
304 * arm-dis.c (data_barrier_option): New function.
305 (print_insn_arm): Use data_barrier_option.
306 (print_insn_thumb32): Use data_barrier_option.
308 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com
310 * arm-dis.c (COND_UNCOND): New constant.
311 (print_insn_coprocessor): Add support for %u format specifier.
312 (print_insn_neon): Likewise.
314 2012-08-21 David S. Miller <davem@davemloft.net>
316 * sparc-opc.c (4-argument crypto instructions): Fix encoding using
319 2012-08-20 Edmar Wienskoski <edmar@freescale.com>
321 * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
322 vabsduh, vabsduw, mviwsplt.
324 2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
326 * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
329 * i386-opc.h: Update CpuPRFCHW comment.
331 * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
332 * i386-init.h: Regenerated.
333 * i386-tbl.h: Likewise.
335 2012-08-17 Nick Clifton <nickc@redhat.com>
337 * po/uk.po: New Ukranian translation.
338 * configure.in (ALL_LINGUAS): Add uk.
339 * configure: Regenerate.
341 2012-08-16 Peter Bergner <bergner@vnet.ibm.com>
343 * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
344 RBX for the third operand.
345 <"lswi">: Use RAX for second and NBI for the third operand.
347 2012-08-15 DJ Delorie <dj@redhat.com>
349 * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
350 operands, so that data addresses can be corrected when not
352 * rl78-decode.c: Regenerate.
353 * rl78-dis.c (print_insn_rl78): Make order of modifiers
354 irrelevent. When the 'e' specifier is used on an operand and no
355 ES prefix is provided, adjust address to make it absolute.
357 2012-08-15 Peter Bergner <bergner@vnet.ibm.com>
359 * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
361 2012-08-15 Peter Bergner <bergner@vnet.ibm.com>
363 * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics.
365 2012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
367 * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
368 macros, use local variables for info struct member accesses,
369 update the type of the variable used to hold the instruction
371 (print_insn_mips, print_mips16_insn_arg): Likewise.
372 (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
373 local variables for info struct member accesses.
374 (print_insn_micromips): Add GET_OP_S local macro.
375 (_print_insn_mips): Update the type of the variable used to hold
376 the instruction word.
378 2012-08-13 Ian Bolton <ian.bolton@arm.com>
379 Laurent Desnogues <laurent.desnogues@arm.com>
380 Jim MacArthur <jim.macarthur@arm.com>
381 Marcus Shawcroft <marcus.shawcroft@arm.com>
382 Nigel Stephens <nigel.stephens@arm.com>
383 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
384 Richard Earnshaw <rearnsha@arm.com>
385 Sofiane Naci <sofiane.naci@arm.com>
386 Tejas Belagod <tejas.belagod@arm.com>
387 Yufeng Zhang <yufeng.zhang@arm.com>
389 * Makefile.am: Add AArch64.
390 * Makefile.in: Regenerate.
391 * aarch64-asm.c: New file.
392 * aarch64-asm.h: New file.
393 * aarch64-dis.c: New file.
394 * aarch64-dis.h: New file.
395 * aarch64-gen.c: New file.
396 * aarch64-opc.c: New file.
397 * aarch64-opc.h: New file.
398 * aarch64-tbl.h: New file.
399 * configure.in: Add AArch64.
400 * configure: Regenerate.
401 * disassemble.c: Add AArch64.
402 * aarch64-asm-2.c: New file (automatically generated).
403 * aarch64-dis-2.c: New file (automatically generated).
404 * aarch64-opc-2.c: New file (automatically generated).
405 * po/POTFILES.in: Regenerate.
407 2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
409 * micromips-opc.c (micromips_opcodes): Update comment.
410 * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
411 instructions for IOCT as appropriate.
412 * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
414 * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
415 the result of a check for the -Wno-missing-field-initializers
417 * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
418 (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
420 (mips16-opc.lo): Likewise.
421 (micromips-opc.lo): Likewise.
422 * aclocal.m4: Regenerate.
423 * configure: Regenerate.
424 * Makefile.in: Regenerate.
426 2012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
429 * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS.
430 * i386-init.h: Regenerated.
432 2012-08-09 Nick Clifton <nickc@redhat.com>
434 * po/vi.po: Updated Vietnamese translation.
436 2012-08-07 Roland McGrath <mcgrathr@google.com>
438 * i386-dis.c (reg_table): Fill out REG_0F0D table with
439 AMD-reserved cases as "prefetch".
440 (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
441 (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
442 (reg_table): Use those under REG_0F18.
443 (mod_table): Add those cases as "nop/reserved".
445 2012-08-07 Jan Beulich <jbeulich@suse.com>
447 * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
449 2012-08-06 Roland McGrath <mcgrathr@google.com>
451 * i386-dis.c (print_insn): Print spaces between multiple excess
452 prefixes. Return actual number of excess prefixes consumed,
455 * i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
457 2012-08-06 Roland McGrath <mcgrathr@google.com>
458 Victor Khimenko <khim@google.com>
459 H.J. Lu <hongjiu.lu@intel.com>
461 * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG.
462 (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG.
463 (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG.
464 (OP_E_register): Likewise.
465 (OP_REG): For low 8 whole registers, treat REX_W like DFLAG.
467 2012-08-02 Jan-Benedict Glaw <jbglaw@lug-owl.de>
469 * configure.in: Formatting.
470 * configure: Regenerate.
472 2012-08-01 Alan Modra <amodra@gmail.com>
474 * h8300-dis.c: Fix printf arg warnings.
475 * i960-dis.c: Likewise.
476 * mips-dis.c: Likewise.
477 * pdp11-dis.c: Likewise.
478 * sh-dis.c: Likewise.
479 * v850-dis.c: Likewise.
480 * configure.in: Formatting.
481 * configure: Regenerate.
482 * rl78-decode.c: Regenerate.
483 * po/POTFILES.in: Regenerate.
485 2012-07-31 Chao-Ying Fu <fu@mips.com>
486 Catherine Moore <clm@codesourcery.com>
487 Maciej W. Rozycki <macro@codesourcery.com>
489 * micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
490 (DSP_VOLA): Likewise.
491 (D32, D33): Likewise.
492 (micromips_opcodes): Add DSP ASE instructions.
493 * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
494 <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
496 2012-07-31 Jan Beulich <jbeulich@suse.com>
498 * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2
499 instruction group. Mark as requiring AVX2.
500 * i386-tbl.h: Re-generate.
502 2012-07-30 Nick Clifton <nickc@redhat.com>
504 * po/opcodes.pot: Updated template.
505 * po/es.po: Updated Spanish translation.
506 * po/fi.po: Updated Finnish translation.
508 2012-07-27 Mike Frysinger <vapier@gentoo.org>
510 * configure.in (BFD_VERSION): Run bfd/configure --version and
511 parse the output of that.
512 * configure: Regenerate.
514 2012-07-25 James Lemke <jwlemke@codesourcery.com>
516 * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
518 2012-07-24 Stephan McCamant <smcc@cs.berkeley.edu>
519 Dr David Alan Gilbert <dave@treblig.org>
522 * arm-dis.c: Add necessary casts for printing integer values.
523 Use %s when printing string values.
524 * hppa-dis.c: Likewise.
525 * m68k-dis.c: Likewise.
526 * microblaze-dis.c: Likewise.
527 * mips-dis.c: Likewise.
528 * sparc-dis.c: Likewise.
530 2012-07-19 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
533 * i386-dis.c (VEX_LEN_0FXOP_08_CC): New.
534 (VEX_LEN_0FXOP_08_CD): Likewise.
535 (VEX_LEN_0FXOP_08_CE): Likewise.
536 (VEX_LEN_0FXOP_08_CF): Likewise.
537 (VEX_LEN_0FXOP_08_EC): Likewise.
538 (VEX_LEN_0FXOP_08_ED): Likewise.
539 (VEX_LEN_0FXOP_08_EE): Likewise.
540 (VEX_LEN_0FXOP_08_EF): Likewise.
541 (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq,
542 vpcomub, vpcomuw, vpcomud, vpcomuq.
543 (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC,
544 VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF,
545 VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE,
548 2012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
550 * i386-dis.c (PREFIX_0F38F6): New.
551 (prefix_table): Add adcx, adox instructions.
552 (three_byte_table): Use PREFIX_0F38F6.
553 (mod_table): Add rdseed instruction.
554 * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
555 (cpu_flags): Likewise.
556 * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
557 (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
558 * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
560 * i386-tbl.h: Regenerate.
561 * i386-init.h: Likewise.
563 2012-07-05 Thomas Schwinge <thomas@codesourcery.com>
565 * mips-dis.c: Remove gratuitous newline.
567 2012-07-05 Sean Keys <skeys@ipdatasys.com>
569 * xgate-dis.c: Removed an IF statement that will
570 always be false due to overlapping operand masks.
571 * xgate-opc.c: Corrected 'com' opcode entry and
574 2012-07-02 Roland McGrath <mcgrathr@google.com>
576 * i386-opc.tbl: Add RepPrefixOk to nop.
577 * i386-tbl.h: Regenerate.
579 2012-06-28 Nick Clifton <nickc@redhat.com>
581 * po/vi.po: Updated Vietnamese translation.
583 2012-06-22 Roland McGrath <mcgrathr@google.com>
585 * i386-opc.tbl: Add RepPrefixOk to ret.
586 * i386-tbl.h: Regenerate.
588 * i386-opc.h (RepPrefixOk): New enum constant.
589 (i386_opcode_modifier): New bitfield 'repprefixok'.
590 * i386-gen.c (opcode_modifiers): Add RepPrefixOk.
591 * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
592 instructions that have IsString.
593 * i386-tbl.h: Regenerate.
595 2012-06-11 Andreas Schwab <schwab@linux-m68k.org>
597 * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx)
598 (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx)
599 (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls)
600 (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst)
601 (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep)
602 (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls)
603 (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x)
604 (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx)
605 (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0.
607 2012-05-19 Alan Modra <amodra@gmail.com>
609 * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h.
610 (get_powerpc_dialect): Detect VLE sections from ELF sh_flags.
612 2012-05-18 Alan Modra <amodra@gmail.com>
614 * ia64-opc.c: Remove #include "ansidecl.h".
615 * z8kgen.c: Include sysdep.h first.
617 * arc-dis.c: Include sysdep.h first, remove some redundant includes.
618 * bfin-dis.c: Likewise.
619 * i860-dis.c: Likewise.
620 * ia64-dis.c: Likewise.
621 * ia64-gen.c: Likewise.
622 * m68hc11-dis.c: Likewise.
623 * mmix-dis.c: Likewise.
624 * msp430-dis.c: Likewise.
625 * or32-dis.c: Likewise.
626 * rl78-dis.c: Likewise.
627 * rx-dis.c: Likewise.
628 * tic4x-dis.c: Likewise.
629 * tilegx-opc.c: Likewise.
630 * tilepro-opc.c: Likewise.
631 * rx-decode.c: Regenerate.
633 2012-05-17 James Lemke <jwlemke@codesourcery.com>
635 * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi.
637 2012-05-17 James Lemke <jwlemke@codesourcery.com>
639 * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE.
641 2012-05-17 Daniel Richard G. <skunk@iskunk.org>
642 Nick Clifton <nickc@redhat.com>
645 * configure.in: Add check that sysdep.h has been included before
646 any system header files.
647 * configure: Regenerate.
648 * config.in: Regenerate.
649 * sysdep.h: Generate an error if included before config.h.
650 * alpha-opc.c: Include sysdep.h before any other header file.
651 * alpha-dis.c: Likewise.
652 * avr-dis.c: Likewise.
653 * cgen-opc.c: Likewise.
654 * cr16-dis.c: Likewise.
655 * cris-dis.c: Likewise.
656 * crx-dis.c: Likewise.
657 * d10v-dis.c: Likewise.
658 * d10v-opc.c: Likewise.
659 * d30v-dis.c: Likewise.
660 * d30v-opc.c: Likewise.
661 * h8500-dis.c: Likewise.
662 * i370-dis.c: Likewise.
663 * i370-opc.c: Likewise.
664 * m10200-dis.c: Likewise.
665 * m10300-dis.c: Likewise.
666 * micromips-opc.c: Likewise.
667 * mips-opc.c: Likewise.
668 * mips61-opc.c: Likewise.
669 * moxie-dis.c: Likewise.
670 * or32-opc.c: Likewise.
671 * pj-dis.c: Likewise.
672 * ppc-dis.c: Likewise.
673 * ppc-opc.c: Likewise.
674 * s390-dis.c: Likewise.
675 * sh-dis.c: Likewise.
676 * sh64-dis.c: Likewise.
677 * sparc-dis.c: Likewise.
678 * sparc-opc.c: Likewise.
679 * spu-dis.c: Likewise.
680 * tic30-dis.c: Likewise.
681 * tic54x-dis.c: Likewise.
682 * tic80-dis.c: Likewise.
683 * tic80-opc.c: Likewise.
684 * tilegx-dis.c: Likewise.
685 * tilepro-dis.c: Likewise.
686 * v850-dis.c: Likewise.
687 * v850-opc.c: Likewise.
688 * vax-dis.c: Likewise.
689 * w65-dis.c: Likewise.
690 * xgate-dis.c: Likewise.
691 * xtensa-dis.c: Likewise.
692 * rl78-decode.opc: Likewise.
693 * rl78-decode.c: Regenerate.
694 * rx-decode.opc: Likewise.
695 * rx-decode.c: Regenerate.
697 2012-05-17 Alan Modra <amodra@gmail.com>
699 * ppc_dis.c: Don't include elf/ppc.h.
701 2012-05-16 Meador Inge <meadori@codesourcery.com>
703 * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
706 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
707 Stephane Carrez <stcarrez@nerim.fr>
709 * configure.in: Add S12X and XGATE co-processor support to m68hc11
711 * disassemble.c: Likewise.
712 * configure: Regenerate.
713 * m68hc11-dis.c: Make objdump output more consistent, use hex
714 instead of decimal and use 0x prefix for hex.
715 * m68hc11-opc.c: Add S12X and XGATE opcodes.
717 2012-05-14 James Lemke <jwlemke@codesourcery.com>
719 * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
720 (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
721 (vle_opcd_indices): New array.
722 (lookup_vle): New function.
723 (disassemble_init_powerpc): Revise for second (VLE) opcode table.
724 (print_insn_powerpc): Likewise.
725 * ppc-opc.c: Likewise.
727 2012-05-14 Catherine Moore <clm@codesourcery.com>
728 Maciej W. Rozycki <macro@codesourcery.com>
729 Rhonda Wittels <rhonda@codesourcery.com>
730 Nathan Froyd <froydnj@codesourcery.com>
732 * ppc-opc.c (insert_arx, extract_arx): New functions.
733 (insert_ary, extract_ary): New functions.
734 (insert_li20, extract_li20): New functions.
735 (insert_rx, extract_rx): New functions.
736 (insert_ry, extract_ry): New functions.
737 (insert_sci8, extract_sci8): New functions.
738 (insert_sci8n, extract_sci8n): New functions.
739 (insert_sd4h, extract_sd4h): New functions.
740 (insert_sd4w, extract_sd4w): New functions.
741 (insert_vlesi, extract_vlesi): New functions.
742 (insert_vlensi, extract_vlensi): New functions.
743 (insert_vleui, extract_vleui): New functions.
744 (insert_vleil, extract_vleil): New functions.
745 (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
746 (BI16, BI32, BO32, B8): New.
747 (B15, B24, CRD32, CRS): New.
748 (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
749 (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
750 (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
751 (SH6_MASK): Use PPC_OPSHIFT_INV.
752 (SI8, UI5, OIMM5, UI7, BO16): New.
753 (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
754 (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
756 (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
757 (OPVUP, OPVUP_MASK OPVUP): New
758 (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
759 (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
760 (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
761 (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
762 (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
763 (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
764 (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
765 (SE_IM5, SE_IM5_MASK): New.
766 (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
767 (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
768 (BO32DNZ, BO32DZ): New.
769 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
771 (powerpc_opcodes): Add new VLE instructions. Update existing
772 instruction to include PPCVLE if supported.
773 * ppc-dis.c (ppc_opts): Add vle entry.
774 (get_powerpc_dialect): New function.
775 (powerpc_init_dialect): VLE support.
776 (print_insn_big_powerpc): Call get_powerpc_dialect.
777 (print_insn_little_powerpc): Likewise.
778 (operand_value_powerpc): Handle negative shift counts.
779 (print_insn_powerpc): Handle 2-byte instruction lengths.
781 2012-05-11 Daniel Richard G. <skunk@iskunk.org>
784 * configure.in: Invoke ACX_HEADER_STRING.
785 * configure: Regenerate.
786 * config.in: Regenerate.
787 * sysdep.h: If STRINGS_WITH_STRING is defined then include both
788 string.h and strings.h.
790 2012-05-11 Nick Clifton <nickc@redhat.com>
793 * arm-dis.c (print_insn): Fix detection of instruction mode in
794 files containing multiple executable sections.
796 2012-05-03 Sean Keys <skeys@ipdatasys.com>
798 * Makefile.in, configure: regenerate
799 * disassemble.c (disassembler): Recognize ARCH_XGATE.
800 * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
802 * configure.in: Recognize xgate.
803 * xgate-dis.c, xgate-opc.c: New files for support of xgate
804 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
805 and opcode generation for xgate.
807 2012-04-30 DJ Delorie <dj@redhat.com>
809 * rx-decode.opc (MOV): Do not sign-extend immediates which are
810 already the maximum bit size.
811 * rx-decode.c: Regenerate.
813 2012-04-27 David S. Miller <davem@davemloft.net>
815 * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
816 * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
818 * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
819 * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
821 * sparc-opc.c (CBCOND): New define.
822 (CBCOND_XCC): Likewise.
823 (cbcond): New helper macro.
824 (sparc_opcodes): Add compare-and-branch instructions.
826 * sparc-dis.c (print_insn_sparc): Handle ')'.
827 * sparc-opc.c (sparc_opcodes): Add crypto instructions.
829 * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
830 into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
832 2012-04-12 David S. Miller <davem@davemloft.net>
834 * sparc-dis.c (X_DISP10): Define.
835 (print_insn_sparc): Handle '='.
837 2012-04-01 Mike Frysinger <vapier@gentoo.org>
839 * bfin-dis.c (fmtconst): Replace decimal handling with a single
840 sprintf call and the '*' field width.
842 2012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
844 * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
846 2012-03-16 Alan Modra <amodra@gmail.com>
848 * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
849 (powerpc_opcd_indices): Bump array size.
850 (disassemble_init_powerpc): Set powerpc_opcd_indices entries
851 corresponding to unused opcodes to following entry.
852 (lookup_powerpc): New function, extracted and optimised from..
853 (print_insn_powerpc): ..here.
855 2012-03-15 Alan Modra <amodra@gmail.com>
856 James Lemke <jwlemke@codesourcery.com>
858 * disassemble.c (disassemble_init_for_target): Handle ppc init.
859 * ppc-dis.c (private): New var.
860 (powerpc_init_dialect): Don't return calloc failure, instead use
862 (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
863 (powerpc_opcd_indices): New array.
864 (disassemble_init_powerpc): New function.
865 (print_insn_big_powerpc): Don't init dialect here.
866 (print_insn_little_powerpc): Likewise.
867 (print_insn_powerpc): Start search using powerpc_opcd_indices.
869 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
871 * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
872 * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
873 (PPCVEC2, PPCTMR, E6500): New short names.
874 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
875 mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
876 lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
877 lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
878 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
879 optional operands on sync instruction for E6500 target.
881 2012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
883 * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
885 2012-02-27 Alan Modra <amodra@gmail.com>
887 * mt-dis.c: Regenerate.
889 2012-02-27 Alan Modra <amodra@gmail.com>
891 * v850-opc.c (extract_v8): Rearrange to make it obvious this
892 is the inverse of corresponding insert function.
893 (extract_d22, extract_u9, extract_r4): Likewise.
894 (extract_d9): Correct sign extension.
895 (extract_d16_15): Don't assume "long" is 32 bits, and don't
896 rely on implementation defined behaviour for shift right of
898 (extract_d16_16, extract_d17_16, extract_i9): Likewise.
899 (extract_d23): Likewise, and correct mask.
901 2012-02-27 Alan Modra <amodra@gmail.com>
903 * crx-dis.c (print_arg): Mask constant to 32 bits.
904 * crx-opc.c (cst4_map): Use int array.
906 2012-02-27 Alan Modra <amodra@gmail.com>
908 * arc-dis.c (BITS): Don't use shifts to mask off bits.
909 (FIELDD): Sign extend with xor,sub.
911 2012-02-25 Walter Lee <walt@tilera.com>
913 * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
914 * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
915 TILEPRO_OPC_LW_TLS_SN.
917 2012-02-21 H.J. Lu <hongjiu.lu@intel.com>
919 * i386-opc.h (HLEPrefixNone): New.
920 (HLEPrefixLock): Likewise.
921 (HLEPrefixAny): Likewise.
922 (HLEPrefixRelease): Likewise.
924 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
926 * i386-dis.c (HLE_Fixup1): New.
927 (HLE_Fixup2): Likewise.
928 (HLE_Fixup3): Likewise.
935 (MOD_C6_REG_7): Likewise.
936 (MOD_C7_REG_7): Likewise.
937 (RM_C6_REG_7): Likewise.
938 (RM_C7_REG_7): Likewise.
939 (XACQUIRE_PREFIX): Likewise.
940 (XRELEASE_PREFIX): Likewise.
941 (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
942 cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
943 Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
944 (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
945 not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
946 MOD_C6_REG_7 and MOD_C7_REG_7.
947 (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
948 (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
950 (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
951 (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
953 * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
955 (cpu_flags): Add CpuHLE and CpuRTM.
956 (opcode_modifiers): Add HLEPrefixOk.
958 * i386-opc.h (CpuHLE): New.
960 (HLEPrefixOk): Likewise.
961 (i386_cpu_flags): Add cpuhle and cpurtm.
962 (i386_opcode_modifier): Add hleprefixok.
964 * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
965 add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
966 sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
967 operand. Add xacquire, xrelease, xabort, xbegin, xend and
969 * i386-init.h: Regenerated.
970 * i386-tbl.h: Likewise.
972 2012-01-24 DJ Delorie <dj@redhat.com>
974 * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
975 * rl78-decode.c: Regenerate.
977 2012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
980 * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
982 2012-01-17 Andreas Schwab <schwab@linux-m68k.org>
984 * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
985 register and move them after pmove with PSR/PCSR register.
987 2012-01-13 H.J. Lu <hongjiu.lu@intel.com>
989 * i386-dis.c (mod_table): Add vmfunc.
991 * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
992 (cpu_flags): CpuVMFUNC.
994 * i386-opc.h (CpuVMFUNC): New.
995 (i386_cpu_flags): Add cpuvmfunc.
997 * i386-opc.tbl: Add vmfunc.
998 * i386-init.h: Regenerated.
999 * i386-tbl.h: Likewise.
1001 For older changes see ChangeLog-2011
1007 version-control: never