1 2016-12-23 Tristan Gingold <gingold@adacore.com>
3 * configure: Regenerate.
5 2016-12-23 Tristan Gingold <gingold@adacore.com>
7 * po/opcodes.pot: Regenerate.
9 2016-12-21 Andrew Waterman <andrew@sifive.com>
11 * riscv-opc.c (riscv_opcodes): Reorder jal and call entries.
13 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
15 * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than
16 ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.
17 (print_insn_mips16): Check opcode entries for validity against
18 the ISA level and ASE set selected.
20 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
22 * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
23 `insn' together, with `extend' as the high-order 16 bits.
24 (match_kind): New enum.
25 (print_insn_mips16): Rework for 32-bit instruction matching.
26 Do not dump EXTEND prefixes here.
27 * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
28 Recode `match' and `mask' fields as 32-bit in absolute "jal" and
31 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
33 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
34 than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"
37 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
39 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
40 than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
43 2016-12-20 Andrew Waterman <andrew@sifive.com>
45 * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
48 2016-12-20 Andrew Waterman <andrew@sifive.com>
50 * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as
53 2016-12-20 Andrew Waterman <andrew@sifive.com>
55 * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
58 2016-12-20 Andrew Waterman <andrew@sifive.com>
60 * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
61 XLEN when none is provided.
63 2016-12-20 Andrew Waterman <andrew@sifive.com>
65 * riscv-opc.c: Formatting fixes.
67 2016-12-20 Alan Modra <amodra@gmail.com>
69 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
70 * Makefile.in: Regenerate.
71 * po/POTFILES.in: Regenerate.
73 2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
75 * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
76 Only examine ELF file structures here.
78 2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
80 * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
81 `bfd_mips_elf_get_abiflags' here.
83 2016-12-16 Nick Clifton <nickc@redhat.com>
85 * arm-dis.c (print_insn_thumb32): Fix compile time warning
86 computing value_in_comment.
88 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
90 * mips-dis.c (mips_convert_abiflags_ases): New function.
91 (set_default_mips_dis_options): Also infer ASE flags from ELF
94 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
96 * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
97 header flag interpretation code.
99 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
101 * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
102 `pinfo2' with SP-relative "sd" entries.
104 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
106 * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
109 2016-12-13 Renlin Li <renlin.li@arm.com>
111 * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
113 (operand_general_constraint_met_p): Remove case for CP_REG.
114 (aarch64_print_operand): Print CRn, CRm operand using imm field.
115 * aarch64-tbl.h (QL_SYS): Use CR qualifier.
117 (aarch64_opcode_table): Change CRn, CRm operand class and type.
118 * aarch64-opc-2.c : Regenerate.
119 * aarch64-asm-2.c : Likewise.
120 * aarch64-dis-2.c : Likewise.
122 2016-12-12 Yao Qi <yao.qi@linaro.org>
124 * rx-dis.c: Include <setjmp.h>
125 (struct private): New.
126 (rx_get_byte): Check return value of read_memory_func, and
127 call memory_error_func and OPCODES_SIGLONGJMP on error.
128 (print_insn_rx): Call OPCODES_SIGSETJMP.
130 2016-12-12 Yao Qi <yao.qi@linaro.org>
132 * rl78-dis.c: Include <setjmp.h>.
133 (struct private): New.
134 (rl78_get_byte): Check return value of read_memory_func, and
135 call memory_error_func and OPCODES_SIGLONGJMP on error.
136 (print_insn_rl78_common): Call OPCODES_SIGJMP.
138 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
140 * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
142 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
144 * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
147 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
149 * mips-dis.c (print_insn_mips16): Use a tab rather than a space
150 to separate `extend' and its uninterpreted argument output.
151 Separate hexadecimal halves of undecoded extended instructions
154 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
156 * mips-dis.c (print_mips16_insn_arg): Remove extraneous
157 indentation space across.
159 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
161 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
162 adjustment for PC-relative operations following MIPS16e compact
163 jumps or undefined RR/J(AL)R(C) encodings.
165 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
167 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
168 variable to `reglane_index'.
170 2016-12-08 Luis Machado <lgustavo@codesourcery.com>
172 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
174 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
176 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
178 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
180 * mips16-opc.c (mips16_opcodes): Update comment naming structure
183 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
185 * mips-dis.c (print_mips_disassembler_options): Reformat output.
187 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
189 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
190 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
192 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
194 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
196 2016-12-01 Nick Clifton <nickc@redhat.com>
199 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
202 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
204 * arc-opc.c (insert_ra_chk): New function.
205 (insert_rb_chk): Likewise.
206 (insert_rad): Update text error message.
207 (insert_rcd): Likewise.
208 (insert_rhv2): Likewise.
209 (insert_r0): Likewise.
210 (insert_r1): Likewise.
211 (insert_r2): Likewise.
212 (insert_r3): Likewise.
213 (insert_sp): Likewise.
214 (insert_gp): Likewise.
215 (insert_pcl): Likewise.
216 (insert_blink): Likewise.
217 (insert_ilink1): Likewise.
218 (insert_ilink2): Likewise.
219 (insert_ras): Likewise.
220 (insert_rbs): Likewise.
221 (insert_rcs): Likewise.
222 (insert_simm3s): Likewise.
223 (insert_rrange): Likewise.
224 (insert_fpel): Likewise.
225 (insert_blinkel): Likewise.
226 (insert_pcel): Likewise.
227 (insert_nps_3bit_dst): Likewise.
228 (insert_nps_3bit_dst_short): Likewise.
229 (insert_nps_3bit_src2_short): Likewise.
230 (insert_nps_bitop_size_2b): Likewise.
231 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
236 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
237 * arc-tbl.h (div, divu): All instructions are DIVREM class.
238 Change first insn argument to check for LP_COUNT usage.
240 (ld, ldd): All instructions are LOAD class. Change first insn
241 argument to check for LP_COUNT usage.
242 (st, std): All instructions are STORE class.
243 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
244 Change first insn argument to check for LP_COUNT usage.
245 (mov): All instructions are MOVE class. Change first insn
246 argument to check for LP_COUNT usage.
248 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
250 * arc-dis.c (is_compatible_p): Remove function.
251 (skip_this_opcode): Don't add any decoding class to decode list.
253 (find_format_from_table): Go through all opcodes, and warn if we
254 use a guessed mnemonic.
256 2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
257 Amit Pawar <amit.pawar@amd.com>
260 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
263 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
265 * configure: Regenerate.
267 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
269 * sparc-opc.c (HWS_V8): Definition moved from
270 gas/config/tc-sparc.c.
280 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
283 2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
285 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
288 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
290 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
291 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
292 (aarch64_opcode_table): Add fcmla and fcadd.
293 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
294 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
295 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
296 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
297 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
298 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
299 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
300 (operand_general_constraint_met_p): Rotate and index range check.
301 (aarch64_print_operand): Handle rotate operand.
302 * aarch64-asm-2.c: Regenerate.
303 * aarch64-dis-2.c: Likewise.
304 * aarch64-opc-2.c: Likewise.
306 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
308 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
309 * aarch64-asm-2.c: Regenerate.
310 * aarch64-dis-2.c: Regenerate.
311 * aarch64-opc-2.c: Regenerate.
313 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
315 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
316 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
317 * aarch64-asm-2.c: Regenerate.
318 * aarch64-dis-2.c: Regenerate.
319 * aarch64-opc-2.c: Regenerate.
321 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
323 * aarch64-tbl.h (QL_X1NIL): New.
324 (arch64_opcode_table): Add ldraa, ldrab.
325 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
326 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
327 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
328 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
329 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
330 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
331 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
332 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
333 (aarch64_print_operand): Likewise.
334 * aarch64-asm-2.c: Regenerate.
335 * aarch64-dis-2.c: Regenerate.
336 * aarch64-opc-2.c: Regenerate.
338 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
340 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
341 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
342 * aarch64-asm-2.c: Regenerate.
343 * aarch64-dis-2.c: Regenerate.
344 * aarch64-opc-2.c: Regenerate.
346 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
348 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
349 (AARCH64_OPERANDS): Add Rm_SP.
350 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
351 * aarch64-asm-2.c: Regenerate.
352 * aarch64-dis-2.c: Regenerate.
353 * aarch64-opc-2.c: Regenerate.
355 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
357 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
358 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
359 autdzb, xpaci, xpacd.
360 * aarch64-asm-2.c: Regenerate.
361 * aarch64-dis-2.c: Regenerate.
362 * aarch64-opc-2.c: Regenerate.
364 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
366 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
367 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
368 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
369 (aarch64_sys_reg_supported_p): Add feature test for new registers.
371 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
373 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
374 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
375 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
377 * aarch64-asm-2.c: Regenerate.
378 * aarch64-dis-2.c: Regenerate.
380 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
382 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
384 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
387 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
388 * i386-dis.c (EdqwS): Removed.
389 (dqw_swap_mode): Likewise.
390 (intel_operand_size): Don't check dqw_swap_mode.
391 (OP_E_register): Likewise.
392 (OP_E_memory): Likewise.
395 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
396 * i386-tbl.h: Regerated.
398 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
400 * i386-opc.tbl: Merge AVX512F vmovq.
401 * i386-tbl.h: Regerated.
403 2016-11-08 H.J. Lu <hongjiu.lu@intel.com>
406 * i386-dis.c (THREE_BYTE_0F7A): Removed.
407 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
408 (three_byte_table): Remove THREE_BYTE_0F7A.
410 2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
413 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
414 (FGRPd9_4): Replace 1 with 2.
415 (FGRPd9_5): Replace 2 with 3.
416 (FGRPd9_6): Replace 3 with 4.
417 (FGRPd9_7): Replace 4 with 5.
418 (FGRPda_5): Replace 5 with 6.
419 (FGRPdb_4): Replace 6 with 7.
420 (FGRPde_3): Replace 7 with 8.
421 (FGRPdf_4): Replace 8 with 9.
422 (fgrps): Add an entry for Bad_Opcode.
424 2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
426 * arc-opc.c (arc_flag_operands): Add F_DI14.
427 (arc_flag_classes): Add C_DI14.
428 * arc-nps400-tbl.h: Add new exc instructions.
430 2016-11-03 Graham Markall <graham.markall@embecosm.com>
432 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
434 * arc-nps-400-tbl.h: Add dcmac instruction.
435 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
436 (insert_nps_rbdouble_64): Added.
437 (extract_nps_rbdouble_64): Added.
438 (insert_nps_proto_size): Added.
439 (extract_nps_proto_size): Added.
441 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
443 * arc-dis.c (struct arc_operand_iterator): Remove all fields
444 relating to long instruction processing, add new limm field.
445 (OPCODE): Rename to...
446 (OPCODE_32BIT_INSN): ...this.
448 (skip_this_opcode): Handle different instruction lengths, update
450 (special_flag_p): Update parameter type.
451 (find_format_from_table): Update for more instruction lengths.
452 (find_format_long_instructions): Delete.
453 (find_format): Update for more instruction lengths.
454 (arc_insn_length): Likewise.
455 (extract_operand_value): Update for more instruction lengths.
456 (operand_iterator_next): Remove code relating to long
458 (arc_opcode_to_insn_type): New function.
459 (print_insn_arc):Update for more instructions lengths.
460 * arc-ext.c (extInstruction_t): Change argument type.
461 * arc-ext.h (extInstruction_t): Change argument type.
462 * arc-fxi.h: Change type unsigned to unsigned long long
463 extensively throughout.
464 * arc-nps400-tbl.h: Add long instructions taken from
465 arc_long_opcodes table in arc-opc.c.
466 * arc-opc.c: Update parameter types on insert/extract handlers.
467 (arc_long_opcodes): Delete.
468 (arc_num_long_opcodes): Delete.
469 (arc_opcode_len): Update for more instruction lengths.
471 2016-11-03 Graham Markall <graham.markall@embecosm.com>
473 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
475 2016-11-03 Graham Markall <graham.markall@embecosm.com>
477 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
479 (find_format_long_instructions): Likewise.
480 * arc-opc.c (arc_opcode_len): New function.
482 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
484 * arc-nps400-tbl.h: Fix some instruction masks.
486 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
488 * i386-dis.c (REG_82): Removed.
489 (X86_64_82_REG_0): Likewise.
490 (X86_64_82_REG_1): Likewise.
491 (X86_64_82_REG_2): Likewise.
492 (X86_64_82_REG_3): Likewise.
493 (X86_64_82_REG_4): Likewise.
494 (X86_64_82_REG_5): Likewise.
495 (X86_64_82_REG_6): Likewise.
496 (X86_64_82_REG_7): Likewise.
498 (dis386): Use X86_64_82 instead of REG_82.
499 (reg_table): Remove REG_82.
500 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
501 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
502 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
505 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
508 * i386-dis.c (REG_82): New.
509 (X86_64_82_REG_0): Likewise.
510 (X86_64_82_REG_1): Likewise.
511 (X86_64_82_REG_2): Likewise.
512 (X86_64_82_REG_3): Likewise.
513 (X86_64_82_REG_4): Likewise.
514 (X86_64_82_REG_5): Likewise.
515 (X86_64_82_REG_6): Likewise.
516 (X86_64_82_REG_7): Likewise.
517 (dis386): Use REG_82.
518 (reg_table): Add REG_82.
519 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
520 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
521 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
523 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
525 * i386-dis.c (REG_82): Renamed to ...
528 (reg_table): Likewise.
530 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
532 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
533 * i386-dis-evex.h (evex_table): Updated.
534 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
535 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
536 (cpu_flags): Add CpuAVX512_4VNNIW.
537 * i386-opc.h (enum): (AVX512_4VNNIW): New.
538 (i386_cpu_flags): Add cpuavx512_4vnniw.
539 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
540 * i386-init.h: Regenerate.
543 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
545 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
546 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
547 * i386-dis-evex.h (evex_table): Updated.
548 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
549 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
550 (cpu_flags): Add CpuAVX512_4FMAPS.
551 (opcode_modifiers): Add ImplicitQuadGroup modifier.
552 * i386-opc.h (AVX512_4FMAP): New.
553 (i386_cpu_flags): Add cpuavx512_4fmaps.
554 (ImplicitQuadGroup): New.
555 (i386_opcode_modifier): Add implicitquadgroup.
556 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
557 * i386-init.h: Regenerate.
560 2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
561 Andrew Waterman <andrew@sifive.com>
563 Add support for RISC-V architecture.
564 * configure.ac: Add entry for bfd_riscv_arch.
565 * configure: Regenerate.
566 * disassemble.c (disassembler): Add support for riscv.
567 (disassembler_usage): Likewise.
568 * riscv-dis.c: New file.
569 * riscv-opc.c: New file.
571 2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
573 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
574 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
575 (rm_table): Update the RM_0FAE_REG_7 entry.
576 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
577 (cpu_flags): Remove CpuPCOMMIT.
578 * i386-opc.h (CpuPCOMMIT): Removed.
579 (i386_cpu_flags): Remove cpupcommit.
580 * i386-opc.tbl: Remove pcommit.
581 * i386-init.h: Regenerated.
582 * i386-tbl.h: Likewise.
584 2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
587 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
588 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
589 32-bit mode. Don't check vex.register_specifier in 32-bit
591 (OP_VEX): Check for invalid mask registers.
593 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
596 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
599 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
602 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
604 2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
606 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
607 local variable to `index_regno'.
609 2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
611 * arc-tbl.h: Removed any "inv.+" instructions from the table.
613 2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
615 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
618 2016-10-11 Jiong Wang <jiong.wang@arm.com>
621 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
623 2016-10-07 Jiong Wang <jiong.wang@arm.com>
626 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
629 2016-10-07 Alan Modra <amodra@gmail.com>
631 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
633 2016-10-06 Alan Modra <amodra@gmail.com>
635 * aarch64-opc.c: Spell fall through comments consistently.
636 * i386-dis.c: Likewise.
637 * aarch64-dis.c: Add missing fall through comments.
638 * aarch64-opc.c: Likewise.
639 * arc-dis.c: Likewise.
640 * arm-dis.c: Likewise.
641 * i386-dis.c: Likewise.
642 * m68k-dis.c: Likewise.
643 * mep-asm.c: Likewise.
644 * ns32k-dis.c: Likewise.
645 * sh-dis.c: Likewise.
646 * tic4x-dis.c: Likewise.
647 * tic6x-dis.c: Likewise.
648 * vax-dis.c: Likewise.
650 2016-10-06 Alan Modra <amodra@gmail.com>
652 * arc-ext.c (create_map): Add missing break.
653 * msp430-decode.opc (encode_as): Likewise.
654 * msp430-decode.c: Regenerate.
656 2016-10-06 Alan Modra <amodra@gmail.com>
658 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
659 * crx-dis.c (print_insn_crx): Likewise.
661 2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
664 * i386-dis.c (putop): Don't assign alt twice.
666 2016-09-29 Jiong Wang <jiong.wang@arm.com>
669 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
671 2016-09-29 Alan Modra <amodra@gmail.com>
673 * ppc-opc.c (L): Make compulsory.
674 (LOPT): New, optional form of L.
675 (HTM_R): Define as LOPT.
677 (L32OPT): New, optional for 32-bit L.
678 (L2OPT): New, 2-bit L for dcbf.
681 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
682 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
684 <tlbiel, tlbie>: Use LOPT.
685 <wclr, wclrall>: Use L2.
687 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
689 * Makefile.in: Regenerate.
690 * configure: Likewise.
692 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
694 * arc-ext-tbl.h (EXTINSN2OPF): Define.
695 (EXTINSN2OP): Use EXTINSN2OPF.
696 (bspeekm, bspop, modapp): New extension instructions.
697 * arc-opc.c (F_DNZ_ND): Define.
702 * arc-tbl.h (dbnz): New instruction.
703 (prealloc): Allow it for ARC EM.
706 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
708 * aarch64-opc.c (print_immediate_offset_address): Print spaces
709 after commas in addresses.
710 (aarch64_print_operand): Likewise.
712 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
714 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
715 rather than "should be" or "expected to be" in error messages.
717 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
719 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
720 (print_mnemonic_name): ...here.
721 (print_comment): New function.
722 (print_aarch64_insn): Call it.
723 * aarch64-opc.c (aarch64_conds): Add SVE names.
724 (aarch64_print_operand): Print alternative condition names in
727 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
729 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
730 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
731 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
732 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
733 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
734 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
735 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
736 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
737 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
738 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
739 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
740 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
741 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
742 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
743 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
744 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
745 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
746 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
747 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
748 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
749 (OP_SVE_XWU, OP_SVE_XXU): New macros.
750 (aarch64_feature_sve): New variable.
752 (_SVE_INSN): Likewise.
753 (aarch64_opcode_table): Add SVE instructions.
754 * aarch64-opc.h (extract_fields): Declare.
755 * aarch64-opc-2.c: Regenerate.
756 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
757 * aarch64-asm-2.c: Regenerate.
758 * aarch64-dis.c (extract_fields): Make global.
759 (do_misc_decoding): Handle the new SVE aarch64_ops.
760 * aarch64-dis-2.c: Regenerate.
762 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
764 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
765 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
767 * aarch64-opc.c (fields): Add corresponding entries.
768 * aarch64-asm.c (aarch64_get_variant): New function.
769 (aarch64_encode_variant_using_iclass): Likewise.
770 (aarch64_opcode_encode): Call it.
771 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
772 (aarch64_opcode_decode): Call it.
774 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
776 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
777 and FP register operands.
778 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
779 (FLD_SVE_Vn): New aarch64_field_kinds.
780 * aarch64-opc.c (fields): Add corresponding entries.
781 (aarch64_print_operand): Handle the new SVE core and FP register
783 * aarch64-opc-2.c: Regenerate.
784 * aarch64-asm-2.c: Likewise.
785 * aarch64-dis-2.c: Likewise.
787 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
789 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
791 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
792 * aarch64-opc.c (fields): Add corresponding entry.
793 (operand_general_constraint_met_p): Handle the new SVE FP immediate
795 (aarch64_print_operand): Likewise.
796 * aarch64-opc-2.c: Regenerate.
797 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
798 (ins_sve_float_zero_one): New inserters.
799 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
800 (aarch64_ins_sve_float_half_two): Likewise.
801 (aarch64_ins_sve_float_zero_one): Likewise.
802 * aarch64-asm-2.c: Regenerate.
803 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
804 (ext_sve_float_zero_one): New extractors.
805 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
806 (aarch64_ext_sve_float_half_two): Likewise.
807 (aarch64_ext_sve_float_zero_one): Likewise.
808 * aarch64-dis-2.c: Regenerate.
810 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
812 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
813 integer immediate operands.
814 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
815 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
816 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
817 * aarch64-opc.c (fields): Add corresponding entries.
818 (operand_general_constraint_met_p): Handle the new SVE integer
820 (aarch64_print_operand): Likewise.
821 (aarch64_sve_dupm_mov_immediate_p): New function.
822 * aarch64-opc-2.c: Regenerate.
823 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
824 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
825 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
826 (aarch64_ins_limm): ...here.
827 (aarch64_ins_inv_limm): New function.
828 (aarch64_ins_sve_aimm): Likewise.
829 (aarch64_ins_sve_asimm): Likewise.
830 (aarch64_ins_sve_limm_mov): Likewise.
831 (aarch64_ins_sve_shlimm): Likewise.
832 (aarch64_ins_sve_shrimm): Likewise.
833 * aarch64-asm-2.c: Regenerate.
834 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
835 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
836 * aarch64-dis.c (decode_limm): New function, split out from...
837 (aarch64_ext_limm): ...here.
838 (aarch64_ext_inv_limm): New function.
839 (decode_sve_aimm): Likewise.
840 (aarch64_ext_sve_aimm): Likewise.
841 (aarch64_ext_sve_asimm): Likewise.
842 (aarch64_ext_sve_limm_mov): Likewise.
843 (aarch64_top_bit): Likewise.
844 (aarch64_ext_sve_shlimm): Likewise.
845 (aarch64_ext_sve_shrimm): Likewise.
846 * aarch64-dis-2.c: Regenerate.
848 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
850 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
852 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
853 the AARCH64_MOD_MUL_VL entry.
854 (value_aligned_p): Cope with non-power-of-two alignments.
855 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
856 (print_immediate_offset_address): Likewise.
857 (aarch64_print_operand): Likewise.
858 * aarch64-opc-2.c: Regenerate.
859 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
860 (ins_sve_addr_ri_s9xvl): New inserters.
861 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
862 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
863 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
864 * aarch64-asm-2.c: Regenerate.
865 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
866 (ext_sve_addr_ri_s9xvl): New extractors.
867 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
868 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
869 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
870 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
871 * aarch64-dis-2.c: Regenerate.
873 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
875 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
877 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
878 (FLD_SVE_xs_22): New aarch64_field_kinds.
879 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
880 (get_operand_specific_data): New function.
881 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
882 FLD_SVE_xs_14 and FLD_SVE_xs_22.
883 (operand_general_constraint_met_p): Handle the new SVE address
885 (sve_reg): New array.
886 (get_addr_sve_reg_name): New function.
887 (aarch64_print_operand): Handle the new SVE address operands.
888 * aarch64-opc-2.c: Regenerate.
889 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
890 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
891 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
892 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
893 (aarch64_ins_sve_addr_rr_lsl): Likewise.
894 (aarch64_ins_sve_addr_rz_xtw): Likewise.
895 (aarch64_ins_sve_addr_zi_u5): Likewise.
896 (aarch64_ins_sve_addr_zz): Likewise.
897 (aarch64_ins_sve_addr_zz_lsl): Likewise.
898 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
899 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
900 * aarch64-asm-2.c: Regenerate.
901 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
902 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
903 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
904 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
905 (aarch64_ext_sve_addr_ri_u6): Likewise.
906 (aarch64_ext_sve_addr_rr_lsl): Likewise.
907 (aarch64_ext_sve_addr_rz_xtw): Likewise.
908 (aarch64_ext_sve_addr_zi_u5): Likewise.
909 (aarch64_ext_sve_addr_zz): Likewise.
910 (aarch64_ext_sve_addr_zz_lsl): Likewise.
911 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
912 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
913 * aarch64-dis-2.c: Regenerate.
915 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
917 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
918 AARCH64_OPND_SVE_PATTERN_SCALED.
919 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
920 * aarch64-opc.c (fields): Add a corresponding entry.
921 (set_multiplier_out_of_range_error): New function.
922 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
923 (operand_general_constraint_met_p): Handle
924 AARCH64_OPND_SVE_PATTERN_SCALED.
925 (print_register_offset_address): Use PRIi64 to print the
927 (aarch64_print_operand): Likewise. Handle
928 AARCH64_OPND_SVE_PATTERN_SCALED.
929 * aarch64-opc-2.c: Regenerate.
930 * aarch64-asm.h (ins_sve_scale): New inserter.
931 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
932 * aarch64-asm-2.c: Regenerate.
933 * aarch64-dis.h (ext_sve_scale): New inserter.
934 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
935 * aarch64-dis-2.c: Regenerate.
937 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
939 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
940 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
941 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
942 (FLD_SVE_prfop): Likewise.
943 * aarch64-opc.c: Include libiberty.h.
944 (aarch64_sve_pattern_array): New variable.
945 (aarch64_sve_prfop_array): Likewise.
946 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
947 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
948 AARCH64_OPND_SVE_PRFOP.
949 * aarch64-asm-2.c: Regenerate.
950 * aarch64-dis-2.c: Likewise.
951 * aarch64-opc-2.c: Likewise.
953 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
955 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
956 AARCH64_OPND_QLF_P_[ZM].
957 (aarch64_print_operand): Print /z and /m where appropriate.
959 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
961 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
962 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
963 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
964 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
965 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
966 * aarch64-opc.c (fields): Add corresponding entries here.
967 (operand_general_constraint_met_p): Check that SVE register lists
968 have the correct length. Check the ranges of SVE index registers.
969 Check for cases where p8-p15 are used in 3-bit predicate fields.
970 (aarch64_print_operand): Handle the new SVE operands.
971 * aarch64-opc-2.c: Regenerate.
972 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
973 * aarch64-asm.c (aarch64_ins_sve_index): New function.
974 (aarch64_ins_sve_reglist): Likewise.
975 * aarch64-asm-2.c: Regenerate.
976 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
977 * aarch64-dis.c (aarch64_ext_sve_index): New function.
978 (aarch64_ext_sve_reglist): Likewise.
979 * aarch64-dis-2.c: Regenerate.
981 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
983 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
984 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
985 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
986 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
989 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
991 * aarch64-opc.c (get_offset_int_reg_name): New function.
992 (print_immediate_offset_address): Likewise.
993 (print_register_offset_address): Take the base and offset
994 registers as parameters.
995 (aarch64_print_operand): Update caller accordingly. Use
996 print_immediate_offset_address.
998 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1000 * aarch64-opc.c (BANK): New macro.
1001 (R32, R64): Take a register number as argument
1002 (int_reg): Use BANK.
1004 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1006 * aarch64-opc.c (print_register_list): Add a prefix parameter.
1007 (aarch64_print_operand): Update accordingly.
1009 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1011 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
1013 * aarch64-asm.h (ins_fpimm): New inserter.
1014 * aarch64-asm.c (aarch64_ins_fpimm): New function.
1015 * aarch64-asm-2.c: Regenerate.
1016 * aarch64-dis.h (ext_fpimm): New extractor.
1017 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
1018 (aarch64_ext_fpimm): New function.
1019 * aarch64-dis-2.c: Regenerate.
1021 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1023 * aarch64-asm.c: Include libiberty.h.
1024 (insert_fields): New function.
1025 (aarch64_ins_imm): Use it.
1026 * aarch64-dis.c (extract_fields): New function.
1027 (aarch64_ext_imm): Use it.
1029 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1031 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
1032 with an esize parameter.
1033 (operand_general_constraint_met_p): Update accordingly.
1034 Fix misindented code.
1035 * aarch64-asm.c (aarch64_ins_limm): Update call to
1036 aarch64_logical_immediate_p.
1038 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1040 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
1042 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1044 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
1046 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
1048 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
1050 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
1052 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
1053 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
1054 xor3>: Delete mnemonics.
1055 <cp_abort>: Rename mnemonic from ...
1056 <cpabort>: ...to this.
1057 <setb>: Change to a X form instruction.
1058 <sync>: Change to 1 operand form.
1059 <copy>: Delete mnemonic.
1060 <copy_first>: Rename mnemonic from ...
1062 <paste, paste.>: Delete mnemonics.
1063 <paste_last>: Rename mnemonic from ...
1064 <paste.>: ...to this.
1066 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
1068 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
1070 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1072 * s390-mkopc.c (main): Support alternate arch strings.
1074 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
1076 * s390-opc.txt: Fix kmctr instruction type.
1078 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
1080 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1081 * i386-init.h: Regenerated.
1083 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
1085 * opcodes/arc-dis.c (print_insn_arc): Changed.
1087 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
1089 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1092 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
1094 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
1095 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1096 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1098 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
1100 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1101 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1102 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1103 PREFIX_MOD_3_0FAE_REG_4.
1104 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1105 PREFIX_MOD_3_0FAE_REG_4.
1106 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1107 (cpu_flags): Add CpuPTWRITE.
1108 * i386-opc.h (CpuPTWRITE): New.
1109 (i386_cpu_flags): Add cpuptwrite.
1110 * i386-opc.tbl: Add ptwrite instruction.
1111 * i386-init.h: Regenerated.
1112 * i386-tbl.h: Likewise.
1114 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
1116 * arc-dis.h: Wrap around in extern "C".
1118 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1120 * aarch64-tbl.h (V8_2_INSN): New macro.
1121 (aarch64_opcode_table): Use it.
1123 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1125 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1126 CORE_INSN, __FP_INSN and SIMD_INSN.
1128 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1130 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1131 (aarch64_opcode_table): Update uses accordingly.
1133 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
1134 Kwok Cheung Yeung <kcy@codesourcery.com>
1137 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1138 'e_cmplwi' to 'e_cmpli' instead.
1139 (OPVUPRT, OPVUPRT_MASK): Define.
1140 (powerpc_opcodes): Add E200Z4 insns.
1141 (vle_opcodes): Add context save/restore insns.
1143 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
1145 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1146 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1149 2016-07-27 Graham Markall <graham.markall@embecosm.com>
1151 * arc-nps400-tbl.h: Change block comments to GNU format.
1152 * arc-dis.c: Add new globals addrtypenames,
1153 addrtypenames_max, and addtypeunknown.
1154 (get_addrtype): New function.
1155 (print_insn_arc): Print colons and address types when
1157 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1158 define insert and extract functions for all address types.
1159 (arc_operands): Add operands for colon and all address
1161 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1162 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1163 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1164 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1165 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1166 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1168 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
1170 * configure: Regenerated.
1172 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1174 * arc-dis.c (skipclass): New structure.
1175 (decodelist): New variable.
1176 (is_compatible_p): New function.
1177 (new_element): Likewise.
1178 (skip_class_p): Likewise.
1179 (find_format_from_table): Use skip_class_p function.
1180 (find_format): Decode first the extension instructions.
1181 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1183 (parse_option): New function.
1184 (parse_disassembler_options): Likewise.
1185 (print_arc_disassembler_options): Likewise.
1186 (print_insn_arc): Use parse_disassembler_options function. Proper
1187 select ARCv2 cpu variant.
1188 * disassemble.c (disassembler_usage): Add ARC disassembler
1191 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1193 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1194 annotation from the "nal" entry and reorder it beyond "bltzal".
1196 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1198 * sparc-opc.c (ldtxa): New macro.
1199 (sparc_opcodes): Use the macro defined above to add entries for
1200 the LDTXA instructions.
1201 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1204 2016-07-07 James Bowman <james.bowman@ftdichip.com>
1206 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1209 2016-07-01 Jan Beulich <jbeulich@suse.com>
1211 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1212 (movzb): Adjust to cover all permitted suffixes.
1214 * i386-tbl.h: Re-generate.
1216 2016-07-01 Jan Beulich <jbeulich@suse.com>
1218 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1219 (lgdt): Remove Tbyte from non-64-bit variant.
1220 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1221 xsaves64, xsavec64): Remove Disp16.
1222 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1223 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1225 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1226 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1227 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1229 * i386-tbl.h: Re-generate.
1231 2016-07-01 Jan Beulich <jbeulich@suse.com>
1233 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1234 * i386-tbl.h: Re-generate.
1236 2016-06-30 Yao Qi <yao.qi@linaro.org>
1238 * arm-dis.c (print_insn): Fix typo in comment.
1240 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1242 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1243 range of ldst_elemlist operands.
1244 (print_register_list): Use PRIi64 to print the index.
1245 (aarch64_print_operand): Likewise.
1247 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1249 * mcore-opc.h: Remove sentinal.
1250 * mcore-dis.c (print_insn_mcore): Adjust.
1252 2016-06-23 Graham Markall <graham.markall@embecosm.com>
1254 * arc-opc.c: Correct description of availability of NPS400
1257 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1259 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1260 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1261 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1262 xor3>: New mnemonics.
1263 <setb>: Change to a VX form instruction.
1264 (insert_sh6): Add support for rldixor.
1265 (extract_sh6): Likewise.
1267 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1269 * arc-ext.h: Wrap in extern C.
1271 2016-06-21 Graham Markall <graham.markall@embecosm.com>
1273 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1274 Use same method for determining instruction length on ARC700 and
1276 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1277 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1278 with the NPS400 subclass.
1279 * arc-opc.c: Likewise.
1281 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1283 * sparc-opc.c (rdasr): New macro.
1289 (sparc_opcodes): Use the macros above to fix and expand the
1290 definition of read/write instructions from/to
1291 asr/privileged/hyperprivileged instructions.
1292 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1293 %hva_mask_nz. Prefer softint_set and softint_clear over
1294 set_softint and clear_softint.
1295 (print_insn_sparc): Support %ver in Rd.
1297 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1299 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1300 architecture according to the hardware capabilities they require.
1302 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1304 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1305 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1306 bfd_mach_sparc_v9{c,d,e,v,m}.
1307 * sparc-opc.c (MASK_V9C): Define.
1308 (MASK_V9D): Likewise.
1309 (MASK_V9E): Likewise.
1310 (MASK_V9V): Likewise.
1311 (MASK_V9M): Likewise.
1312 (v6): Add MASK_V9{C,D,E,V,M}.
1313 (v6notlet): Likewise.
1317 (v9andleon): Likewise.
1325 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1327 2016-06-15 Nick Clifton <nickc@redhat.com>
1329 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1330 constants to match expected behaviour.
1331 (nds32_parse_opcode): Likewise. Also for whitespace.
1333 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1335 * arc-opc.c (extract_rhv1): Extract value from insn.
1337 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1339 * arc-nps400-tbl.h: Add ldbit instruction.
1340 * arc-opc.c: Add flag classes required for ldbit.
1342 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1344 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1345 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1346 support the above instructions.
1348 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1350 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1351 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1352 csma, cbba, zncv, and hofs.
1353 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1354 support the above instructions.
1356 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1358 * arc-nps400-tbl.h: Add andab and orab instructions.
1360 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1362 * arc-nps400-tbl.h: Add addl-like instructions.
1364 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1366 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1368 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1370 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1373 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1375 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1377 (init_disasm): Handle new command line option "insnlength".
1378 (print_s390_disassembler_options): Mention new option in help
1380 (print_insn_s390): Use the encoded insn length when dumping
1381 unknown instructions.
1383 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1385 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1386 to the address and set as symbol address for LDS/ STS immediate operands.
1388 2016-06-07 Alan Modra <amodra@gmail.com>
1390 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1391 cpu for "vle" to e500.
1392 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1393 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1394 (PPCNONE): Delete, substitute throughout.
1395 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1396 except for major opcode 4 and 31.
1397 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1399 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1401 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1402 ARM_EXT_RAS in relevant entries.
1404 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1407 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1410 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1413 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1414 (indir_v_mode): New.
1415 Add comments for '&'.
1416 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1417 (putop): Handle '&'.
1418 (intel_operand_size): Handle indir_v_mode.
1419 (OP_E_register): Likewise.
1420 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1421 64-bit indirect call/jmp for AMD64.
1422 * i386-tbl.h: Regenerated
1424 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1426 * arc-dis.c (struct arc_operand_iterator): New structure.
1427 (find_format_from_table): All the old content from find_format,
1428 with some minor adjustments, and parameter renaming.
1429 (find_format_long_instructions): New function.
1430 (find_format): Rewritten.
1431 (arc_insn_length): Add LSB parameter.
1432 (extract_operand_value): New function.
1433 (operand_iterator_next): New function.
1434 (print_insn_arc): Use new functions to find opcode, and iterator
1436 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1437 (extract_nps_3bit_dst_short): New function.
1438 (insert_nps_3bit_src2_short): New function.
1439 (extract_nps_3bit_src2_short): New function.
1440 (insert_nps_bitop1_size): New function.
1441 (extract_nps_bitop1_size): New function.
1442 (insert_nps_bitop2_size): New function.
1443 (extract_nps_bitop2_size): New function.
1444 (insert_nps_bitop_mod4_msb): New function.
1445 (extract_nps_bitop_mod4_msb): New function.
1446 (insert_nps_bitop_mod4_lsb): New function.
1447 (extract_nps_bitop_mod4_lsb): New function.
1448 (insert_nps_bitop_dst_pos3_pos4): New function.
1449 (extract_nps_bitop_dst_pos3_pos4): New function.
1450 (insert_nps_bitop_ins_ext): New function.
1451 (extract_nps_bitop_ins_ext): New function.
1452 (arc_operands): Add new operands.
1453 (arc_long_opcodes): New global array.
1454 (arc_num_long_opcodes): New global.
1455 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1457 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1459 * nds32-asm.h: Add extern "C".
1460 * sh-opc.h: Likewise.
1462 2016-06-01 Graham Markall <graham.markall@embecosm.com>
1464 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1465 0,b,limm to the rflt instruction.
1467 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1469 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1472 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1475 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1476 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1477 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1478 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1479 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1480 * i386-init.h: Regenerated.
1482 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1485 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1486 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1487 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1488 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1489 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1490 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1491 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1492 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1493 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1494 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1495 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1496 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1497 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1498 CpuRegMask for AVX512.
1499 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1501 (set_bitfield_from_cpu_flag_init): New function.
1502 (set_bitfield): Remove const on f. Call
1503 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1504 * i386-opc.h (CpuRegMMX): New.
1505 (CpuRegXMM): Likewise.
1506 (CpuRegYMM): Likewise.
1507 (CpuRegZMM): Likewise.
1508 (CpuRegMask): Likewise.
1509 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1511 * i386-init.h: Regenerated.
1512 * i386-tbl.h: Likewise.
1514 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1517 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1518 (opcode_modifiers): Add AMD64 and Intel64.
1519 (main): Properly verify CpuMax.
1520 * i386-opc.h (CpuAMD64): Removed.
1521 (CpuIntel64): Likewise.
1522 (CpuMax): Set to CpuNo64.
1523 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1525 (Intel64): Likewise.
1526 (i386_opcode_modifier): Add amd64 and intel64.
1527 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1529 * i386-init.h: Regenerated.
1530 * i386-tbl.h: Likewise.
1532 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1535 * i386-gen.c (main): Fail if CpuMax is incorrect.
1536 * i386-opc.h (CpuMax): Set to CpuIntel64.
1537 * i386-tbl.h: Regenerated.
1539 2016-05-27 Nick Clifton <nickc@redhat.com>
1542 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1543 (msp430dis_opcode_unsigned): New function.
1544 (msp430dis_opcode_signed): New function.
1545 (msp430_singleoperand): Use the new opcode reading functions.
1546 Only disassenmble bytes if they were successfully read.
1547 (msp430_doubleoperand): Likewise.
1548 (msp430_branchinstr): Likewise.
1549 (msp430x_callx_instr): Likewise.
1550 (print_insn_msp430): Check that it is safe to read bytes before
1551 attempting disassembly. Use the new opcode reading functions.
1553 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1555 * ppc-opc.c (CY): New define. Document it.
1556 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1558 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1560 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1561 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1562 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1563 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1565 * i386-init.h: Regenerated.
1567 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1570 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1571 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1572 * i386-init.h: Regenerated.
1574 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1576 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1577 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1578 * i386-init.h: Regenerated.
1580 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1582 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1584 (print_insn_arc): Set insn_type information.
1585 * arc-opc.c (C_CC): Add F_CLASS_COND.
1586 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1587 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1588 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1589 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1590 (brne, brne_s, jeq_s, jne_s): Likewise.
1592 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1594 * arc-tbl.h (neg): New instruction variant.
1596 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1598 * arc-dis.c (find_format, find_format, get_auxreg)
1599 (print_insn_arc): Changed.
1600 * arc-ext.h (INSERT_XOP): Likewise.
1602 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1604 * tic54x-dis.c (sprint_mmr): Adjust.
1605 * tic54x-opc.c: Likewise.
1607 2016-05-19 Alan Modra <amodra@gmail.com>
1609 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1611 2016-05-19 Alan Modra <amodra@gmail.com>
1613 * ppc-opc.c: Formatting.
1614 (NSISIGNOPT): Define.
1615 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1617 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1619 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1620 replacing references to `micromips_ase' throughout.
1621 (_print_insn_mips): Don't use file-level microMIPS annotation to
1622 determine the disassembly mode with the symbol table.
1624 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1626 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1628 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1630 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1632 * mips-opc.c (D34): New macro.
1633 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1635 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1637 * i386-dis.c (prefix_table): Add RDPID instruction.
1638 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1639 (cpu_flags): Add RDPID bitfield.
1640 * i386-opc.h (enum): Add RDPID element.
1641 (i386_cpu_flags): Add RDPID field.
1642 * i386-opc.tbl: Add RDPID instruction.
1643 * i386-init.h: Regenerate.
1644 * i386-tbl.h: Regenerate.
1646 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1648 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1649 branch type of a symbol.
1650 (print_insn): Likewise.
1652 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1654 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1655 Mainline Security Extensions instructions.
1656 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1657 Extensions instructions.
1658 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1660 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1663 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1665 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1667 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1669 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1670 (arcExtMap_genOpcode): Likewise.
1671 * arc-opc.c (arg_32bit_rc): Define new variable.
1672 (arg_32bit_u6): Likewise.
1673 (arg_32bit_limm): Likewise.
1675 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1677 * aarch64-gen.c (VERIFIER): Define.
1678 * aarch64-opc.c (VERIFIER): Define.
1679 (verify_ldpsw): Use static linkage.
1680 * aarch64-opc.h (verify_ldpsw): Remove.
1681 * aarch64-tbl.h: Use VERIFIER for verifiers.
1683 2016-04-28 Nick Clifton <nickc@redhat.com>
1686 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1687 * aarch64-opc.c (verify_ldpsw): New function.
1688 * aarch64-opc.h (verify_ldpsw): New prototype.
1689 * aarch64-tbl.h: Add initialiser for verifier field.
1690 (LDPSW): Set verifier to verify_ldpsw.
1692 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1696 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1697 smaller than address size.
1699 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1701 * alpha-dis.c: Regenerate.
1702 * crx-dis.c: Likewise.
1703 * disassemble.c: Likewise.
1704 * epiphany-opc.c: Likewise.
1705 * fr30-opc.c: Likewise.
1706 * frv-opc.c: Likewise.
1707 * ip2k-opc.c: Likewise.
1708 * iq2000-opc.c: Likewise.
1709 * lm32-opc.c: Likewise.
1710 * lm32-opinst.c: Likewise.
1711 * m32c-opc.c: Likewise.
1712 * m32r-opc.c: Likewise.
1713 * m32r-opinst.c: Likewise.
1714 * mep-opc.c: Likewise.
1715 * mt-opc.c: Likewise.
1716 * or1k-opc.c: Likewise.
1717 * or1k-opinst.c: Likewise.
1718 * tic80-opc.c: Likewise.
1719 * xc16x-opc.c: Likewise.
1720 * xstormy16-opc.c: Likewise.
1722 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1724 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1725 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1726 calcsd, and calcxd instructions.
1727 * arc-opc.c (insert_nps_bitop_size): Delete.
1728 (extract_nps_bitop_size): Delete.
1729 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1730 (extract_nps_qcmp_m3): Define.
1731 (extract_nps_qcmp_m2): Define.
1732 (extract_nps_qcmp_m1): Define.
1733 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1734 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1735 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1736 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1737 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1740 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1742 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1744 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1746 * Makefile.in: Regenerated with automake 1.11.6.
1747 * aclocal.m4: Likewise.
1749 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1751 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1753 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1754 (extract_nps_cmem_uimm16): New function.
1755 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1757 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1759 * arc-dis.c (arc_insn_length): New function.
1760 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1761 (find_format): Change insnLen parameter to unsigned.
1763 2016-04-13 Nick Clifton <nickc@redhat.com>
1766 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1767 the LD.B and LD.BU instructions.
1769 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1771 * arc-dis.c (find_format): Check for extension flags.
1772 (print_flags): New function.
1773 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1775 * arc-ext.c (arcExtMap_coreRegName): Use
1776 LAST_EXTENSION_CORE_REGISTER.
1777 (arcExtMap_coreReadWrite): Likewise.
1778 (dump_ARC_extmap): Update printing.
1779 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1780 (arc_aux_regs): Add cpu field.
1781 * arc-regs.h: Add cpu field, lower case name aux registers.
1783 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1785 * arc-tbl.h: Add rtsc, sleep with no arguments.
1787 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1789 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1791 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1792 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1793 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1794 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1795 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1796 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1797 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1798 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1799 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1800 (arc_opcode arc_opcodes): Null terminate the array.
1801 (arc_num_opcodes): Remove.
1802 * arc-ext.h (INSERT_XOP): Define.
1803 (extInstruction_t): Likewise.
1804 (arcExtMap_instName): Delete.
1805 (arcExtMap_insn): New function.
1806 (arcExtMap_genOpcode): Likewise.
1807 * arc-ext.c (ExtInstruction): Remove.
1808 (create_map): Zero initialize instruction fields.
1809 (arcExtMap_instName): Remove.
1810 (arcExtMap_insn): New function.
1811 (dump_ARC_extmap): More info while debuging.
1812 (arcExtMap_genOpcode): New function.
1813 * arc-dis.c (find_format): New function.
1814 (print_insn_arc): Use find_format.
1815 (arc_get_disassembler): Enable dump_ARC_extmap only when
1818 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1820 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1821 instruction bits out.
1823 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1825 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1826 * arc-opc.c (arc_flag_operands): Add new flags.
1827 (arc_flag_classes): Add new classes.
1829 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1831 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1833 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1835 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1836 encode1, rflt, crc16, and crc32 instructions.
1837 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1838 (arc_flag_classes): Add C_NPS_R.
1839 (insert_nps_bitop_size_2b): New function.
1840 (extract_nps_bitop_size_2b): Likewise.
1841 (insert_nps_bitop_uimm8): Likewise.
1842 (extract_nps_bitop_uimm8): Likewise.
1843 (arc_operands): Add new operand entries.
1845 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1847 * arc-regs.h: Add a new subclass field. Add double assist
1848 accumulator register values.
1849 * arc-tbl.h: Use DPA subclass to mark the double assist
1850 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1851 * arc-opc.c (RSP): Define instead of SP.
1852 (arc_aux_regs): Add the subclass field.
1854 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1856 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1858 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1860 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1863 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1865 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1866 issues. No functional changes.
1868 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1870 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1871 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1872 (RTT): Remove duplicate.
1873 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1874 (PCT_CONFIG*): Remove.
1875 (D1L, D1H, D2H, D2L): Define.
1877 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1879 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1881 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1883 * arc-tbl.h (invld07): Remove.
1884 * arc-ext-tbl.h: New file.
1885 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1886 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1888 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1890 Fix -Wstack-usage warnings.
1891 * aarch64-dis.c (print_operands): Substitute size.
1892 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1894 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1896 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1897 to get a proper diagnostic when an invalid ASR register is used.
1899 2016-03-22 Nick Clifton <nickc@redhat.com>
1901 * configure: Regenerate.
1903 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1905 * arc-nps400-tbl.h: New file.
1906 * arc-opc.c: Add top level comment.
1907 (insert_nps_3bit_dst): New function.
1908 (extract_nps_3bit_dst): New function.
1909 (insert_nps_3bit_src2): New function.
1910 (extract_nps_3bit_src2): New function.
1911 (insert_nps_bitop_size): New function.
1912 (extract_nps_bitop_size): New function.
1913 (arc_flag_operands): Add nps400 entries.
1914 (arc_flag_classes): Add nps400 entries.
1915 (arc_operands): Add nps400 entries.
1916 (arc_opcodes): Add nps400 include.
1918 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1920 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1921 the new class enum values.
1923 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1925 * arc-dis.c (print_insn_arc): Handle nps400.
1927 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1929 * arc-opc.c (BASE): Delete.
1931 2016-03-18 Nick Clifton <nickc@redhat.com>
1934 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1935 of MOV insn that aliases an ORR insn.
1937 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1939 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1941 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1943 * mcore-opc.h: Add const qualifiers.
1944 * microblaze-opc.h (struct op_code_struct): Likewise.
1945 * sh-opc.h: Likewise.
1946 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1947 (tic4x_print_op): Likewise.
1949 2016-03-02 Alan Modra <amodra@gmail.com>
1951 * or1k-desc.h: Regenerate.
1952 * fr30-ibld.c: Regenerate.
1953 * rl78-decode.c: Regenerate.
1955 2016-03-01 Nick Clifton <nickc@redhat.com>
1958 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1960 2016-02-24 Renlin Li <renlin.li@arm.com>
1962 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1963 (print_insn_coprocessor): Support fp16 instructions.
1965 2016-02-24 Renlin Li <renlin.li@arm.com>
1967 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1968 vminnm, vrint(mpna).
1970 2016-02-24 Renlin Li <renlin.li@arm.com>
1972 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1973 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1975 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1977 * i386-dis.c (print_insn): Parenthesize expression to prevent
1978 truncated addresses.
1981 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1982 Janek van Oirschot <jvanoirs@synopsys.com>
1984 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1987 2016-02-04 Nick Clifton <nickc@redhat.com>
1990 * msp430-dis.c (print_insn_msp430): Add a special case for
1991 decoding an RRC instruction with the ZC bit set in the extension
1994 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1996 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1997 * epiphany-ibld.c: Regenerate.
1998 * fr30-ibld.c: Regenerate.
1999 * frv-ibld.c: Regenerate.
2000 * ip2k-ibld.c: Regenerate.
2001 * iq2000-ibld.c: Regenerate.
2002 * lm32-ibld.c: Regenerate.
2003 * m32c-ibld.c: Regenerate.
2004 * m32r-ibld.c: Regenerate.
2005 * mep-ibld.c: Regenerate.
2006 * mt-ibld.c: Regenerate.
2007 * or1k-ibld.c: Regenerate.
2008 * xc16x-ibld.c: Regenerate.
2009 * xstormy16-ibld.c: Regenerate.
2011 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
2013 * epiphany-dis.c: Regenerated from latest cpu files.
2015 2016-02-01 Michael McConville <mmcco@mykolab.com>
2017 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
2020 2016-01-25 Renlin Li <renlin.li@arm.com>
2022 * arm-dis.c (mapping_symbol_for_insn): New function.
2023 (find_ifthen_state): Call mapping_symbol_for_insn().
2025 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
2027 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
2028 of MSR UAO immediate operand.
2030 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
2032 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
2033 instruction support.
2035 2016-01-17 Alan Modra <amodra@gmail.com>
2037 * configure: Regenerate.
2039 2016-01-14 Nick Clifton <nickc@redhat.com>
2041 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
2042 instructions that can support stack pointer operations.
2043 * rl78-decode.c: Regenerate.
2044 * rl78-dis.c: Fix display of stack pointer in MOVW based
2047 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
2049 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
2050 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
2051 erxtatus_el1 and erxaddr_el1.
2053 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
2055 * arm-dis.c (arm_opcodes): Add "esb".
2056 (thumb_opcodes): Likewise.
2058 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
2060 * ppc-opc.c <xscmpnedp>: Delete.
2061 <xvcmpnedp>: Likewise.
2062 <xvcmpnedp.>: Likewise.
2063 <xvcmpnesp>: Likewise.
2064 <xvcmpnesp.>: Likewise.
2066 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
2069 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
2072 2016-01-01 Alan Modra <amodra@gmail.com>
2074 Update year range in copyright notice of all files.
2076 For older changes see ChangeLog-2015
2078 Copyright (C) 2016 Free Software Foundation, Inc.
2080 Copying and distribution of this file, with or without modification,
2081 are permitted in any medium without royalty provided the copyright
2082 notice and this notice are preserved.
2088 version-control: never