1 2019-05-20 Nick Clifton <nickc@redhat.com>
3 * po/fr.po: Updated French translation.
5 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
6 Michael Collison <michael.collison@arm.com>
8 * arm-dis.c (thumb32_opcodes): Add new instructions.
9 (enum mve_instructions): Likewise.
10 (enum mve_undefined): Add new reasons.
11 (is_mve_encoding_conflict): Handle new instructions.
12 (is_mve_undefined): Likewise.
13 (is_mve_unpredictable): Likewise.
14 (print_mve_undefined): Likewise.
15 (print_mve_size): Likewise.
17 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
18 Michael Collison <michael.collison@arm.com>
20 * arm-dis.c (thumb32_opcodes): Add new instructions.
21 (enum mve_instructions): Likewise.
22 (is_mve_encoding_conflict): Handle new instructions.
23 (is_mve_undefined): Likewise.
24 (is_mve_unpredictable): Likewise.
25 (print_mve_size): Likewise.
27 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
28 Michael Collison <michael.collison@arm.com>
30 * arm-dis.c (thumb32_opcodes): Add new instructions.
31 (enum mve_instructions): Likewise.
32 (is_mve_encoding_conflict): Likewise.
33 (is_mve_unpredictable): Likewise.
34 (print_mve_size): Likewise.
36 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
37 Michael Collison <michael.collison@arm.com>
39 * arm-dis.c (thumb32_opcodes): Add new instructions.
40 (enum mve_instructions): Likewise.
41 (is_mve_encoding_conflict): Handle new instructions.
42 (is_mve_undefined): Likewise.
43 (is_mve_unpredictable): Likewise.
44 (print_mve_size): Likewise.
46 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
47 Michael Collison <michael.collison@arm.com>
49 * arm-dis.c (thumb32_opcodes): Add new instructions.
50 (enum mve_instructions): Likewise.
51 (is_mve_encoding_conflict): Handle new instructions.
52 (is_mve_undefined): Likewise.
53 (is_mve_unpredictable): Likewise.
54 (print_mve_size): Likewise.
55 (print_insn_mve): Likewise.
57 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
58 Michael Collison <michael.collison@arm.com>
60 * arm-dis.c (thumb32_opcodes): Add new instructions.
61 (print_insn_thumb32): Handle new instructions.
63 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
64 Michael Collison <michael.collison@arm.com>
66 * arm-dis.c (enum mve_instructions): Add new instructions.
67 (enum mve_undefined): Add new reasons.
68 (is_mve_encoding_conflict): Handle new instructions.
69 (is_mve_undefined): Likewise.
70 (is_mve_unpredictable): Likewise.
71 (print_mve_undefined): Likewise.
72 (print_mve_size): Likewise.
73 (print_mve_shift_n): Likewise.
74 (print_insn_mve): Likewise.
76 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
77 Michael Collison <michael.collison@arm.com>
79 * arm-dis.c (enum mve_instructions): Add new instructions.
80 (is_mve_encoding_conflict): Handle new instructions.
81 (is_mve_unpredictable): Likewise.
82 (print_mve_rotate): Likewise.
83 (print_mve_size): Likewise.
84 (print_insn_mve): Likewise.
86 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
87 Michael Collison <michael.collison@arm.com>
89 * arm-dis.c (enum mve_instructions): Add new instructions.
90 (is_mve_encoding_conflict): Handle new instructions.
91 (is_mve_unpredictable): Likewise.
92 (print_mve_size): Likewise.
93 (print_insn_mve): Likewise.
95 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
96 Michael Collison <michael.collison@arm.com>
98 * arm-dis.c (enum mve_instructions): Add new instructions.
99 (enum mve_undefined): Add new reasons.
100 (is_mve_encoding_conflict): Handle new instructions.
101 (is_mve_undefined): Likewise.
102 (is_mve_unpredictable): Likewise.
103 (print_mve_undefined): Likewise.
104 (print_mve_size): Likewise.
105 (print_insn_mve): Likewise.
107 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
108 Michael Collison <michael.collison@arm.com>
110 * arm-dis.c (enum mve_instructions): Add new instructions.
111 (is_mve_encoding_conflict): Handle new instructions.
112 (is_mve_undefined): Likewise.
113 (is_mve_unpredictable): Likewise.
114 (print_mve_size): Likewise.
115 (print_insn_mve): Likewise.
117 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
118 Michael Collison <michael.collison@arm.com>
120 * arm-dis.c (enum mve_instructions): Add new instructions.
121 (enum mve_unpredictable): Add new reasons.
122 (enum mve_undefined): Likewise.
123 (is_mve_okay_in_it): Handle new isntructions.
124 (is_mve_encoding_conflict): Likewise.
125 (is_mve_undefined): Likewise.
126 (is_mve_unpredictable): Likewise.
127 (print_mve_vmov_index): Likewise.
128 (print_simd_imm8): Likewise.
129 (print_mve_undefined): Likewise.
130 (print_mve_unpredictable): Likewise.
131 (print_mve_size): Likewise.
132 (print_insn_mve): Likewise.
134 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
135 Michael Collison <michael.collison@arm.com>
137 * arm-dis.c (enum mve_instructions): Add new instructions.
138 (enum mve_unpredictable): Add new reasons.
139 (enum mve_undefined): Likewise.
140 (is_mve_encoding_conflict): Handle new instructions.
141 (is_mve_undefined): Likewise.
142 (is_mve_unpredictable): Likewise.
143 (print_mve_undefined): Likewise.
144 (print_mve_unpredictable): Likewise.
145 (print_mve_rounding_mode): Likewise.
146 (print_mve_vcvt_size): Likewise.
147 (print_mve_size): Likewise.
148 (print_insn_mve): Likewise.
150 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
151 Michael Collison <michael.collison@arm.com>
153 * arm-dis.c (enum mve_instructions): Add new instructions.
154 (enum mve_unpredictable): Add new reasons.
155 (enum mve_undefined): Likewise.
156 (is_mve_undefined): Handle new instructions.
157 (is_mve_unpredictable): Likewise.
158 (print_mve_undefined): Likewise.
159 (print_mve_unpredictable): Likewise.
160 (print_mve_size): Likewise.
161 (print_insn_mve): Likewise.
163 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
164 Michael Collison <michael.collison@arm.com>
166 * arm-dis.c (enum mve_instructions): Add new instructions.
167 (enum mve_undefined): Add new reasons.
168 (insns): Add new instructions.
169 (is_mve_encoding_conflict):
170 (print_mve_vld_str_addr): New print function.
171 (is_mve_undefined): Handle new instructions.
172 (is_mve_unpredictable): Likewise.
173 (print_mve_undefined): Likewise.
174 (print_mve_size): Likewise.
175 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
176 (print_insn_mve): Handle new operands.
178 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
179 Michael Collison <michael.collison@arm.com>
181 * arm-dis.c (enum mve_instructions): Add new instructions.
182 (enum mve_unpredictable): Add new reasons.
183 (is_mve_encoding_conflict): Handle new instructions.
184 (is_mve_unpredictable): Likewise.
185 (mve_opcodes): Add new instructions.
186 (print_mve_unpredictable): Handle new reasons.
187 (print_mve_register_blocks): New print function.
188 (print_mve_size): Handle new instructions.
189 (print_insn_mve): Likewise.
191 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
192 Michael Collison <michael.collison@arm.com>
194 * arm-dis.c (enum mve_instructions): Add new instructions.
195 (enum mve_unpredictable): Add new reasons.
196 (enum mve_undefined): Likewise.
197 (is_mve_encoding_conflict): Handle new instructions.
198 (is_mve_undefined): Likewise.
199 (is_mve_unpredictable): Likewise.
200 (coprocessor_opcodes): Move NEON VDUP from here...
201 (neon_opcodes): ... to here.
202 (mve_opcodes): Add new instructions.
203 (print_mve_undefined): Handle new reasons.
204 (print_mve_unpredictable): Likewise.
205 (print_mve_size): Handle new instructions.
206 (print_insn_neon): Handle vdup.
207 (print_insn_mve): Handle new operands.
209 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
210 Michael Collison <michael.collison@arm.com>
212 * arm-dis.c (enum mve_instructions): Add new instructions.
213 (enum mve_unpredictable): Add new values.
214 (mve_opcodes): Add new instructions.
215 (vec_condnames): New array with vector conditions.
216 (mve_predicatenames): New array with predicate suffixes.
217 (mve_vec_sizename): New array with vector sizes.
218 (enum vpt_pred_state): New enum with vector predication states.
219 (struct vpt_block): New struct type for vpt blocks.
220 (vpt_block_state): Global struct to keep track of state.
221 (mve_extract_pred_mask): New helper function.
222 (num_instructions_vpt_block): Likewise.
223 (mark_outside_vpt_block): Likewise.
224 (mark_inside_vpt_block): Likewise.
225 (invert_next_predicate_state): Likewise.
226 (update_next_predicate_state): Likewise.
227 (update_vpt_block_state): Likewise.
228 (is_vpt_instruction): Likewise.
229 (is_mve_encoding_conflict): Add entries for new instructions.
230 (is_mve_unpredictable): Likewise.
231 (print_mve_unpredictable): Handle new cases.
232 (print_instruction_predicate): Likewise.
233 (print_mve_size): New function.
234 (print_vec_condition): New function.
235 (print_insn_mve): Handle vpt blocks and new print operands.
237 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
239 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
240 8, 14 and 15 for Armv8.1-M Mainline.
242 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
243 Michael Collison <michael.collison@arm.com>
245 * arm-dis.c (enum mve_instructions): New enum.
246 (enum mve_unpredictable): Likewise.
247 (enum mve_undefined): Likewise.
248 (struct mopcode32): New struct.
249 (is_mve_okay_in_it): New function.
250 (is_mve_architecture): Likewise.
251 (arm_decode_field): Likewise.
252 (arm_decode_field_multiple): Likewise.
253 (is_mve_encoding_conflict): Likewise.
254 (is_mve_undefined): Likewise.
255 (is_mve_unpredictable): Likewise.
256 (print_mve_undefined): Likewise.
257 (print_mve_unpredictable): Likewise.
258 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
259 (print_insn_mve): New function.
260 (print_insn_thumb32): Handle MVE architecture.
261 (select_arm_features): Force thumb for Armv8.1-m Mainline.
263 2019-05-10 Nick Clifton <nickc@redhat.com>
266 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
267 end of the table prematurely.
269 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
271 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
274 2019-05-11 Alan Modra <amodra@gmail.com>
276 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
277 when -Mraw is in effect.
279 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
281 * aarch64-dis-2.c: Regenerate.
282 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
283 (OP_SVE_BBB): New variant set.
284 (OP_SVE_DDDD): New variant set.
285 (OP_SVE_HHH): New variant set.
286 (OP_SVE_HHHU): New variant set.
287 (OP_SVE_SSS): New variant set.
288 (OP_SVE_SSSU): New variant set.
289 (OP_SVE_SHH): New variant set.
290 (OP_SVE_SBBU): New variant set.
291 (OP_SVE_DSS): New variant set.
292 (OP_SVE_DHHU): New variant set.
293 (OP_SVE_VMV_HSD_BHS): New variant set.
294 (OP_SVE_VVU_HSD_BHS): New variant set.
295 (OP_SVE_VVVU_SD_BH): New variant set.
296 (OP_SVE_VVVU_BHSD): New variant set.
297 (OP_SVE_VVV_QHD_DBS): New variant set.
298 (OP_SVE_VVV_HSD_BHS): New variant set.
299 (OP_SVE_VVV_HSD_BHS2): New variant set.
300 (OP_SVE_VVV_BHS_HSD): New variant set.
301 (OP_SVE_VV_BHS_HSD): New variant set.
302 (OP_SVE_VVV_SD): New variant set.
303 (OP_SVE_VVU_BHS_HSD): New variant set.
304 (OP_SVE_VZVV_SD): New variant set.
305 (OP_SVE_VZVV_BH): New variant set.
306 (OP_SVE_VZV_SD): New variant set.
307 (aarch64_opcode_table): Add sve2 instructions.
309 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
311 * aarch64-asm-2.c: Regenerated.
312 * aarch64-dis-2.c: Regenerated.
313 * aarch64-opc-2.c: Regenerated.
314 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
315 for SVE_SHLIMM_UNPRED_22.
316 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
317 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
320 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
322 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
323 sve_size_tsz_bhs iclass encode.
324 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
325 sve_size_tsz_bhs iclass decode.
327 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
329 * aarch64-asm-2.c: Regenerated.
330 * aarch64-dis-2.c: Regenerated.
331 * aarch64-opc-2.c: Regenerated.
332 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
333 for SVE_Zm4_11_INDEX.
334 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
335 (fields): Handle SVE_i2h field.
336 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
337 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
339 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
341 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
342 sve_shift_tsz_bhsd iclass encode.
343 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
344 sve_shift_tsz_bhsd iclass decode.
346 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
348 * aarch64-asm-2.c: Regenerated.
349 * aarch64-dis-2.c: Regenerated.
350 * aarch64-opc-2.c: Regenerated.
351 * aarch64-asm.c (aarch64_ins_sve_shrimm):
352 (aarch64_encode_variant_using_iclass): Handle
353 sve_shift_tsz_hsd iclass encode.
354 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
355 sve_shift_tsz_hsd iclass decode.
356 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
357 for SVE_SHRIMM_UNPRED_22.
358 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
359 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
362 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
364 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
365 sve_size_013 iclass encode.
366 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
367 sve_size_013 iclass decode.
369 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
371 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
372 sve_size_bh iclass encode.
373 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
374 sve_size_bh iclass decode.
376 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
378 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
379 sve_size_sd2 iclass encode.
380 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
381 sve_size_sd2 iclass decode.
382 * aarch64-opc.c (fields): Handle SVE_sz2 field.
383 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
385 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
387 * aarch64-asm-2.c: Regenerated.
388 * aarch64-dis-2.c: Regenerated.
389 * aarch64-opc-2.c: Regenerated.
390 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
392 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
393 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
395 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
397 * aarch64-asm-2.c: Regenerated.
398 * aarch64-dis-2.c: Regenerated.
399 * aarch64-opc-2.c: Regenerated.
400 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
401 for SVE_Zm3_11_INDEX.
402 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
403 (fields): Handle SVE_i3l and SVE_i3h2 fields.
404 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
406 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
408 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
410 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
411 sve_size_hsd2 iclass encode.
412 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
413 sve_size_hsd2 iclass decode.
414 * aarch64-opc.c (fields): Handle SVE_size field.
415 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
417 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
419 * aarch64-asm-2.c: Regenerated.
420 * aarch64-dis-2.c: Regenerated.
421 * aarch64-opc-2.c: Regenerated.
422 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
424 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
425 (fields): Handle SVE_rot3 field.
426 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
427 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
429 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
431 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
434 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
437 (aarch64_feature_sve2, aarch64_feature_sve2aes,
438 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
439 aarch64_feature_sve2bitperm): New feature sets.
440 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
441 for feature set addresses.
442 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
443 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
445 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
446 Faraz Shahbazker <fshahbazker@wavecomp.com>
448 * mips-dis.c (mips_calculate_combination_ases): Add ISA
449 argument and set ASE_EVA_R6 appropriately.
450 (set_default_mips_dis_options): Pass ISA to above.
451 (parse_mips_dis_option): Likewise.
452 * mips-opc.c (EVAR6): New macro.
453 (mips_builtin_opcodes): Add llwpe, scwpe.
455 2019-05-01 Sudakshina Das <sudi.das@arm.com>
457 * aarch64-asm-2.c: Regenerated.
458 * aarch64-dis-2.c: Regenerated.
459 * aarch64-opc-2.c: Regenerated.
460 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
461 AARCH64_OPND_TME_UIMM16.
462 (aarch64_print_operand): Likewise.
463 * aarch64-tbl.h (QL_IMM_NIL): New.
466 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
468 2019-04-29 John Darrington <john@darrington.wattle.id.au>
470 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
472 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
473 Faraz Shahbazker <fshahbazker@wavecomp.com>
475 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
477 2019-04-24 John Darrington <john@darrington.wattle.id.au>
479 * s12z-opc.h: Add extern "C" bracketing to help
480 users who wish to use this interface in c++ code.
482 2019-04-24 John Darrington <john@darrington.wattle.id.au>
484 * s12z-opc.c (bm_decode): Handle bit map operations with the
487 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
489 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
490 specifier. Add entries for VLDR and VSTR of system registers.
491 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
492 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
493 of %J and %K format specifier.
495 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
497 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
498 Add new entries for VSCCLRM instruction.
499 (print_insn_coprocessor): Handle new %C format control code.
501 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
503 * arm-dis.c (enum isa): New enum.
504 (struct sopcode32): New structure.
505 (coprocessor_opcodes): change type of entries to struct sopcode32 and
506 set isa field of all current entries to ANY.
507 (print_insn_coprocessor): Change type of insn to struct sopcode32.
508 Only match an entry if its isa field allows the current mode.
510 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
512 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
514 (print_insn_thumb32): Add logic to print %n CLRM register list.
516 2019-04-15 Sudakshina Das <sudi.das@arm.com>
518 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
521 2019-04-15 Sudakshina Das <sudi.das@arm.com>
523 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
524 (print_insn_thumb32): Edit the switch case for %Z.
526 2019-04-15 Sudakshina Das <sudi.das@arm.com>
528 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
530 2019-04-15 Sudakshina Das <sudi.das@arm.com>
532 * arm-dis.c (thumb32_opcodes): New instruction bfl.
534 2019-04-15 Sudakshina Das <sudi.das@arm.com>
536 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
538 2019-04-15 Sudakshina Das <sudi.das@arm.com>
540 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
541 Arm register with r13 and r15 unpredictable.
542 (thumb32_opcodes): New instructions for bfx and bflx.
544 2019-04-15 Sudakshina Das <sudi.das@arm.com>
546 * arm-dis.c (thumb32_opcodes): New instructions for bf.
548 2019-04-15 Sudakshina Das <sudi.das@arm.com>
550 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
552 2019-04-15 Sudakshina Das <sudi.das@arm.com>
554 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
556 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
558 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
560 2019-04-12 John Darrington <john@darrington.wattle.id.au>
562 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
563 "optr". ("operator" is a reserved word in c++).
565 2019-04-11 Sudakshina Das <sudi.das@arm.com>
567 * aarch64-opc.c (aarch64_print_operand): Add case for
569 (verify_constraints): Likewise.
570 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
571 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
572 to accept Rt|SP as first operand.
573 (AARCH64_OPERANDS): Add new Rt_SP.
574 * aarch64-asm-2.c: Regenerated.
575 * aarch64-dis-2.c: Regenerated.
576 * aarch64-opc-2.c: Regenerated.
578 2019-04-11 Sudakshina Das <sudi.das@arm.com>
580 * aarch64-asm-2.c: Regenerated.
581 * aarch64-dis-2.c: Likewise.
582 * aarch64-opc-2.c: Likewise.
583 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
585 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
587 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
589 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
591 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
592 * i386-init.h: Regenerated.
594 2019-04-07 Alan Modra <amodra@gmail.com>
596 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
597 op_separator to control printing of spaces, comma and parens
598 rather than need_comma, need_paren and spaces vars.
600 2019-04-07 Alan Modra <amodra@gmail.com>
603 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
604 (print_insn_neon, print_insn_arm): Likewise.
606 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
608 * i386-dis-evex.h (evex_table): Updated to support BF16
610 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
611 and EVEX_W_0F3872_P_3.
612 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
613 (cpu_flags): Add bitfield for CpuAVX512_BF16.
614 * i386-opc.h (enum): Add CpuAVX512_BF16.
615 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
616 * i386-opc.tbl: Add AVX512 BF16 instructions.
617 * i386-init.h: Regenerated.
618 * i386-tbl.h: Likewise.
620 2019-04-05 Alan Modra <amodra@gmail.com>
622 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
623 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
624 to favour printing of "-" branch hint when using the "y" bit.
625 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
627 2019-04-05 Alan Modra <amodra@gmail.com>
629 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
630 opcode until first operand is output.
632 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
635 * ppc-opc.c (valid_bo_pre_v2): Add comments.
636 (valid_bo_post_v2): Add support for 'at' branch hints.
637 (insert_bo): Only error on branch on ctr.
638 (get_bo_hint_mask): New function.
639 (insert_boe): Add new 'branch_taken' formal argument. Add support
640 for inserting 'at' branch hints.
641 (extract_boe): Add new 'branch_taken' formal argument. Add support
642 for extracting 'at' branch hints.
643 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
644 (BOE): Delete operand.
645 (BOM, BOP): New operands.
647 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
648 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
649 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
650 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
651 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
652 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
653 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
654 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
655 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
656 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
657 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
658 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
659 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
660 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
661 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
662 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
663 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
664 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
665 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
666 bttarl+>: New extended mnemonics.
668 2019-03-28 Alan Modra <amodra@gmail.com>
671 * ppc-opc.c (BTF): Define.
672 (powerpc_opcodes): Use for mtfsb*.
673 * ppc-dis.c (print_insn_powerpc): Print fields with both
674 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
676 2019-03-25 Tamar Christina <tamar.christina@arm.com>
678 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
679 (mapping_symbol_for_insn): Implement new algorithm.
680 (print_insn): Remove duplicate code.
682 2019-03-25 Tamar Christina <tamar.christina@arm.com>
684 * aarch64-dis.c (print_insn_aarch64):
687 2019-03-25 Tamar Christina <tamar.christina@arm.com>
689 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
692 2019-03-25 Tamar Christina <tamar.christina@arm.com>
694 * aarch64-dis.c (last_stop_offset): New.
695 (print_insn_aarch64): Use stop_offset.
697 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
700 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
702 * i386-init.h: Regenerated.
704 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
707 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
708 vmovdqu16, vmovdqu32 and vmovdqu64.
709 * i386-tbl.h: Regenerated.
711 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
713 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
714 from vstrszb, vstrszh, and vstrszf.
716 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
718 * s390-opc.txt: Add instruction descriptions.
720 2019-02-08 Jim Wilson <jimw@sifive.com>
722 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
725 2019-02-07 Tamar Christina <tamar.christina@arm.com>
727 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
729 2019-02-07 Tamar Christina <tamar.christina@arm.com>
732 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
733 * aarch64-opc.c (verify_elem_sd): New.
734 (fields): Add FLD_sz entr.
735 * aarch64-tbl.h (_SIMD_INSN): New.
736 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
737 fmulx scalar and vector by element isns.
739 2019-02-07 Nick Clifton <nickc@redhat.com>
741 * po/sv.po: Updated Swedish translation.
743 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
745 * s390-mkopc.c (main): Accept arch13 as cpu string.
746 * s390-opc.c: Add new instruction formats and instruction opcode
748 * s390-opc.txt: Add new arch13 instructions.
750 2019-01-25 Sudakshina Das <sudi.das@arm.com>
752 * aarch64-tbl.h (QL_LDST_AT): Update macro.
753 (aarch64_opcode): Change encoding for stg, stzg
755 * aarch64-asm-2.c: Regenerated.
756 * aarch64-dis-2.c: Regenerated.
757 * aarch64-opc-2.c: Regenerated.
759 2019-01-25 Sudakshina Das <sudi.das@arm.com>
761 * aarch64-asm-2.c: Regenerated.
762 * aarch64-dis-2.c: Likewise.
763 * aarch64-opc-2.c: Likewise.
764 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
766 2019-01-25 Sudakshina Das <sudi.das@arm.com>
767 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
769 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
770 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
771 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
772 * aarch64-dis.h (ext_addr_simple_2): Likewise.
773 * aarch64-opc.c (operand_general_constraint_met_p): Remove
774 case for ldstgv_indexed.
775 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
776 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
777 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
778 * aarch64-asm-2.c: Regenerated.
779 * aarch64-dis-2.c: Regenerated.
780 * aarch64-opc-2.c: Regenerated.
782 2019-01-23 Nick Clifton <nickc@redhat.com>
784 * po/pt_BR.po: Updated Brazilian Portuguese translation.
786 2019-01-21 Nick Clifton <nickc@redhat.com>
788 * po/de.po: Updated German translation.
789 * po/uk.po: Updated Ukranian translation.
791 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
792 * mips-dis.c (mips_arch_choices): Fix typo in
793 gs464, gs464e and gs264e descriptors.
795 2019-01-19 Nick Clifton <nickc@redhat.com>
797 * configure: Regenerate.
798 * po/opcodes.pot: Regenerate.
800 2018-06-24 Nick Clifton <nickc@redhat.com>
804 2019-01-09 John Darrington <john@darrington.wattle.id.au>
806 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
808 -dis.c (opr_emit_disassembly): Do not omit an index if it is
811 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
813 * configure: Regenerate.
815 2019-01-07 Alan Modra <amodra@gmail.com>
817 * configure: Regenerate.
818 * po/POTFILES.in: Regenerate.
820 2019-01-03 John Darrington <john@darrington.wattle.id.au>
822 * s12z-opc.c: New file.
823 * s12z-opc.h: New file.
824 * s12z-dis.c: Removed all code not directly related to display
825 of instructions. Used the interface provided by the new files
827 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
828 * Makefile.in: Regenerate.
829 * configure.ac (bfd_s12z_arch): Correct the dependencies.
830 * configure: Regenerate.
832 2019-01-01 Alan Modra <amodra@gmail.com>
834 Update year range in copyright notice of all files.
836 For older changes see ChangeLog-2018
838 Copyright (C) 2019 Free Software Foundation, Inc.
840 Copying and distribution of this file, with or without modification,
841 are permitted in any medium without royalty provided the copyright
842 notice and this notice are preserved.
848 version-control: never