1 2011-09-07 Andreas Schwab <schwab@linux-m68k.org>
3 * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
5 2011-08-26 Nick Clifton <nickc@redhat.com>
7 * po/es.po: Updated Spanish translation.
9 2011-08-22 Nick Clifton <nickc@redhat.com>
11 * Makefile.am (CPUDIR): Redfine to point to top level cpu
13 (stamp-frv): Use CPUDIR.
14 (stamp-iq2000): Likewise.
15 (stamp-lm32): Likewise.
16 (stamp-m32c): Likewise.
18 (stamp-xc16x): Likewise.
19 * Makefile.in: Regenerate.
21 2011-08-09 Chao-ying Fu <fu@mips.com>
22 Maciej W. Rozycki <macro@codesourcery.com>
24 * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
26 (print_insn_args, print_insn_micromips): Handle MCU.
27 * micromips-opc.c (MC): New macro.
28 (micromips_opcodes): Add "aclr", "aset" and "iret".
29 * mips-opc.c (MC): New macro.
30 (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
32 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
34 * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
35 (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
36 (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
37 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
38 (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
39 (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
41 (micromips_opcodes): Update register use flags of: "addiu",
42 "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
43 "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
44 "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
45 "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
46 "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
47 "swm" and "xor" instructions.
49 2011-08-05 David S. Miller <davem@davemloft.net>
51 * sparc-dis.c (v9a_ast_reg_names): Add "cps".
53 (print_insn_sparc): Handle '4', '5', and '(' format codes.
54 Accept %asr numbers below 28.
55 * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
58 2011-08-02 Quentin Neill <quentin.neill@amd.com>
60 * i386-dis.c (xop_table): Remove spurious bextr insn.
62 2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
65 * i386-dis.c (print_insn): Optimize info->mach check.
67 2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
70 * i386-opc.tbl: Add Disp32S to 64bit call.
71 * i386-tbl.h: Regenerated.
73 2011-07-24 Chao-ying Fu <fu@mips.com>
74 Maciej W. Rozycki <macro@codesourcery.com>
76 * micromips-opc.c: New file.
77 * mips-dis.c (micromips_to_32_reg_b_map): New array.
78 (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
79 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
80 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
81 (micromips_to_32_reg_q_map): Likewise.
82 (micromips_imm_b_map, micromips_imm_c_map): Likewise.
83 (micromips_ase): New variable.
84 (is_micromips): New function.
85 (set_default_mips_dis_options): Handle microMIPS ASE.
86 (print_insn_micromips): New function.
87 (is_compressed_mode_p): Likewise.
88 (_print_insn_mips): Handle microMIPS instructions.
89 * Makefile.am (CFILES): Add micromips-opc.c.
90 * configure.in (bfd_mips_arch): Add micromips-opc.lo.
91 * Makefile.in: Regenerate.
92 * configure: Regenerate.
94 * mips-dis.c (micromips_to_32_reg_h_map): New variable.
95 (micromips_to_32_reg_i_map): Likewise.
96 (micromips_to_32_reg_m_map): Likewise.
97 (micromips_to_32_reg_n_map): New macro.
99 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
101 * mips-opc.c (NODS): New macro.
102 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
103 (DSP_VOLA): Likewise.
104 (mips_builtin_opcodes): Add NODS annotation to "deret" and
105 "eret". Replace INSN_SYNC with NODS throughout. Use NODS in
106 place of TRAP for "wait", "waiti" and "yield".
107 * mips16-opc.c (NODS): New macro.
108 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
109 (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
110 "restore" and "save".
112 2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
114 * configure.in: Handle bfd_k1om_arch.
115 * configure: Regenerated.
117 * disassemble.c (disassembler): Handle bfd_k1om_arch.
119 * i386-dis.c (print_insn): Handle bfd_mach_k1om and
120 bfd_mach_k1om_intel_syntax.
122 * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
123 ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
124 (cpu_flags): Add CpuK1OM.
126 * i386-opc.h (CpuK1OM): New.
127 (i386_cpu_flags): Add cpuk1om.
129 * i386-init.h: Regenerated.
130 * i386-tbl.h: Likewise.
132 2011-07-12 Nick Clifton <nickc@redhat.com>
134 * arm-dis.c (print_insn_arm): Revert previous, undocumented,
137 2011-07-01 Nick Clifton <nickc@redhat.com>
140 * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
141 insns using post-increment addressing.
143 2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
145 * i386-dis.c (vex_len_table): Update rorxS.
147 2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
149 AVX Programming Reference (June, 2011)
150 * i386-dis.c (vex_len_table): Correct rorxS.
152 * i386-opc.tbl: Correct rorx.
153 * i386-tbl.h: Regenerated.
155 2011-06-29 H.J. Lu <hongjiu.lu@intel.com>
157 * tilegx-opc.c (find_opcode): Replace "index" with "i".
158 * tilepro-opc.c (find_opcode): Likewise.
160 2011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
162 * mips16-opc.c (jalrc, jrc): Move earlier in file.
164 2011-06-21 H.J. Lu <hongjiu.lu@intel.com>
166 * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
169 2011-06-17 Andreas Schwab <schwab@redhat.com>
171 * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
172 (MOSTLYCLEANFILES): ... here.
173 * Makefile.in: Regenerate.
175 2011-06-14 Alan Modra <amodra@gmail.com>
177 * Makefile.in: Regenerate.
179 2011-06-13 Walter Lee <walt@tilera.com>
181 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
182 tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
183 * Makefile.in: Regenerate.
184 * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
185 * configure: Regenerate.
186 * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
187 * po/POTFILES.in: Regenerate.
188 * tilegx-dis.c: New file.
189 * tilegx-opc.c: New file.
190 * tilepro-dis.c: New file.
191 * tilepro-opc.c: New file.
193 2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
195 AVX Programming Reference (June, 2011)
196 * i386-dis.c (XMGatherQ): New.
197 * i386-dis.c (EXxmm_mb): New.
198 (EXxmm_mb): Likewise.
199 (EXxmm_mw): Likewise.
200 (EXxmm_md): Likewise.
201 (EXxmm_mq): Likewise.
204 (VexGatherQ): Likewise.
205 (MVexVSIBDWpX): Likewise.
206 (MVexVSIBQWpX): Likewise.
207 (xmm_mb_mode): Likewise.
208 (xmm_mw_mode): Likewise.
209 (xmm_md_mode): Likewise.
210 (xmm_mq_mode): Likewise.
211 (xmmdw_mode): Likewise.
212 (xmmqd_mode): Likewise.
213 (ymmxmm_mode): Likewise.
214 (vex_vsib_d_w_dq_mode): Likewise.
215 (vex_vsib_q_w_dq_mode): Likewise.
216 (MOD_VEX_0F385A_PREFIX_2): Likewise.
217 (MOD_VEX_0F388C_PREFIX_2): Likewise.
218 (MOD_VEX_0F388E_PREFIX_2): Likewise.
219 (PREFIX_0F3882): Likewise.
220 (PREFIX_VEX_0F3816): Likewise.
221 (PREFIX_VEX_0F3836): Likewise.
222 (PREFIX_VEX_0F3845): Likewise.
223 (PREFIX_VEX_0F3846): Likewise.
224 (PREFIX_VEX_0F3847): Likewise.
225 (PREFIX_VEX_0F3858): Likewise.
226 (PREFIX_VEX_0F3859): Likewise.
227 (PREFIX_VEX_0F385A): Likewise.
228 (PREFIX_VEX_0F3878): Likewise.
229 (PREFIX_VEX_0F3879): Likewise.
230 (PREFIX_VEX_0F388C): Likewise.
231 (PREFIX_VEX_0F388E): Likewise.
232 (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
233 (PREFIX_VEX_0F38F5): Likewise.
234 (PREFIX_VEX_0F38F6): Likewise.
235 (PREFIX_VEX_0F3A00): Likewise.
236 (PREFIX_VEX_0F3A01): Likewise.
237 (PREFIX_VEX_0F3A02): Likewise.
238 (PREFIX_VEX_0F3A38): Likewise.
239 (PREFIX_VEX_0F3A39): Likewise.
240 (PREFIX_VEX_0F3A46): Likewise.
241 (PREFIX_VEX_0F3AF0): Likewise.
242 (VEX_LEN_0F3816_P_2): Likewise.
243 (VEX_LEN_0F3819_P_2): Likewise.
244 (VEX_LEN_0F3836_P_2): Likewise.
245 (VEX_LEN_0F385A_P_2_M_0): Likewise.
246 (VEX_LEN_0F38F5_P_0): Likewise.
247 (VEX_LEN_0F38F5_P_1): Likewise.
248 (VEX_LEN_0F38F5_P_3): Likewise.
249 (VEX_LEN_0F38F6_P_3): Likewise.
250 (VEX_LEN_0F38F7_P_1): Likewise.
251 (VEX_LEN_0F38F7_P_2): Likewise.
252 (VEX_LEN_0F38F7_P_3): Likewise.
253 (VEX_LEN_0F3A00_P_2): Likewise.
254 (VEX_LEN_0F3A01_P_2): Likewise.
255 (VEX_LEN_0F3A38_P_2): Likewise.
256 (VEX_LEN_0F3A39_P_2): Likewise.
257 (VEX_LEN_0F3A46_P_2): Likewise.
258 (VEX_LEN_0F3AF0_P_3): Likewise.
259 (VEX_W_0F3816_P_2): Likewise.
260 (VEX_W_0F3818_P_2): Likewise.
261 (VEX_W_0F3819_P_2): Likewise.
262 (VEX_W_0F3836_P_2): Likewise.
263 (VEX_W_0F3846_P_2): Likewise.
264 (VEX_W_0F3858_P_2): Likewise.
265 (VEX_W_0F3859_P_2): Likewise.
266 (VEX_W_0F385A_P_2_M_0): Likewise.
267 (VEX_W_0F3878_P_2): Likewise.
268 (VEX_W_0F3879_P_2): Likewise.
269 (VEX_W_0F3A00_P_2): Likewise.
270 (VEX_W_0F3A01_P_2): Likewise.
271 (VEX_W_0F3A02_P_2): Likewise.
272 (VEX_W_0F3A38_P_2): Likewise.
273 (VEX_W_0F3A39_P_2): Likewise.
274 (VEX_W_0F3A46_P_2): Likewise.
275 (MOD_VEX_0F3818_PREFIX_2): Removed.
276 (MOD_VEX_0F3819_PREFIX_2): Likewise.
277 (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
278 (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
279 (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
280 (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
281 (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
282 (VEX_LEN_0F3A0E_P_2): Likewise.
283 (VEX_LEN_0F3A0F_P_2): Likewise.
284 (VEX_LEN_0F3A42_P_2): Likewise.
285 (VEX_LEN_0F3A4C_P_2): Likewise.
286 (VEX_W_0F3818_P_2_M_0): Likewise.
287 (VEX_W_0F3819_P_2_M_0): Likewise.
288 (prefix_table): Updated.
289 (three_byte_table): Likewise.
290 (vex_table): Likewise.
291 (vex_len_table): Likewise.
292 (vex_w_table): Likewise.
293 (mod_table): Likewise.
294 (putop): Handle "LW".
295 (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
296 xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
297 vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
299 (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
300 vex_vsib_q_w_dq_mode.
301 (OP_XMM): Handle vex_vsib_q_w_dq_mode.
304 * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
305 and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
306 CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
307 (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
308 (opcode_modifiers): Add VecSIB.
310 * i386-opc.h (CpuAVX2): New.
312 (CpuLZCNT): Likewise.
313 (CpuINVPCID): Likewise.
314 (VecSIB128): Likewise.
315 (VecSIB256): Likewise.
317 (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
318 (i386_opcode_modifier): Add vecsib.
320 * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
321 * i386-init.h: Regenerated.
322 * i386-tbl.h: Likewise.
324 2011-06-03 Quentin Neill <quentin.neill@amd.com>
326 * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
327 * i386-init.h: Regenerated.
329 2011-06-03 Nick Clifton <nickc@redhat.com>
332 * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
333 computing address offsets.
334 (print_arm_address): Likewise.
335 (print_insn_arm): Likewise.
336 (print_insn_thumb16): Likewise.
337 (print_insn_thumb32): Likewise.
339 2011-06-02 Jie Zhang <jie@codesourcery.com>
340 Nathan Sidwell <nathan@codesourcery.com>
341 Maciej Rozycki <macro@codesourcery.com>
343 * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
345 (print_arm_address): Likewise. Elide positive #0 appropriately.
346 (print_insn_arm): Likewise.
348 2011-06-02 Nick Clifton <nickc@redhat.com>
351 * arm-dis.c (print_insn_thumb32): Do not sign extend addresses
352 passed to print_address_func.
354 2011-06-02 Nick Clifton <nickc@redhat.com>
356 * arm-dis.c: Fix spelling mistakes.
357 * op/opcodes.pot: Regenerate.
359 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
361 * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
362 S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
363 * s390-opc.txt: Fix cxr instruction type.
365 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
367 * s390-opc.c: Add new instruction types marking register pair
369 * s390-opc.txt: Match instructions having register pair operands
370 to the new instruction types.
372 2011-05-19 Nick Clifton <nickc@redhat.com>
374 * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
377 2011-05-10 Quentin Neill <quentin.neill@amd.com>
379 * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
380 * i386-init.h: Regenerated.
382 2011-04-27 Nick Clifton <nickc@redhat.com>
384 * po/da.po: Updated Danish translation.
386 2011-04-26 Anton Blanchard <anton@samba.org>
388 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
390 2011-04-21 DJ Delorie <dj@redhat.com>
392 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
393 * rx-decode.c: Regenerate.
395 2011-04-20 H.J. Lu <hongjiu.lu@intel.com>
397 * i386-init.h: Regenerated.
399 2011-04-19 Quentin Neill <quentin.neill@amd.com>
401 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
404 2011-04-13 Nick Clifton <nickc@redhat.com>
406 * v850-dis.c (disassemble): Always print a closing square brace if
407 an opening square brace was printed.
409 2011-04-12 Nick Clifton <nickc@redhat.com>
412 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
414 (print_insn_thumb32): Handle %L.
416 2011-04-11 Julian Brown <julian@codesourcery.com>
418 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
419 (print_insn_thumb32): Add APSR bitmask support.
421 2011-04-07 Paul Carroll<pcarroll@codesourcery.com>
423 * arm-dis.c (print_insn): init vars moved into private_data structure.
425 2011-03-24 Mike Frysinger <vapier@gentoo.org>
427 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
429 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
431 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
432 post-increment to support LPM Z+ instruction. Add support for 'E'
433 constraint for DES instruction.
434 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
436 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
438 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
440 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
442 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
443 Use branch types instead.
444 (print_insn): Likewise.
446 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
448 * mips-opc.c (mips_builtin_opcodes): Correct register use
449 annotation of "alnv.ps".
451 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
453 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
455 2011-02-22 Mike Frysinger <vapier@gentoo.org>
457 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
459 2011-02-22 Mike Frysinger <vapier@gentoo.org>
461 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
463 2011-02-19 Mike Frysinger <vapier@gentoo.org>
465 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
466 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
467 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
468 exception, end_of_registers, msize, memory, bfd_mach.
469 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
470 LB0REG, LC1REG, LT1REG, LB1REG): Delete
471 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
472 (get_allreg): Change to new defines. Fallback to abort().
474 2011-02-14 Mike Frysinger <vapier@gentoo.org>
476 * bfin-dis.c: Add whitespace/parenthesis where needed.
478 2011-02-14 Mike Frysinger <vapier@gentoo.org>
480 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
483 2011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
485 * configure: Regenerate.
487 2011-02-13 Mike Frysinger <vapier@gentoo.org>
489 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
491 2011-02-13 Mike Frysinger <vapier@gentoo.org>
493 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
494 dregs only when P is set, and dregs_lo otherwise.
496 2011-02-13 Mike Frysinger <vapier@gentoo.org>
498 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
500 2011-02-12 Mike Frysinger <vapier@gentoo.org>
502 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
504 2011-02-12 Mike Frysinger <vapier@gentoo.org>
506 * bfin-dis.c (machine_registers): Delete REG_GP.
507 (reg_names): Delete "GP".
508 (decode_allregs): Change REG_GP to REG_LASTREG.
510 2011-02-12 Mike Frysinger <vapier@gentoo.org>
512 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
515 2011-02-11 Mike Frysinger <vapier@gentoo.org>
517 * bfin-dis.c (reg_names): Add const.
518 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
519 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
520 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
521 decode_counters, decode_allregs): Likewise.
523 2011-02-09 Michael Snyder <msnyder@vmware.com>
525 * i386-dis.c (OP_J): Parenthesize expression to prevent
527 (print_insn): Fix indentation off-by-one.
529 2011-02-01 Nick Clifton <nickc@redhat.com>
531 * po/da.po: Updated Danish translation.
533 2011-01-21 Dave Murphy <davem@devkitpro.org>
535 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
537 2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
539 * i386-dis.c (sIbT): New.
540 (b_T_mode): Likewise.
541 (dis386): Replace sIb with sIbT on "pushT".
542 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
543 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
545 2011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
547 * i386-init.h: Regenerated.
548 * i386-tbl.h: Regenerated
550 2011-01-17 Quentin Neill <quentin.neill@amd.com>
552 * i386-dis.c (REG_XOP_TBM_01): New.
553 (REG_XOP_TBM_02): New.
554 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
555 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
556 entries, and add bextr instruction.
558 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
559 (cpu_flags): Add CpuTBM.
561 * i386-opc.h (CpuTBM) New.
562 (i386_cpu_flags): Add bit cputbm.
564 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
565 blcs, blsfill, blsic, t1mskc, and tzmsk.
567 2011-01-12 DJ Delorie <dj@redhat.com>
569 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
571 2011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
573 * mips-dis.c (print_insn_args): Adjust the value to print the real
574 offset for "+c" argument.
576 2011-01-10 Nick Clifton <nickc@redhat.com>
578 * po/da.po: Updated Danish translation.
580 2011-01-05 Nathan Sidwell <nathan@codesourcery.com>
582 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
584 2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
586 * i386-dis.c (REG_VEX_38F3): New.
587 (PREFIX_0FBC): Likewise.
588 (PREFIX_VEX_38F2): Likewise.
589 (PREFIX_VEX_38F3_REG_1): Likewise.
590 (PREFIX_VEX_38F3_REG_2): Likewise.
591 (PREFIX_VEX_38F3_REG_3): Likewise.
592 (PREFIX_VEX_38F7): Likewise.
593 (VEX_LEN_38F2_P_0): Likewise.
594 (VEX_LEN_38F3_R_1_P_0): Likewise.
595 (VEX_LEN_38F3_R_2_P_0): Likewise.
596 (VEX_LEN_38F3_R_3_P_0): Likewise.
597 (VEX_LEN_38F7_P_0): Likewise.
598 (dis386_twobyte): Use PREFIX_0FBC.
599 (reg_table): Add REG_VEX_38F3.
600 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
601 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
602 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
603 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
605 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
606 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
609 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
610 (cpu_flags): Add CpuBMI.
612 * i386-opc.h (CpuBMI): New.
613 (i386_cpu_flags): Add cpubmi.
615 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
616 * i386-init.h: Regenerated.
617 * i386-tbl.h: Likewise.
619 2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
621 * i386-dis.c (VexGdq): New.
622 (OP_VEX): Handle dq_mode.
624 2011-01-01 H.J. Lu <hongjiu.lu@intel.com>
626 * i386-gen.c (process_copyright): Update copyright to 2011.
628 For older changes see ChangeLog-2010
634 version-control: never