1 2018-09-13 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
4 * i386-tbl.h: Re-generate.
6 2018-09-13 Jan Beulich <jbeulich@suse.com>
8 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
9 * i386-tbl.h: Re-generate.
11 2018-09-13 Jan Beulich <jbeulich@suse.com>
13 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
14 * i386-tbl.h: Re-generate.
16 2018-09-13 Jan Beulich <jbeulich@suse.com>
18 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
20 * i386-tbl.h: Re-generate.
22 2018-09-13 Jan Beulich <jbeulich@suse.com>
24 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
26 * i386-tbl.h: Re-generate.
28 2018-09-13 Jan Beulich <jbeulich@suse.com>
30 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
32 * i386-tbl.h: Re-generate.
34 2018-09-13 Jan Beulich <jbeulich@suse.com>
36 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
37 * i386-tbl.h: Re-generate.
39 2018-09-13 Jan Beulich <jbeulich@suse.com>
41 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
42 * i386-tbl.h: Re-generate.
44 2018-09-13 Jan Beulich <jbeulich@suse.com>
46 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
47 * i386-tbl.h: Re-generate.
49 2018-09-13 Jan Beulich <jbeulich@suse.com>
51 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
52 (vpbroadcastw, rdpid): Drop NoRex64.
53 * i386-tbl.h: Re-generate.
55 2018-09-13 Jan Beulich <jbeulich@suse.com>
57 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
58 store templates, adding D.
59 * i386-tbl.h: Re-generate.
61 2018-09-13 Jan Beulich <jbeulich@suse.com>
63 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
64 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
65 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
66 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
67 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
68 Fold load and store templates where possible, adding D. Drop
69 IgnoreSize where it was pointlessly present. Drop redundant
71 * i386-tbl.h: Re-generate.
73 2018-09-13 Jan Beulich <jbeulich@suse.com>
75 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
76 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
77 (intel_operand_size): Handle v_bndmk_mode.
78 (OP_E_memory): Likewise. Produce (bad) when also riprel.
80 2018-09-08 John Darrington <john@darrington.wattle.id.au>
82 * disassemble.c (ARCH_s12z): Define if ARCH_all.
84 2018-08-31 Kito Cheng <kito@andestech.com>
86 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
87 compressed floating point instructions.
89 2018-08-30 Kito Cheng <kito@andestech.com>
91 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
92 riscv_opcode.xlen_requirement.
93 * riscv-opc.c (riscv_opcodes): Update for struct change.
95 2018-08-29 Martin Aberg <maberg@gaisler.com>
97 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
98 psr (PWRPSR) instruction.
100 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
102 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
104 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
106 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
108 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
110 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
111 loongson3a as an alias of gs464 for compatibility.
112 * mips-opc.c (mips_opcodes): Change Comments.
114 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
116 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
118 (print_mips_disassembler_options): Document -M loongson-ext.
119 * mips-opc.c (LEXT2): New macro.
120 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
122 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
124 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
126 (parse_mips_ase_option): Handle -M loongson-ext option.
127 (print_mips_disassembler_options): Document -M loongson-ext.
128 * mips-opc.c (IL3A): Delete.
129 * mips-opc.c (LEXT): New macro.
130 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
133 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
135 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
137 (parse_mips_ase_option): Handle -M loongson-cam option.
138 (print_mips_disassembler_options): Document -M loongson-cam.
139 * mips-opc.c (LCAM): New macro.
140 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
143 2018-08-21 Alan Modra <amodra@gmail.com>
145 * ppc-dis.c (operand_value_powerpc): Init "invalid".
146 (skip_optional_operands): Count optional operands, and update
147 ppc_optional_operand_value call.
148 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
149 (extract_vlensi): Likewise.
150 (extract_fxm): Return default value for missing optional operand.
151 (extract_ls, extract_raq, extract_tbr): Likewise.
152 (insert_sxl, extract_sxl): New functions.
153 (insert_esync, extract_esync): Remove Power9 handling and simplify.
154 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
155 flag and extra entry.
156 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
159 2018-08-20 Alan Modra <amodra@gmail.com>
161 * sh-opc.h (MASK): Simplify.
163 2018-08-18 John Darrington <john@darrington.wattle.id.au>
165 * s12z-dis.c (bm_decode): Deal with cases where the mode is
166 BM_RESERVED0 or BM_RESERVED1
167 (bm_rel_decode, bm_n_bytes): Ditto.
169 2018-08-18 John Darrington <john@darrington.wattle.id.au>
173 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
175 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
176 address with the addr32 prefix and without base nor index
179 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
181 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
182 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
183 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
184 (cpu_flags): Add CpuCMOV and CpuFXSR.
185 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
186 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
187 * i386-init.h: Regenerated.
188 * i386-tbl.h: Likewise.
190 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
192 * arc-regs.h: Update auxiliary registers.
194 2018-08-06 Jan Beulich <jbeulich@suse.com>
196 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
197 (RegIP, RegIZ): Define.
198 * i386-reg.tbl: Adjust comments.
199 (rip): Use Qword instead of BaseIndex. Use RegIP.
200 (eip): Use Dword instead of BaseIndex. Use RegIP.
201 (riz): Add Qword. Use RegIZ.
202 (eiz): Add Dword. Use RegIZ.
203 * i386-tbl.h: Re-generate.
205 2018-08-03 Jan Beulich <jbeulich@suse.com>
207 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
208 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
209 vpmovzxdq, vpmovzxwd): Remove NoRex64.
210 * i386-tbl.h: Re-generate.
212 2018-08-03 Jan Beulich <jbeulich@suse.com>
214 * i386-gen.c (operand_types): Remove Mem field.
215 * i386-opc.h (union i386_operand_type): Remove mem field.
216 * i386-init.h, i386-tbl.h: Re-generate.
218 2018-08-01 Alan Modra <amodra@gmail.com>
220 * po/POTFILES.in: Regenerate.
222 2018-07-31 Nick Clifton <nickc@redhat.com>
224 * po/sv.po: Updated Swedish translation.
226 2018-07-31 Jan Beulich <jbeulich@suse.com>
228 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
229 * i386-init.h, i386-tbl.h: Re-generate.
231 2018-07-31 Jan Beulich <jbeulich@suse.com>
233 * i386-opc.h (ZEROING_MASKING) Rename to ...
234 (DYNAMIC_MASKING): ... this. Adjust comment.
235 * i386-opc.tbl (MaskingMorZ): Define.
236 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
237 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
238 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
239 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
240 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
241 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
242 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
243 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
244 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
246 2018-07-31 Jan Beulich <jbeulich@suse.com>
248 * i386-opc.tbl: Use element rather than vector size for AVX512*
249 scatter/gather insns.
250 * i386-tbl.h: Re-generate.
252 2018-07-31 Jan Beulich <jbeulich@suse.com>
254 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
255 (cpu_flags): Drop CpuVREX.
256 * i386-opc.h (CpuVREX): Delete.
257 (union i386_cpu_flags): Remove cpuvrex.
258 * i386-init.h, i386-tbl.h: Re-generate.
260 2018-07-30 Jim Wilson <jimw@sifive.com>
262 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
264 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
266 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
268 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
269 * Makefile.in: Regenerated.
270 * configure.ac: Add C-SKY.
271 * configure: Regenerated.
272 * csky-dis.c: New file.
273 * csky-opc.h: New file.
274 * disassemble.c (ARCH_csky): Define.
275 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
276 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
278 2018-07-27 Alan Modra <amodra@gmail.com>
280 * ppc-opc.c (insert_sprbat): Correct function parameter and
282 (extract_sprbat): Likewise, variable too.
284 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
285 Alan Modra <amodra@gmail.com>
287 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
288 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
289 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
290 support disjointed BAT.
291 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
292 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
293 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
295 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
296 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
298 * i386-gen.c (adjust_broadcast_modifier): New function.
299 (process_i386_opcode_modifier): Add an argument for operands.
300 Adjust the Broadcast value based on operands.
301 (output_i386_opcode): Pass operand_types to
302 process_i386_opcode_modifier.
303 (process_i386_opcodes): Pass NULL as operands to
304 process_i386_opcode_modifier.
305 * i386-opc.h (BYTE_BROADCAST): New.
306 (WORD_BROADCAST): Likewise.
307 (DWORD_BROADCAST): Likewise.
308 (QWORD_BROADCAST): Likewise.
309 (i386_opcode_modifier): Expand broadcast to 3 bits.
310 * i386-tbl.h: Regenerated.
312 2018-07-24 Alan Modra <amodra@gmail.com>
315 * or1k-desc.h: Regenerate.
317 2018-07-24 Jan Beulich <jbeulich@suse.com>
319 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
320 vcvtusi2ss, and vcvtusi2sd.
321 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
322 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
323 * i386-tbl.h: Re-generate.
325 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
327 * arc-opc.c (extract_w6): Fix extending the sign.
329 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
331 * arc-tbl.h (vewt): Allow it for ARC EM family.
333 2018-07-23 Alan Modra <amodra@gmail.com>
336 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
337 opcode variants for mtspr/mfspr encodings.
339 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
340 Maciej W. Rozycki <macro@mips.com>
342 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
343 loongson3a descriptors.
344 (parse_mips_ase_option): Handle -M loongson-mmi option.
345 (print_mips_disassembler_options): Document -M loongson-mmi.
346 * mips-opc.c (LMMI): New macro.
347 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
350 2018-07-19 Jan Beulich <jbeulich@suse.com>
352 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
353 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
354 IgnoreSize and [XYZ]MMword where applicable.
355 * i386-tbl.h: Re-generate.
357 2018-07-19 Jan Beulich <jbeulich@suse.com>
359 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
360 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
361 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
362 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
363 * i386-tbl.h: Re-generate.
365 2018-07-19 Jan Beulich <jbeulich@suse.com>
367 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
368 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
369 VPCLMULQDQ templates into their respective AVX512VL counterparts
370 where possible, using Disp8ShiftVL and CheckRegSize instead of
371 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
372 * i386-tbl.h: Re-generate.
374 2018-07-19 Jan Beulich <jbeulich@suse.com>
376 * i386-opc.tbl: Fold AVX512DQ templates into their respective
377 AVX512VL counterparts where possible, using Disp8ShiftVL and
378 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
379 IgnoreSize) as appropriate.
380 * i386-tbl.h: Re-generate.
382 2018-07-19 Jan Beulich <jbeulich@suse.com>
384 * i386-opc.tbl: Fold AVX512BW templates into their respective
385 AVX512VL counterparts where possible, using Disp8ShiftVL and
386 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
387 IgnoreSize) as appropriate.
388 * i386-tbl.h: Re-generate.
390 2018-07-19 Jan Beulich <jbeulich@suse.com>
392 * i386-opc.tbl: Fold AVX512CD templates into their respective
393 AVX512VL counterparts where possible, using Disp8ShiftVL and
394 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
395 IgnoreSize) as appropriate.
396 * i386-tbl.h: Re-generate.
398 2018-07-19 Jan Beulich <jbeulich@suse.com>
400 * i386-opc.h (DISP8_SHIFT_VL): New.
401 * i386-opc.tbl (Disp8ShiftVL): Define.
402 (various): Fold AVX512VL templates into their respective
403 AVX512F counterparts where possible, using Disp8ShiftVL and
404 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
405 IgnoreSize) as appropriate.
406 * i386-tbl.h: Re-generate.
408 2018-07-19 Jan Beulich <jbeulich@suse.com>
410 * Makefile.am: Change dependencies and rule for
411 $(srcdir)/i386-init.h.
412 * Makefile.in: Re-generate.
413 * i386-gen.c (process_i386_opcodes): New local variable
414 "marker". Drop opening of input file. Recognize marker and line
416 * i386-opc.tbl (OPCODE_I386_H): Define.
417 (i386-opc.h): Include it.
420 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
423 * i386-opc.h (Byte): Update comments.
432 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
434 * i386-tbl.h: Regenerated.
436 2018-07-12 Sudakshina Das <sudi.das@arm.com>
438 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
439 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
440 * aarch64-asm-2.c: Regenerate.
441 * aarch64-dis-2.c: Regenerate.
442 * aarch64-opc-2.c: Regenerate.
444 2018-07-12 Tamar Christina <tamar.christina@arm.com>
447 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
448 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
449 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
450 sqdmulh, sqrdmulh): Use Em16.
452 2018-07-11 Sudakshina Das <sudi.das@arm.com>
454 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
455 csdb together with them.
456 (thumb32_opcodes): Likewise.
458 2018-07-11 Jan Beulich <jbeulich@suse.com>
460 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
461 requiring 32-bit registers as operands 2 and 3. Improve
463 (mwait, mwaitx): Fold templates. Improve comments.
464 OPERAND_TYPE_INOUTPORTREG.
465 * i386-tbl.h: Re-generate.
467 2018-07-11 Jan Beulich <jbeulich@suse.com>
469 * i386-gen.c (operand_type_init): Remove
470 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
471 OPERAND_TYPE_INOUTPORTREG.
472 * i386-init.h: Re-generate.
474 2018-07-11 Jan Beulich <jbeulich@suse.com>
476 * i386-opc.tbl (wrssd, wrussd): Add Dword.
477 (wrssq, wrussq): Add Qword.
478 * i386-tbl.h: Re-generate.
480 2018-07-11 Jan Beulich <jbeulich@suse.com>
482 * i386-opc.h: Rename OTMax to OTNum.
483 (OTNumOfUints): Adjust calculation.
484 (OTUnused): Directly alias to OTNum.
486 2018-07-09 Maciej W. Rozycki <macro@mips.com>
488 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
490 (lea_reg_xys): Likewise.
491 (print_insn_loop_primitive): Rename `reg' local variable to
494 2018-07-06 Tamar Christina <tamar.christina@arm.com>
497 * aarch64-tbl.h (ldarh): Fix disassembly mask.
499 2018-07-06 Tamar Christina <tamar.christina@arm.com>
502 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
503 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
505 2018-07-02 Maciej W. Rozycki <macro@mips.com>
508 * mips-dis.c (mips_option_arg_t): New enumeration.
509 (mips_options): New variable.
510 (disassembler_options_mips): New function.
511 (print_mips_disassembler_options): Reimplement in terms of
512 `disassembler_options_mips'.
513 * arm-dis.c (disassembler_options_arm): Adapt to using the
514 `disasm_options_and_args_t' structure.
515 * ppc-dis.c (disassembler_options_powerpc): Likewise.
516 * s390-dis.c (disassembler_options_s390): Likewise.
518 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
520 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
522 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
523 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
524 * testsuite/ld-arm/tls-longplt.d: Likewise.
526 2018-06-29 Tamar Christina <tamar.christina@arm.com>
529 * aarch64-asm-2.c: Regenerate.
530 * aarch64-dis-2.c: Likewise.
531 * aarch64-opc-2.c: Likewise.
532 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
533 * aarch64-opc.c (operand_general_constraint_met_p,
534 aarch64_print_operand): Likewise.
535 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
536 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
538 (AARCH64_OPERANDS): Add Em2.
540 2018-06-26 Nick Clifton <nickc@redhat.com>
542 * po/uk.po: Updated Ukranian translation.
543 * po/de.po: Updated German translation.
544 * po/pt_BR.po: Updated Brazilian Portuguese translation.
546 2018-06-26 Nick Clifton <nickc@redhat.com>
548 * nfp-dis.c: Fix spelling mistake.
550 2018-06-24 Nick Clifton <nickc@redhat.com>
552 * configure: Regenerate.
553 * po/opcodes.pot: Regenerate.
555 2018-06-24 Nick Clifton <nickc@redhat.com>
559 2018-06-19 Tamar Christina <tamar.christina@arm.com>
561 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
562 * aarch64-asm-2.c: Regenerate.
563 * aarch64-dis-2.c: Likewise.
565 2018-06-21 Maciej W. Rozycki <macro@mips.com>
567 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
568 `-M ginv' option description.
570 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
573 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
576 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
578 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
579 * configure.ac: Remove AC_PREREQ.
580 * Makefile.in: Re-generate.
581 * aclocal.m4: Re-generate.
582 * configure: Re-generate.
584 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
586 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
587 mips64r6 descriptors.
588 (parse_mips_ase_option): Handle -Mginv option.
589 (print_mips_disassembler_options): Document -Mginv.
590 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
592 (mips_opcodes): Define ginvi and ginvt.
594 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
595 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
597 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
598 * mips-opc.c (CRC, CRC64): New macros.
599 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
600 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
603 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
606 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
607 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
609 2018-06-06 Alan Modra <amodra@gmail.com>
611 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
612 setjmp. Move init for some other vars later too.
614 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
616 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
617 (dis_private): Add new fields for property section tracking.
618 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
619 (xtensa_instruction_fits): New functions.
620 (fetch_data): Bump minimal fetch size to 4.
621 (print_insn_xtensa): Make struct dis_private static.
622 Load and prepare property table on section change.
623 Don't disassemble literals. Don't disassemble instructions that
624 cross property table boundaries.
626 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
628 * configure: Regenerated.
630 2018-06-01 Jan Beulich <jbeulich@suse.com>
632 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
633 * i386-tbl.h: Re-generate.
635 2018-06-01 Jan Beulich <jbeulich@suse.com>
637 * i386-opc.tbl (sldt, str): Add NoRex64.
638 * i386-tbl.h: Re-generate.
640 2018-06-01 Jan Beulich <jbeulich@suse.com>
642 * i386-opc.tbl (invpcid): Add Oword.
643 * i386-tbl.h: Re-generate.
645 2018-06-01 Alan Modra <amodra@gmail.com>
647 * sysdep.h (_bfd_error_handler): Don't declare.
648 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
649 * rl78-decode.opc: Likewise.
650 * msp430-decode.c: Regenerate.
651 * rl78-decode.c: Regenerate.
653 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
655 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
656 * i386-init.h : Regenerated.
658 2018-05-25 Alan Modra <amodra@gmail.com>
660 * Makefile.in: Regenerate.
661 * po/POTFILES.in: Regenerate.
663 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
665 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
666 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
667 (insert_bab, extract_bab, insert_btab, extract_btab,
668 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
669 (BAT, BBA VBA RBS XB6S): Delete macros.
670 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
671 (BB, BD, RBX, XC6): Update for new macros.
672 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
673 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
674 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
675 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
677 2018-05-18 John Darrington <john@darrington.wattle.id.au>
679 * Makefile.am: Add support for s12z architecture.
680 * configure.ac: Likewise.
681 * disassemble.c: Likewise.
682 * disassemble.h: Likewise.
683 * Makefile.in: Regenerate.
684 * configure: Regenerate.
685 * s12z-dis.c: New file.
688 2018-05-18 Alan Modra <amodra@gmail.com>
690 * nfp-dis.c: Don't #include libbfd.h.
691 (init_nfp3200_priv): Use bfd_get_section_contents.
692 (nit_nfp6000_mecsr_sec): Likewise.
694 2018-05-17 Nick Clifton <nickc@redhat.com>
696 * po/zh_CN.po: Updated simplified Chinese translation.
698 2018-05-16 Tamar Christina <tamar.christina@arm.com>
701 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
702 * aarch64-dis-2.c: Regenerate.
704 2018-05-15 Tamar Christina <tamar.christina@arm.com>
707 * aarch64-asm.c (opintl.h): Include.
708 (aarch64_ins_sysreg): Enforce read/write constraints.
709 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
710 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
711 (F_REG_READ, F_REG_WRITE): New.
712 * aarch64-opc.c (aarch64_print_operand): Generate notes for
714 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
715 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
716 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
717 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
718 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
719 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
720 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
721 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
722 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
723 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
724 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
725 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
726 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
727 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
728 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
729 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
730 msr (F_SYS_WRITE), mrs (F_SYS_READ).
732 2018-05-15 Tamar Christina <tamar.christina@arm.com>
735 * aarch64-dis.c (no_notes: New.
736 (parse_aarch64_dis_option): Support notes.
737 (aarch64_decode_insn, print_operands): Likewise.
738 (print_aarch64_disassembler_options): Document notes.
739 * aarch64-opc.c (aarch64_print_operand): Support notes.
741 2018-05-15 Tamar Christina <tamar.christina@arm.com>
744 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
745 and take error struct.
746 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
747 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
748 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
749 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
750 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
751 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
752 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
753 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
754 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
755 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
756 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
757 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
758 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
759 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
760 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
761 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
762 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
763 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
764 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
765 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
766 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
767 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
768 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
769 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
770 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
771 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
772 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
773 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
774 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
775 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
776 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
777 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
778 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
779 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
780 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
781 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
782 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
783 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
784 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
785 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
786 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
787 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
788 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
789 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
790 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
791 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
792 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
793 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
794 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
795 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
796 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
797 (determine_disassembling_preference, aarch64_decode_insn,
798 print_insn_aarch64_word, print_insn_data): Take errors struct.
799 (print_insn_aarch64): Use errors.
800 * aarch64-asm-2.c: Regenerate.
801 * aarch64-dis-2.c: Regenerate.
802 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
803 boolean in aarch64_insert_operan.
804 (print_operand_extractor): Likewise.
805 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
807 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
809 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
811 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
813 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
815 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
817 * cr16-opc.c (cr16_instruction): Comment typo fix.
818 * hppa-dis.c (print_insn_hppa): Likewise.
820 2018-05-08 Jim Wilson <jimw@sifive.com>
822 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
823 (match_c_slli64, match_srxi_as_c_srxi): New.
824 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
825 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
826 <c.slli, c.srli, c.srai>: Use match_s_slli.
827 <c.slli64, c.srli64, c.srai64>: New.
829 2018-05-08 Alan Modra <amodra@gmail.com>
831 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
832 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
833 partition opcode space for index lookup.
835 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
837 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
838 <insn_length>: ...with this. Update usage.
839 Remove duplicate call to *info->memory_error_func.
841 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
842 H.J. Lu <hongjiu.lu@intel.com>
844 * i386-dis.c (Gva): New.
845 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
846 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
847 (prefix_table): New instructions (see prefix above).
848 (mod_table): New instructions (see prefix above).
849 (OP_G): Handle va_mode.
850 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
852 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
853 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
854 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
855 * i386-opc.tbl: Add movidir{i,64b}.
856 * i386-init.h: Regenerated.
857 * i386-tbl.h: Likewise.
859 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
861 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
863 * i386-opc.h (AddrPrefixOp0): Renamed to ...
864 (AddrPrefixOpReg): This.
865 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
866 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
868 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
870 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
871 (vle_num_opcodes): Likewise.
872 (spe2_num_opcodes): Likewise.
873 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
875 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
876 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
879 2018-05-01 Tamar Christina <tamar.christina@arm.com>
881 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
883 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
885 Makefile.am: Added nfp-dis.c.
886 configure.ac: Added bfd_nfp_arch.
887 disassemble.h: Added print_insn_nfp prototype.
888 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
889 nfp-dis.c: New, for NFP support.
890 po/POTFILES.in: Added nfp-dis.c to the list.
891 Makefile.in: Regenerate.
892 configure: Regenerate.
894 2018-04-26 Jan Beulich <jbeulich@suse.com>
896 * i386-opc.tbl: Fold various non-memory operand AVX512VL
897 templates into their base ones.
898 * i386-tlb.h: Re-generate.
900 2018-04-26 Jan Beulich <jbeulich@suse.com>
902 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
903 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
904 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
905 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
906 * i386-init.h: Re-generate.
908 2018-04-26 Jan Beulich <jbeulich@suse.com>
910 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
911 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
912 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
913 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
915 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
917 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
919 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
920 cpuregzmm, and cpuregmask.
921 * i386-init.h: Re-generate.
922 * i386-tbl.h: Re-generate.
924 2018-04-26 Jan Beulich <jbeulich@suse.com>
926 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
927 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
928 * i386-init.h: Re-generate.
930 2018-04-26 Jan Beulich <jbeulich@suse.com>
932 * i386-gen.c (VexImmExt): Delete.
933 * i386-opc.h (VexImmExt, veximmext): Delete.
934 * i386-opc.tbl: Drop all VexImmExt uses.
935 * i386-tlb.h: Re-generate.
937 2018-04-25 Jan Beulich <jbeulich@suse.com>
939 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
941 * i386-tlb.h: Re-generate.
943 2018-04-25 Tamar Christina <tamar.christina@arm.com>
945 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
947 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
949 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
951 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
952 (cpu_flags): Add CpuCLDEMOTE.
953 * i386-init.h: Regenerate.
954 * i386-opc.h (enum): Add CpuCLDEMOTE,
955 (i386_cpu_flags): Add cpucldemote.
956 * i386-opc.tbl: Add cldemote.
957 * i386-tbl.h: Regenerate.
959 2018-04-16 Alan Modra <amodra@gmail.com>
961 * Makefile.am: Remove sh5 and sh64 support.
962 * configure.ac: Likewise.
963 * disassemble.c: Likewise.
964 * disassemble.h: Likewise.
965 * sh-dis.c: Likewise.
966 * sh64-dis.c: Delete.
967 * sh64-opc.c: Delete.
968 * sh64-opc.h: Delete.
969 * Makefile.in: Regenerate.
970 * configure: Regenerate.
971 * po/POTFILES.in: Regenerate.
973 2018-04-16 Alan Modra <amodra@gmail.com>
975 * Makefile.am: Remove w65 support.
976 * configure.ac: Likewise.
977 * disassemble.c: Likewise.
978 * disassemble.h: Likewise.
981 * Makefile.in: Regenerate.
982 * configure: Regenerate.
983 * po/POTFILES.in: Regenerate.
985 2018-04-16 Alan Modra <amodra@gmail.com>
987 * configure.ac: Remove we32k support.
988 * configure: Regenerate.
990 2018-04-16 Alan Modra <amodra@gmail.com>
992 * Makefile.am: Remove m88k support.
993 * configure.ac: Likewise.
994 * disassemble.c: Likewise.
995 * disassemble.h: Likewise.
996 * m88k-dis.c: Delete.
997 * Makefile.in: Regenerate.
998 * configure: Regenerate.
999 * po/POTFILES.in: Regenerate.
1001 2018-04-16 Alan Modra <amodra@gmail.com>
1003 * Makefile.am: Remove i370 support.
1004 * configure.ac: Likewise.
1005 * disassemble.c: Likewise.
1006 * disassemble.h: Likewise.
1007 * i370-dis.c: Delete.
1008 * i370-opc.c: Delete.
1009 * Makefile.in: Regenerate.
1010 * configure: Regenerate.
1011 * po/POTFILES.in: Regenerate.
1013 2018-04-16 Alan Modra <amodra@gmail.com>
1015 * Makefile.am: Remove h8500 support.
1016 * configure.ac: Likewise.
1017 * disassemble.c: Likewise.
1018 * disassemble.h: Likewise.
1019 * h8500-dis.c: Delete.
1020 * h8500-opc.h: Delete.
1021 * Makefile.in: Regenerate.
1022 * configure: Regenerate.
1023 * po/POTFILES.in: Regenerate.
1025 2018-04-16 Alan Modra <amodra@gmail.com>
1027 * configure.ac: Remove tahoe support.
1028 * configure: Regenerate.
1030 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1032 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1034 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1036 * i386-tbl.h: Regenerated.
1038 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1040 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1041 PREFIX_MOD_1_0FAE_REG_6.
1043 (OP_E_register): Use va_mode.
1044 * i386-dis-evex.h (prefix_table):
1045 New instructions (see prefixes above).
1046 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1047 (cpu_flags): Likewise.
1048 * i386-opc.h (enum): Likewise.
1049 (i386_cpu_flags): Likewise.
1050 * i386-opc.tbl: Add umonitor, umwait, tpause.
1051 * i386-init.h: Regenerate.
1052 * i386-tbl.h: Likewise.
1054 2018-04-11 Alan Modra <amodra@gmail.com>
1056 * opcodes/i860-dis.c: Delete.
1057 * opcodes/i960-dis.c: Delete.
1058 * Makefile.am: Remove i860 and i960 support.
1059 * configure.ac: Likewise.
1060 * disassemble.c: Likewise.
1061 * disassemble.h: Likewise.
1062 * Makefile.in: Regenerate.
1063 * configure: Regenerate.
1064 * po/POTFILES.in: Regenerate.
1066 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1069 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1071 (print_insn): Clear vex instead of vex.evex.
1073 2018-04-04 Nick Clifton <nickc@redhat.com>
1075 * po/es.po: Updated Spanish translation.
1077 2018-03-28 Jan Beulich <jbeulich@suse.com>
1079 * i386-gen.c (opcode_modifiers): Delete VecESize.
1080 * i386-opc.h (VecESize): Delete.
1081 (struct i386_opcode_modifier): Delete vecesize.
1082 * i386-opc.tbl: Drop VecESize.
1083 * i386-tlb.h: Re-generate.
1085 2018-03-28 Jan Beulich <jbeulich@suse.com>
1087 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1088 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1089 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1090 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1091 * i386-tlb.h: Re-generate.
1093 2018-03-28 Jan Beulich <jbeulich@suse.com>
1095 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1097 * i386-tlb.h: Re-generate.
1099 2018-03-28 Jan Beulich <jbeulich@suse.com>
1101 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1102 (vex_len_table): Drop Y for vcvt*2si.
1103 (putop): Replace plain 'Y' handling by abort().
1105 2018-03-28 Nick Clifton <nickc@redhat.com>
1108 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1109 instructions with only a base address register.
1110 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1111 handle AARHC64_OPND_SVE_ADDR_R.
1112 (aarch64_print_operand): Likewise.
1113 * aarch64-asm-2.c: Regenerate.
1114 * aarch64_dis-2.c: Regenerate.
1115 * aarch64-opc-2.c: Regenerate.
1117 2018-03-22 Jan Beulich <jbeulich@suse.com>
1119 * i386-opc.tbl: Drop VecESize from register only insn forms and
1120 memory forms not allowing broadcast.
1121 * i386-tlb.h: Re-generate.
1123 2018-03-22 Jan Beulich <jbeulich@suse.com>
1125 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1126 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1127 sha256*): Drop Disp<N>.
1129 2018-03-22 Jan Beulich <jbeulich@suse.com>
1131 * i386-dis.c (EbndS, bnd_swap_mode): New.
1132 (prefix_table): Use EbndS.
1133 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1134 * i386-opc.tbl (bndmov): Move misplaced Load.
1135 * i386-tlb.h: Re-generate.
1137 2018-03-22 Jan Beulich <jbeulich@suse.com>
1139 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1140 templates allowing memory operands and folded ones for register
1142 * i386-tlb.h: Re-generate.
1144 2018-03-22 Jan Beulich <jbeulich@suse.com>
1146 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1147 256-bit templates. Drop redundant leftover Disp<N>.
1148 * i386-tlb.h: Re-generate.
1150 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1152 * riscv-opc.c (riscv_insn_types): New.
1154 2018-03-13 Nick Clifton <nickc@redhat.com>
1156 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1158 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1160 * i386-opc.tbl: Add Optimize to clr.
1161 * i386-tbl.h: Regenerated.
1163 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1165 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1166 * i386-opc.h (OldGcc): Removed.
1167 (i386_opcode_modifier): Remove oldgcc.
1168 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1169 instructions for old (<= 2.8.1) versions of gcc.
1170 * i386-tbl.h: Regenerated.
1172 2018-03-08 Jan Beulich <jbeulich@suse.com>
1174 * i386-opc.h (EVEXDYN): New.
1175 * i386-opc.tbl: Fold various AVX512VL templates.
1176 * i386-tlb.h: Re-generate.
1178 2018-03-08 Jan Beulich <jbeulich@suse.com>
1180 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1181 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1182 vpexpandd, vpexpandq): Fold AFX512VF templates.
1183 * i386-tlb.h: Re-generate.
1185 2018-03-08 Jan Beulich <jbeulich@suse.com>
1187 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1188 Fold 128- and 256-bit VEX-encoded templates.
1189 * i386-tlb.h: Re-generate.
1191 2018-03-08 Jan Beulich <jbeulich@suse.com>
1193 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1194 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1195 vpexpandd, vpexpandq): Fold AVX512F templates.
1196 * i386-tlb.h: Re-generate.
1198 2018-03-08 Jan Beulich <jbeulich@suse.com>
1200 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1201 64-bit templates. Drop Disp<N>.
1202 * i386-tlb.h: Re-generate.
1204 2018-03-08 Jan Beulich <jbeulich@suse.com>
1206 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1207 and 256-bit templates.
1208 * i386-tlb.h: Re-generate.
1210 2018-03-08 Jan Beulich <jbeulich@suse.com>
1212 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1213 * i386-tlb.h: Re-generate.
1215 2018-03-08 Jan Beulich <jbeulich@suse.com>
1217 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1219 * i386-tlb.h: Re-generate.
1221 2018-03-08 Jan Beulich <jbeulich@suse.com>
1223 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1224 * i386-tlb.h: Re-generate.
1226 2018-03-08 Jan Beulich <jbeulich@suse.com>
1228 * i386-gen.c (opcode_modifiers): Delete FloatD.
1229 * i386-opc.h (FloatD): Delete.
1230 (struct i386_opcode_modifier): Delete floatd.
1231 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1233 * i386-tlb.h: Re-generate.
1235 2018-03-08 Jan Beulich <jbeulich@suse.com>
1237 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1239 2018-03-08 Jan Beulich <jbeulich@suse.com>
1241 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1242 * i386-tlb.h: Re-generate.
1244 2018-03-08 Jan Beulich <jbeulich@suse.com>
1246 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1248 * i386-tlb.h: Re-generate.
1250 2018-03-07 Alan Modra <amodra@gmail.com>
1252 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1254 * disassemble.h (print_insn_rs6000): Delete.
1255 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1256 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1257 (print_insn_rs6000): Delete.
1259 2018-03-03 Alan Modra <amodra@gmail.com>
1261 * sysdep.h (opcodes_error_handler): Define.
1262 (_bfd_error_handler): Declare.
1263 * Makefile.am: Remove stray #.
1264 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1266 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1267 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1268 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1269 opcodes_error_handler to print errors. Standardize error messages.
1270 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1271 and include opintl.h.
1272 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1273 * i386-gen.c: Standardize error messages.
1274 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1275 * Makefile.in: Regenerate.
1276 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1277 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1278 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1279 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1280 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1281 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1282 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1283 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1284 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1285 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1286 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1287 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1288 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1290 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1292 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1293 vpsub[bwdq] instructions.
1294 * i386-tbl.h: Regenerated.
1296 2018-03-01 Alan Modra <amodra@gmail.com>
1298 * configure.ac (ALL_LINGUAS): Sort.
1299 * configure: Regenerate.
1301 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1303 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1304 macro by assignements.
1306 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1309 * i386-gen.c (opcode_modifiers): Add Optimize.
1310 * i386-opc.h (Optimize): New enum.
1311 (i386_opcode_modifier): Add optimize.
1312 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1313 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1314 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1315 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1316 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1318 * i386-tbl.h: Regenerated.
1320 2018-02-26 Alan Modra <amodra@gmail.com>
1322 * crx-dis.c (getregliststring): Allocate a large enough buffer
1323 to silence false positive gcc8 warning.
1325 2018-02-22 Shea Levy <shea@shealevy.com>
1327 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1329 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1331 * i386-opc.tbl: Add {rex},
1332 * i386-tbl.h: Regenerated.
1334 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1336 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1337 (mips16_opcodes): Replace `M' with `m' for "restore".
1339 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1341 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1343 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1345 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1346 variable to `function_index'.
1348 2018-02-13 Nick Clifton <nickc@redhat.com>
1351 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1352 about truncation of printing.
1354 2018-02-12 Henry Wong <henry@stuffedcow.net>
1356 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1358 2018-02-05 Nick Clifton <nickc@redhat.com>
1360 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1362 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1364 * i386-dis.c (enum): Add pconfig.
1365 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1366 (cpu_flags): Add CpuPCONFIG.
1367 * i386-opc.h (enum): Add CpuPCONFIG.
1368 (i386_cpu_flags): Add cpupconfig.
1369 * i386-opc.tbl: Add PCONFIG instruction.
1370 * i386-init.h: Regenerate.
1371 * i386-tbl.h: Likewise.
1373 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1375 * i386-dis.c (enum): Add PREFIX_0F09.
1376 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1377 (cpu_flags): Add CpuWBNOINVD.
1378 * i386-opc.h (enum): Add CpuWBNOINVD.
1379 (i386_cpu_flags): Add cpuwbnoinvd.
1380 * i386-opc.tbl: Add WBNOINVD instruction.
1381 * i386-init.h: Regenerate.
1382 * i386-tbl.h: Likewise.
1384 2018-01-17 Jim Wilson <jimw@sifive.com>
1386 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1388 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1390 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1391 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1392 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1393 (cpu_flags): Add CpuIBT, CpuSHSTK.
1394 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1395 (i386_cpu_flags): Add cpuibt, cpushstk.
1396 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1397 * i386-init.h: Regenerate.
1398 * i386-tbl.h: Likewise.
1400 2018-01-16 Nick Clifton <nickc@redhat.com>
1402 * po/pt_BR.po: Updated Brazilian Portugese translation.
1403 * po/de.po: Updated German translation.
1405 2018-01-15 Jim Wilson <jimw@sifive.com>
1407 * riscv-opc.c (match_c_nop): New.
1408 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1410 2018-01-15 Nick Clifton <nickc@redhat.com>
1412 * po/uk.po: Updated Ukranian translation.
1414 2018-01-13 Nick Clifton <nickc@redhat.com>
1416 * po/opcodes.pot: Regenerated.
1418 2018-01-13 Nick Clifton <nickc@redhat.com>
1420 * configure: Regenerate.
1422 2018-01-13 Nick Clifton <nickc@redhat.com>
1424 2.30 branch created.
1426 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1428 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1429 * i386-tbl.h: Regenerate.
1431 2018-01-10 Jan Beulich <jbeulich@suse.com>
1433 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1434 * i386-tbl.h: Re-generate.
1436 2018-01-10 Jan Beulich <jbeulich@suse.com>
1438 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1439 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1440 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1441 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1442 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1443 Disp8MemShift of AVX512VL forms.
1444 * i386-tbl.h: Re-generate.
1446 2018-01-09 Jim Wilson <jimw@sifive.com>
1448 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1449 then the hi_addr value is zero.
1451 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1453 * arm-dis.c (arm_opcodes): Add csdb.
1454 (thumb32_opcodes): Add csdb.
1456 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1458 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1459 * aarch64-asm-2.c: Regenerate.
1460 * aarch64-dis-2.c: Regenerate.
1461 * aarch64-opc-2.c: Regenerate.
1463 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1466 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1467 Remove AVX512 vmovd with 64-bit operands.
1468 * i386-tbl.h: Regenerated.
1470 2018-01-05 Jim Wilson <jimw@sifive.com>
1472 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1475 2018-01-03 Alan Modra <amodra@gmail.com>
1477 Update year range in copyright notice of all files.
1479 2018-01-02 Jan Beulich <jbeulich@suse.com>
1481 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1482 and OPERAND_TYPE_REGZMM entries.
1484 For older changes see ChangeLog-2017
1486 Copyright (C) 2018 Free Software Foundation, Inc.
1488 Copying and distribution of this file, with or without modification,
1489 are permitted in any medium without royalty provided the copyright
1490 notice and this notice are preserved.
1496 version-control: never