1 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2 Michael Collison <michael.collison@arm.com>
4 * arm-dis.c (enum mve_instructions): Add new instructions.
5 (is_mve_encoding_conflict): Handle new instructions.
6 (is_mve_unpredictable): Likewise.
7 (print_mve_rotate): Likewise.
8 (print_mve_size): Likewise.
9 (print_insn_mve): Likewise.
11 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
12 Michael Collison <michael.collison@arm.com>
14 * arm-dis.c (enum mve_instructions): Add new instructions.
15 (is_mve_encoding_conflict): Handle new instructions.
16 (is_mve_unpredictable): Likewise.
17 (print_mve_size): Likewise.
18 (print_insn_mve): Likewise.
20 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
21 Michael Collison <michael.collison@arm.com>
23 * arm-dis.c (enum mve_instructions): Add new instructions.
24 (enum mve_undefined): Add new reasons.
25 (is_mve_encoding_conflict): Handle new instructions.
26 (is_mve_undefined): Likewise.
27 (is_mve_unpredictable): Likewise.
28 (print_mve_undefined): Likewise.
29 (print_mve_size): Likewise.
30 (print_insn_mve): Likewise.
32 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
33 Michael Collison <michael.collison@arm.com>
35 * arm-dis.c (enum mve_instructions): Add new instructions.
36 (is_mve_encoding_conflict): Handle new instructions.
37 (is_mve_undefined): Likewise.
38 (is_mve_unpredictable): Likewise.
39 (print_mve_size): Likewise.
40 (print_insn_mve): Likewise.
42 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
43 Michael Collison <michael.collison@arm.com>
45 * arm-dis.c (enum mve_instructions): Add new instructions.
46 (enum mve_unpredictable): Add new reasons.
47 (enum mve_undefined): Likewise.
48 (is_mve_okay_in_it): Handle new isntructions.
49 (is_mve_encoding_conflict): Likewise.
50 (is_mve_undefined): Likewise.
51 (is_mve_unpredictable): Likewise.
52 (print_mve_vmov_index): Likewise.
53 (print_simd_imm8): Likewise.
54 (print_mve_undefined): Likewise.
55 (print_mve_unpredictable): Likewise.
56 (print_mve_size): Likewise.
57 (print_insn_mve): Likewise.
59 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
60 Michael Collison <michael.collison@arm.com>
62 * arm-dis.c (enum mve_instructions): Add new instructions.
63 (enum mve_unpredictable): Add new reasons.
64 (enum mve_undefined): Likewise.
65 (is_mve_encoding_conflict): Handle new instructions.
66 (is_mve_undefined): Likewise.
67 (is_mve_unpredictable): Likewise.
68 (print_mve_undefined): Likewise.
69 (print_mve_unpredictable): Likewise.
70 (print_mve_rounding_mode): Likewise.
71 (print_mve_vcvt_size): Likewise.
72 (print_mve_size): Likewise.
73 (print_insn_mve): Likewise.
75 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
76 Michael Collison <michael.collison@arm.com>
78 * arm-dis.c (enum mve_instructions): Add new instructions.
79 (enum mve_unpredictable): Add new reasons.
80 (enum mve_undefined): Likewise.
81 (is_mve_undefined): Handle new instructions.
82 (is_mve_unpredictable): Likewise.
83 (print_mve_undefined): Likewise.
84 (print_mve_unpredictable): Likewise.
85 (print_mve_size): Likewise.
86 (print_insn_mve): Likewise.
88 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
89 Michael Collison <michael.collison@arm.com>
91 * arm-dis.c (enum mve_instructions): Add new instructions.
92 (enum mve_undefined): Add new reasons.
93 (insns): Add new instructions.
94 (is_mve_encoding_conflict):
95 (print_mve_vld_str_addr): New print function.
96 (is_mve_undefined): Handle new instructions.
97 (is_mve_unpredictable): Likewise.
98 (print_mve_undefined): Likewise.
99 (print_mve_size): Likewise.
100 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
101 (print_insn_mve): Handle new operands.
103 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
104 Michael Collison <michael.collison@arm.com>
106 * arm-dis.c (enum mve_instructions): Add new instructions.
107 (enum mve_unpredictable): Add new reasons.
108 (is_mve_encoding_conflict): Handle new instructions.
109 (is_mve_unpredictable): Likewise.
110 (mve_opcodes): Add new instructions.
111 (print_mve_unpredictable): Handle new reasons.
112 (print_mve_register_blocks): New print function.
113 (print_mve_size): Handle new instructions.
114 (print_insn_mve): Likewise.
116 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
117 Michael Collison <michael.collison@arm.com>
119 * arm-dis.c (enum mve_instructions): Add new instructions.
120 (enum mve_unpredictable): Add new reasons.
121 (enum mve_undefined): Likewise.
122 (is_mve_encoding_conflict): Handle new instructions.
123 (is_mve_undefined): Likewise.
124 (is_mve_unpredictable): Likewise.
125 (coprocessor_opcodes): Move NEON VDUP from here...
126 (neon_opcodes): ... to here.
127 (mve_opcodes): Add new instructions.
128 (print_mve_undefined): Handle new reasons.
129 (print_mve_unpredictable): Likewise.
130 (print_mve_size): Handle new instructions.
131 (print_insn_neon): Handle vdup.
132 (print_insn_mve): Handle new operands.
134 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
135 Michael Collison <michael.collison@arm.com>
137 * arm-dis.c (enum mve_instructions): Add new instructions.
138 (enum mve_unpredictable): Add new values.
139 (mve_opcodes): Add new instructions.
140 (vec_condnames): New array with vector conditions.
141 (mve_predicatenames): New array with predicate suffixes.
142 (mve_vec_sizename): New array with vector sizes.
143 (enum vpt_pred_state): New enum with vector predication states.
144 (struct vpt_block): New struct type for vpt blocks.
145 (vpt_block_state): Global struct to keep track of state.
146 (mve_extract_pred_mask): New helper function.
147 (num_instructions_vpt_block): Likewise.
148 (mark_outside_vpt_block): Likewise.
149 (mark_inside_vpt_block): Likewise.
150 (invert_next_predicate_state): Likewise.
151 (update_next_predicate_state): Likewise.
152 (update_vpt_block_state): Likewise.
153 (is_vpt_instruction): Likewise.
154 (is_mve_encoding_conflict): Add entries for new instructions.
155 (is_mve_unpredictable): Likewise.
156 (print_mve_unpredictable): Handle new cases.
157 (print_instruction_predicate): Likewise.
158 (print_mve_size): New function.
159 (print_vec_condition): New function.
160 (print_insn_mve): Handle vpt blocks and new print operands.
162 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
164 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
165 8, 14 and 15 for Armv8.1-M Mainline.
167 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
168 Michael Collison <michael.collison@arm.com>
170 * arm-dis.c (enum mve_instructions): New enum.
171 (enum mve_unpredictable): Likewise.
172 (enum mve_undefined): Likewise.
173 (struct mopcode32): New struct.
174 (is_mve_okay_in_it): New function.
175 (is_mve_architecture): Likewise.
176 (arm_decode_field): Likewise.
177 (arm_decode_field_multiple): Likewise.
178 (is_mve_encoding_conflict): Likewise.
179 (is_mve_undefined): Likewise.
180 (is_mve_unpredictable): Likewise.
181 (print_mve_undefined): Likewise.
182 (print_mve_unpredictable): Likewise.
183 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
184 (print_insn_mve): New function.
185 (print_insn_thumb32): Handle MVE architecture.
186 (select_arm_features): Force thumb for Armv8.1-m Mainline.
188 2019-05-10 Nick Clifton <nickc@redhat.com>
191 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
192 end of the table prematurely.
194 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
196 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
199 2019-05-11 Alan Modra <amodra@gmail.com>
201 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
202 when -Mraw is in effect.
204 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
206 * aarch64-dis-2.c: Regenerate.
207 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
208 (OP_SVE_BBB): New variant set.
209 (OP_SVE_DDDD): New variant set.
210 (OP_SVE_HHH): New variant set.
211 (OP_SVE_HHHU): New variant set.
212 (OP_SVE_SSS): New variant set.
213 (OP_SVE_SSSU): New variant set.
214 (OP_SVE_SHH): New variant set.
215 (OP_SVE_SBBU): New variant set.
216 (OP_SVE_DSS): New variant set.
217 (OP_SVE_DHHU): New variant set.
218 (OP_SVE_VMV_HSD_BHS): New variant set.
219 (OP_SVE_VVU_HSD_BHS): New variant set.
220 (OP_SVE_VVVU_SD_BH): New variant set.
221 (OP_SVE_VVVU_BHSD): New variant set.
222 (OP_SVE_VVV_QHD_DBS): New variant set.
223 (OP_SVE_VVV_HSD_BHS): New variant set.
224 (OP_SVE_VVV_HSD_BHS2): New variant set.
225 (OP_SVE_VVV_BHS_HSD): New variant set.
226 (OP_SVE_VV_BHS_HSD): New variant set.
227 (OP_SVE_VVV_SD): New variant set.
228 (OP_SVE_VVU_BHS_HSD): New variant set.
229 (OP_SVE_VZVV_SD): New variant set.
230 (OP_SVE_VZVV_BH): New variant set.
231 (OP_SVE_VZV_SD): New variant set.
232 (aarch64_opcode_table): Add sve2 instructions.
234 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
236 * aarch64-asm-2.c: Regenerated.
237 * aarch64-dis-2.c: Regenerated.
238 * aarch64-opc-2.c: Regenerated.
239 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
240 for SVE_SHLIMM_UNPRED_22.
241 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
242 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
245 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
247 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
248 sve_size_tsz_bhs iclass encode.
249 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
250 sve_size_tsz_bhs iclass decode.
252 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
254 * aarch64-asm-2.c: Regenerated.
255 * aarch64-dis-2.c: Regenerated.
256 * aarch64-opc-2.c: Regenerated.
257 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
258 for SVE_Zm4_11_INDEX.
259 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
260 (fields): Handle SVE_i2h field.
261 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
262 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
264 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
266 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
267 sve_shift_tsz_bhsd iclass encode.
268 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
269 sve_shift_tsz_bhsd iclass decode.
271 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
273 * aarch64-asm-2.c: Regenerated.
274 * aarch64-dis-2.c: Regenerated.
275 * aarch64-opc-2.c: Regenerated.
276 * aarch64-asm.c (aarch64_ins_sve_shrimm):
277 (aarch64_encode_variant_using_iclass): Handle
278 sve_shift_tsz_hsd iclass encode.
279 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
280 sve_shift_tsz_hsd iclass decode.
281 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
282 for SVE_SHRIMM_UNPRED_22.
283 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
284 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
287 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
289 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
290 sve_size_013 iclass encode.
291 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
292 sve_size_013 iclass decode.
294 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
296 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
297 sve_size_bh iclass encode.
298 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
299 sve_size_bh iclass decode.
301 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
303 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
304 sve_size_sd2 iclass encode.
305 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
306 sve_size_sd2 iclass decode.
307 * aarch64-opc.c (fields): Handle SVE_sz2 field.
308 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
310 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
312 * aarch64-asm-2.c: Regenerated.
313 * aarch64-dis-2.c: Regenerated.
314 * aarch64-opc-2.c: Regenerated.
315 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
317 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
318 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
320 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
322 * aarch64-asm-2.c: Regenerated.
323 * aarch64-dis-2.c: Regenerated.
324 * aarch64-opc-2.c: Regenerated.
325 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
326 for SVE_Zm3_11_INDEX.
327 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
328 (fields): Handle SVE_i3l and SVE_i3h2 fields.
329 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
331 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
333 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
335 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
336 sve_size_hsd2 iclass encode.
337 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
338 sve_size_hsd2 iclass decode.
339 * aarch64-opc.c (fields): Handle SVE_size field.
340 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
342 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
344 * aarch64-asm-2.c: Regenerated.
345 * aarch64-dis-2.c: Regenerated.
346 * aarch64-opc-2.c: Regenerated.
347 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
349 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
350 (fields): Handle SVE_rot3 field.
351 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
352 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
354 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
356 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
359 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
362 (aarch64_feature_sve2, aarch64_feature_sve2aes,
363 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
364 aarch64_feature_sve2bitperm): New feature sets.
365 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
366 for feature set addresses.
367 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
368 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
370 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
371 Faraz Shahbazker <fshahbazker@wavecomp.com>
373 * mips-dis.c (mips_calculate_combination_ases): Add ISA
374 argument and set ASE_EVA_R6 appropriately.
375 (set_default_mips_dis_options): Pass ISA to above.
376 (parse_mips_dis_option): Likewise.
377 * mips-opc.c (EVAR6): New macro.
378 (mips_builtin_opcodes): Add llwpe, scwpe.
380 2019-05-01 Sudakshina Das <sudi.das@arm.com>
382 * aarch64-asm-2.c: Regenerated.
383 * aarch64-dis-2.c: Regenerated.
384 * aarch64-opc-2.c: Regenerated.
385 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
386 AARCH64_OPND_TME_UIMM16.
387 (aarch64_print_operand): Likewise.
388 * aarch64-tbl.h (QL_IMM_NIL): New.
391 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
393 2019-04-29 John Darrington <john@darrington.wattle.id.au>
395 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
397 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
398 Faraz Shahbazker <fshahbazker@wavecomp.com>
400 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
402 2019-04-24 John Darrington <john@darrington.wattle.id.au>
404 * s12z-opc.h: Add extern "C" bracketing to help
405 users who wish to use this interface in c++ code.
407 2019-04-24 John Darrington <john@darrington.wattle.id.au>
409 * s12z-opc.c (bm_decode): Handle bit map operations with the
412 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
414 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
415 specifier. Add entries for VLDR and VSTR of system registers.
416 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
417 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
418 of %J and %K format specifier.
420 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
422 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
423 Add new entries for VSCCLRM instruction.
424 (print_insn_coprocessor): Handle new %C format control code.
426 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
428 * arm-dis.c (enum isa): New enum.
429 (struct sopcode32): New structure.
430 (coprocessor_opcodes): change type of entries to struct sopcode32 and
431 set isa field of all current entries to ANY.
432 (print_insn_coprocessor): Change type of insn to struct sopcode32.
433 Only match an entry if its isa field allows the current mode.
435 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
437 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
439 (print_insn_thumb32): Add logic to print %n CLRM register list.
441 2019-04-15 Sudakshina Das <sudi.das@arm.com>
443 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
446 2019-04-15 Sudakshina Das <sudi.das@arm.com>
448 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
449 (print_insn_thumb32): Edit the switch case for %Z.
451 2019-04-15 Sudakshina Das <sudi.das@arm.com>
453 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
455 2019-04-15 Sudakshina Das <sudi.das@arm.com>
457 * arm-dis.c (thumb32_opcodes): New instruction bfl.
459 2019-04-15 Sudakshina Das <sudi.das@arm.com>
461 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
463 2019-04-15 Sudakshina Das <sudi.das@arm.com>
465 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
466 Arm register with r13 and r15 unpredictable.
467 (thumb32_opcodes): New instructions for bfx and bflx.
469 2019-04-15 Sudakshina Das <sudi.das@arm.com>
471 * arm-dis.c (thumb32_opcodes): New instructions for bf.
473 2019-04-15 Sudakshina Das <sudi.das@arm.com>
475 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
477 2019-04-15 Sudakshina Das <sudi.das@arm.com>
479 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
481 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
483 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
485 2019-04-12 John Darrington <john@darrington.wattle.id.au>
487 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
488 "optr". ("operator" is a reserved word in c++).
490 2019-04-11 Sudakshina Das <sudi.das@arm.com>
492 * aarch64-opc.c (aarch64_print_operand): Add case for
494 (verify_constraints): Likewise.
495 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
496 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
497 to accept Rt|SP as first operand.
498 (AARCH64_OPERANDS): Add new Rt_SP.
499 * aarch64-asm-2.c: Regenerated.
500 * aarch64-dis-2.c: Regenerated.
501 * aarch64-opc-2.c: Regenerated.
503 2019-04-11 Sudakshina Das <sudi.das@arm.com>
505 * aarch64-asm-2.c: Regenerated.
506 * aarch64-dis-2.c: Likewise.
507 * aarch64-opc-2.c: Likewise.
508 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
510 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
512 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
514 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
516 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
517 * i386-init.h: Regenerated.
519 2019-04-07 Alan Modra <amodra@gmail.com>
521 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
522 op_separator to control printing of spaces, comma and parens
523 rather than need_comma, need_paren and spaces vars.
525 2019-04-07 Alan Modra <amodra@gmail.com>
528 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
529 (print_insn_neon, print_insn_arm): Likewise.
531 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
533 * i386-dis-evex.h (evex_table): Updated to support BF16
535 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
536 and EVEX_W_0F3872_P_3.
537 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
538 (cpu_flags): Add bitfield for CpuAVX512_BF16.
539 * i386-opc.h (enum): Add CpuAVX512_BF16.
540 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
541 * i386-opc.tbl: Add AVX512 BF16 instructions.
542 * i386-init.h: Regenerated.
543 * i386-tbl.h: Likewise.
545 2019-04-05 Alan Modra <amodra@gmail.com>
547 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
548 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
549 to favour printing of "-" branch hint when using the "y" bit.
550 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
552 2019-04-05 Alan Modra <amodra@gmail.com>
554 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
555 opcode until first operand is output.
557 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
560 * ppc-opc.c (valid_bo_pre_v2): Add comments.
561 (valid_bo_post_v2): Add support for 'at' branch hints.
562 (insert_bo): Only error on branch on ctr.
563 (get_bo_hint_mask): New function.
564 (insert_boe): Add new 'branch_taken' formal argument. Add support
565 for inserting 'at' branch hints.
566 (extract_boe): Add new 'branch_taken' formal argument. Add support
567 for extracting 'at' branch hints.
568 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
569 (BOE): Delete operand.
570 (BOM, BOP): New operands.
572 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
573 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
574 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
575 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
576 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
577 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
578 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
579 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
580 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
581 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
582 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
583 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
584 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
585 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
586 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
587 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
588 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
589 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
590 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
591 bttarl+>: New extended mnemonics.
593 2019-03-28 Alan Modra <amodra@gmail.com>
596 * ppc-opc.c (BTF): Define.
597 (powerpc_opcodes): Use for mtfsb*.
598 * ppc-dis.c (print_insn_powerpc): Print fields with both
599 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
601 2019-03-25 Tamar Christina <tamar.christina@arm.com>
603 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
604 (mapping_symbol_for_insn): Implement new algorithm.
605 (print_insn): Remove duplicate code.
607 2019-03-25 Tamar Christina <tamar.christina@arm.com>
609 * aarch64-dis.c (print_insn_aarch64):
612 2019-03-25 Tamar Christina <tamar.christina@arm.com>
614 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
617 2019-03-25 Tamar Christina <tamar.christina@arm.com>
619 * aarch64-dis.c (last_stop_offset): New.
620 (print_insn_aarch64): Use stop_offset.
622 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
625 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
627 * i386-init.h: Regenerated.
629 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
632 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
633 vmovdqu16, vmovdqu32 and vmovdqu64.
634 * i386-tbl.h: Regenerated.
636 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
638 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
639 from vstrszb, vstrszh, and vstrszf.
641 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
643 * s390-opc.txt: Add instruction descriptions.
645 2019-02-08 Jim Wilson <jimw@sifive.com>
647 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
650 2019-02-07 Tamar Christina <tamar.christina@arm.com>
652 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
654 2019-02-07 Tamar Christina <tamar.christina@arm.com>
657 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
658 * aarch64-opc.c (verify_elem_sd): New.
659 (fields): Add FLD_sz entr.
660 * aarch64-tbl.h (_SIMD_INSN): New.
661 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
662 fmulx scalar and vector by element isns.
664 2019-02-07 Nick Clifton <nickc@redhat.com>
666 * po/sv.po: Updated Swedish translation.
668 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
670 * s390-mkopc.c (main): Accept arch13 as cpu string.
671 * s390-opc.c: Add new instruction formats and instruction opcode
673 * s390-opc.txt: Add new arch13 instructions.
675 2019-01-25 Sudakshina Das <sudi.das@arm.com>
677 * aarch64-tbl.h (QL_LDST_AT): Update macro.
678 (aarch64_opcode): Change encoding for stg, stzg
680 * aarch64-asm-2.c: Regenerated.
681 * aarch64-dis-2.c: Regenerated.
682 * aarch64-opc-2.c: Regenerated.
684 2019-01-25 Sudakshina Das <sudi.das@arm.com>
686 * aarch64-asm-2.c: Regenerated.
687 * aarch64-dis-2.c: Likewise.
688 * aarch64-opc-2.c: Likewise.
689 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
691 2019-01-25 Sudakshina Das <sudi.das@arm.com>
692 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
694 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
695 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
696 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
697 * aarch64-dis.h (ext_addr_simple_2): Likewise.
698 * aarch64-opc.c (operand_general_constraint_met_p): Remove
699 case for ldstgv_indexed.
700 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
701 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
702 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
703 * aarch64-asm-2.c: Regenerated.
704 * aarch64-dis-2.c: Regenerated.
705 * aarch64-opc-2.c: Regenerated.
707 2019-01-23 Nick Clifton <nickc@redhat.com>
709 * po/pt_BR.po: Updated Brazilian Portuguese translation.
711 2019-01-21 Nick Clifton <nickc@redhat.com>
713 * po/de.po: Updated German translation.
714 * po/uk.po: Updated Ukranian translation.
716 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
717 * mips-dis.c (mips_arch_choices): Fix typo in
718 gs464, gs464e and gs264e descriptors.
720 2019-01-19 Nick Clifton <nickc@redhat.com>
722 * configure: Regenerate.
723 * po/opcodes.pot: Regenerate.
725 2018-06-24 Nick Clifton <nickc@redhat.com>
729 2019-01-09 John Darrington <john@darrington.wattle.id.au>
731 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
733 -dis.c (opr_emit_disassembly): Do not omit an index if it is
736 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
738 * configure: Regenerate.
740 2019-01-07 Alan Modra <amodra@gmail.com>
742 * configure: Regenerate.
743 * po/POTFILES.in: Regenerate.
745 2019-01-03 John Darrington <john@darrington.wattle.id.au>
747 * s12z-opc.c: New file.
748 * s12z-opc.h: New file.
749 * s12z-dis.c: Removed all code not directly related to display
750 of instructions. Used the interface provided by the new files
752 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
753 * Makefile.in: Regenerate.
754 * configure.ac (bfd_s12z_arch): Correct the dependencies.
755 * configure: Regenerate.
757 2019-01-01 Alan Modra <amodra@gmail.com>
759 Update year range in copyright notice of all files.
761 For older changes see ChangeLog-2018
763 Copyright (C) 2019 Free Software Foundation, Inc.
765 Copying and distribution of this file, with or without modification,
766 are permitted in any medium without royalty provided the copyright
767 notice and this notice are preserved.
773 version-control: never