1 2018-05-17 Nick Clifton <nickc@redhat.com>
3 * po/zh_CN.po: Updated simplified Chinese translation.
5 2018-05-16 Tamar Christina <tamar.christina@arm.com>
8 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
9 * aarch64-dis-2.c: Regenerate.
11 2018-05-15 Tamar Christina <tamar.christina@arm.com>
14 * aarch64-asm.c (opintl.h): Include.
15 (aarch64_ins_sysreg): Enforce read/write constraints.
16 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
17 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
18 (F_REG_READ, F_REG_WRITE): New.
19 * aarch64-opc.c (aarch64_print_operand): Generate notes for
21 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
22 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
23 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
24 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
25 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
26 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
27 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
28 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
29 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
30 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
31 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
32 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
33 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
34 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
35 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
36 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
37 msr (F_SYS_WRITE), mrs (F_SYS_READ).
39 2018-05-15 Tamar Christina <tamar.christina@arm.com>
42 * aarch64-dis.c (no_notes: New.
43 (parse_aarch64_dis_option): Support notes.
44 (aarch64_decode_insn, print_operands): Likewise.
45 (print_aarch64_disassembler_options): Document notes.
46 * aarch64-opc.c (aarch64_print_operand): Support notes.
48 2018-05-15 Tamar Christina <tamar.christina@arm.com>
51 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
52 and take error struct.
53 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
54 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
55 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
56 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
57 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
58 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
59 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
60 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
61 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
62 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
63 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
64 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
65 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
66 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
67 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
68 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
69 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
70 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
71 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
72 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
73 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
74 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
75 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
76 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
77 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
78 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
79 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
80 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
81 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
82 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
83 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
84 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
85 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
86 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
87 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
88 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
89 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
90 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
91 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
92 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
93 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
94 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
95 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
96 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
97 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
98 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
99 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
100 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
101 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
102 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
103 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
104 (determine_disassembling_preference, aarch64_decode_insn,
105 print_insn_aarch64_word, print_insn_data): Take errors struct.
106 (print_insn_aarch64): Use errors.
107 * aarch64-asm-2.c: Regenerate.
108 * aarch64-dis-2.c: Regenerate.
109 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
110 boolean in aarch64_insert_operan.
111 (print_operand_extractor): Likewise.
112 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
114 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
116 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
118 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
120 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
122 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
124 * cr16-opc.c (cr16_instruction): Comment typo fix.
125 * hppa-dis.c (print_insn_hppa): Likewise.
127 2018-05-08 Jim Wilson <jimw@sifive.com>
129 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
130 (match_c_slli64, match_srxi_as_c_srxi): New.
131 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
132 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
133 <c.slli, c.srli, c.srai>: Use match_s_slli.
134 <c.slli64, c.srli64, c.srai64>: New.
136 2018-05-08 Alan Modra <amodra@gmail.com>
138 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
139 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
140 partition opcode space for index lookup.
142 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
144 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
145 <insn_length>: ...with this. Update usage.
146 Remove duplicate call to *info->memory_error_func.
148 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
149 H.J. Lu <hongjiu.lu@intel.com>
151 * i386-dis.c (Gva): New.
152 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
153 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
154 (prefix_table): New instructions (see prefix above).
155 (mod_table): New instructions (see prefix above).
156 (OP_G): Handle va_mode.
157 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
159 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
160 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
161 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
162 * i386-opc.tbl: Add movidir{i,64b}.
163 * i386-init.h: Regenerated.
164 * i386-tbl.h: Likewise.
166 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
168 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
170 * i386-opc.h (AddrPrefixOp0): Renamed to ...
171 (AddrPrefixOpReg): This.
172 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
173 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
175 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
177 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
178 (vle_num_opcodes): Likewise.
179 (spe2_num_opcodes): Likewise.
180 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
182 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
183 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
186 2018-05-01 Tamar Christina <tamar.christina@arm.com>
188 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
190 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
192 Makefile.am: Added nfp-dis.c.
193 configure.ac: Added bfd_nfp_arch.
194 disassemble.h: Added print_insn_nfp prototype.
195 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
196 nfp-dis.c: New, for NFP support.
197 po/POTFILES.in: Added nfp-dis.c to the list.
198 Makefile.in: Regenerate.
199 configure: Regenerate.
201 2018-04-26 Jan Beulich <jbeulich@suse.com>
203 * i386-opc.tbl: Fold various non-memory operand AVX512VL
204 templates into their base ones.
205 * i386-tlb.h: Re-generate.
207 2018-04-26 Jan Beulich <jbeulich@suse.com>
209 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
210 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
211 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
212 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
213 * i386-init.h: Re-generate.
215 2018-04-26 Jan Beulich <jbeulich@suse.com>
217 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
218 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
219 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
220 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
222 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
224 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
226 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
227 cpuregzmm, and cpuregmask.
228 * i386-init.h: Re-generate.
229 * i386-tbl.h: Re-generate.
231 2018-04-26 Jan Beulich <jbeulich@suse.com>
233 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
234 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
235 * i386-init.h: Re-generate.
237 2018-04-26 Jan Beulich <jbeulich@suse.com>
239 * i386-gen.c (VexImmExt): Delete.
240 * i386-opc.h (VexImmExt, veximmext): Delete.
241 * i386-opc.tbl: Drop all VexImmExt uses.
242 * i386-tlb.h: Re-generate.
244 2018-04-25 Jan Beulich <jbeulich@suse.com>
246 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
248 * i386-tlb.h: Re-generate.
250 2018-04-25 Tamar Christina <tamar.christina@arm.com>
252 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
254 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
256 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
258 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
259 (cpu_flags): Add CpuCLDEMOTE.
260 * i386-init.h: Regenerate.
261 * i386-opc.h (enum): Add CpuCLDEMOTE,
262 (i386_cpu_flags): Add cpucldemote.
263 * i386-opc.tbl: Add cldemote.
264 * i386-tbl.h: Regenerate.
266 2018-04-16 Alan Modra <amodra@gmail.com>
268 * Makefile.am: Remove sh5 and sh64 support.
269 * configure.ac: Likewise.
270 * disassemble.c: Likewise.
271 * disassemble.h: Likewise.
272 * sh-dis.c: Likewise.
273 * sh64-dis.c: Delete.
274 * sh64-opc.c: Delete.
275 * sh64-opc.h: Delete.
276 * Makefile.in: Regenerate.
277 * configure: Regenerate.
278 * po/POTFILES.in: Regenerate.
280 2018-04-16 Alan Modra <amodra@gmail.com>
282 * Makefile.am: Remove w65 support.
283 * configure.ac: Likewise.
284 * disassemble.c: Likewise.
285 * disassemble.h: Likewise.
288 * Makefile.in: Regenerate.
289 * configure: Regenerate.
290 * po/POTFILES.in: Regenerate.
292 2018-04-16 Alan Modra <amodra@gmail.com>
294 * configure.ac: Remove we32k support.
295 * configure: Regenerate.
297 2018-04-16 Alan Modra <amodra@gmail.com>
299 * Makefile.am: Remove m88k support.
300 * configure.ac: Likewise.
301 * disassemble.c: Likewise.
302 * disassemble.h: Likewise.
303 * m88k-dis.c: Delete.
304 * Makefile.in: Regenerate.
305 * configure: Regenerate.
306 * po/POTFILES.in: Regenerate.
308 2018-04-16 Alan Modra <amodra@gmail.com>
310 * Makefile.am: Remove i370 support.
311 * configure.ac: Likewise.
312 * disassemble.c: Likewise.
313 * disassemble.h: Likewise.
314 * i370-dis.c: Delete.
315 * i370-opc.c: Delete.
316 * Makefile.in: Regenerate.
317 * configure: Regenerate.
318 * po/POTFILES.in: Regenerate.
320 2018-04-16 Alan Modra <amodra@gmail.com>
322 * Makefile.am: Remove h8500 support.
323 * configure.ac: Likewise.
324 * disassemble.c: Likewise.
325 * disassemble.h: Likewise.
326 * h8500-dis.c: Delete.
327 * h8500-opc.h: Delete.
328 * Makefile.in: Regenerate.
329 * configure: Regenerate.
330 * po/POTFILES.in: Regenerate.
332 2018-04-16 Alan Modra <amodra@gmail.com>
334 * configure.ac: Remove tahoe support.
335 * configure: Regenerate.
337 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
339 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
341 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
343 * i386-tbl.h: Regenerated.
345 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
347 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
348 PREFIX_MOD_1_0FAE_REG_6.
350 (OP_E_register): Use va_mode.
351 * i386-dis-evex.h (prefix_table):
352 New instructions (see prefixes above).
353 * i386-gen.c (cpu_flag_init): Add WAITPKG.
354 (cpu_flags): Likewise.
355 * i386-opc.h (enum): Likewise.
356 (i386_cpu_flags): Likewise.
357 * i386-opc.tbl: Add umonitor, umwait, tpause.
358 * i386-init.h: Regenerate.
359 * i386-tbl.h: Likewise.
361 2018-04-11 Alan Modra <amodra@gmail.com>
363 * opcodes/i860-dis.c: Delete.
364 * opcodes/i960-dis.c: Delete.
365 * Makefile.am: Remove i860 and i960 support.
366 * configure.ac: Likewise.
367 * disassemble.c: Likewise.
368 * disassemble.h: Likewise.
369 * Makefile.in: Regenerate.
370 * configure: Regenerate.
371 * po/POTFILES.in: Regenerate.
373 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
376 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
378 (print_insn): Clear vex instead of vex.evex.
380 2018-04-04 Nick Clifton <nickc@redhat.com>
382 * po/es.po: Updated Spanish translation.
384 2018-03-28 Jan Beulich <jbeulich@suse.com>
386 * i386-gen.c (opcode_modifiers): Delete VecESize.
387 * i386-opc.h (VecESize): Delete.
388 (struct i386_opcode_modifier): Delete vecesize.
389 * i386-opc.tbl: Drop VecESize.
390 * i386-tlb.h: Re-generate.
392 2018-03-28 Jan Beulich <jbeulich@suse.com>
394 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
395 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
396 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
397 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
398 * i386-tlb.h: Re-generate.
400 2018-03-28 Jan Beulich <jbeulich@suse.com>
402 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
404 * i386-tlb.h: Re-generate.
406 2018-03-28 Jan Beulich <jbeulich@suse.com>
408 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
409 (vex_len_table): Drop Y for vcvt*2si.
410 (putop): Replace plain 'Y' handling by abort().
412 2018-03-28 Nick Clifton <nickc@redhat.com>
415 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
416 instructions with only a base address register.
417 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
418 handle AARHC64_OPND_SVE_ADDR_R.
419 (aarch64_print_operand): Likewise.
420 * aarch64-asm-2.c: Regenerate.
421 * aarch64_dis-2.c: Regenerate.
422 * aarch64-opc-2.c: Regenerate.
424 2018-03-22 Jan Beulich <jbeulich@suse.com>
426 * i386-opc.tbl: Drop VecESize from register only insn forms and
427 memory forms not allowing broadcast.
428 * i386-tlb.h: Re-generate.
430 2018-03-22 Jan Beulich <jbeulich@suse.com>
432 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
433 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
434 sha256*): Drop Disp<N>.
436 2018-03-22 Jan Beulich <jbeulich@suse.com>
438 * i386-dis.c (EbndS, bnd_swap_mode): New.
439 (prefix_table): Use EbndS.
440 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
441 * i386-opc.tbl (bndmov): Move misplaced Load.
442 * i386-tlb.h: Re-generate.
444 2018-03-22 Jan Beulich <jbeulich@suse.com>
446 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
447 templates allowing memory operands and folded ones for register
449 * i386-tlb.h: Re-generate.
451 2018-03-22 Jan Beulich <jbeulich@suse.com>
453 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
454 256-bit templates. Drop redundant leftover Disp<N>.
455 * i386-tlb.h: Re-generate.
457 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
459 * riscv-opc.c (riscv_insn_types): New.
461 2018-03-13 Nick Clifton <nickc@redhat.com>
463 * po/pt_BR.po: Updated Brazilian Portuguese translation.
465 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
467 * i386-opc.tbl: Add Optimize to clr.
468 * i386-tbl.h: Regenerated.
470 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
472 * i386-gen.c (opcode_modifiers): Remove OldGcc.
473 * i386-opc.h (OldGcc): Removed.
474 (i386_opcode_modifier): Remove oldgcc.
475 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
476 instructions for old (<= 2.8.1) versions of gcc.
477 * i386-tbl.h: Regenerated.
479 2018-03-08 Jan Beulich <jbeulich@suse.com>
481 * i386-opc.h (EVEXDYN): New.
482 * i386-opc.tbl: Fold various AVX512VL templates.
483 * i386-tlb.h: Re-generate.
485 2018-03-08 Jan Beulich <jbeulich@suse.com>
487 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
488 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
489 vpexpandd, vpexpandq): Fold AFX512VF templates.
490 * i386-tlb.h: Re-generate.
492 2018-03-08 Jan Beulich <jbeulich@suse.com>
494 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
495 Fold 128- and 256-bit VEX-encoded templates.
496 * i386-tlb.h: Re-generate.
498 2018-03-08 Jan Beulich <jbeulich@suse.com>
500 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
501 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
502 vpexpandd, vpexpandq): Fold AVX512F templates.
503 * i386-tlb.h: Re-generate.
505 2018-03-08 Jan Beulich <jbeulich@suse.com>
507 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
508 64-bit templates. Drop Disp<N>.
509 * i386-tlb.h: Re-generate.
511 2018-03-08 Jan Beulich <jbeulich@suse.com>
513 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
514 and 256-bit templates.
515 * i386-tlb.h: Re-generate.
517 2018-03-08 Jan Beulich <jbeulich@suse.com>
519 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
520 * i386-tlb.h: Re-generate.
522 2018-03-08 Jan Beulich <jbeulich@suse.com>
524 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
526 * i386-tlb.h: Re-generate.
528 2018-03-08 Jan Beulich <jbeulich@suse.com>
530 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
531 * i386-tlb.h: Re-generate.
533 2018-03-08 Jan Beulich <jbeulich@suse.com>
535 * i386-gen.c (opcode_modifiers): Delete FloatD.
536 * i386-opc.h (FloatD): Delete.
537 (struct i386_opcode_modifier): Delete floatd.
538 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
540 * i386-tlb.h: Re-generate.
542 2018-03-08 Jan Beulich <jbeulich@suse.com>
544 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
546 2018-03-08 Jan Beulich <jbeulich@suse.com>
548 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
549 * i386-tlb.h: Re-generate.
551 2018-03-08 Jan Beulich <jbeulich@suse.com>
553 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
555 * i386-tlb.h: Re-generate.
557 2018-03-07 Alan Modra <amodra@gmail.com>
559 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
561 * disassemble.h (print_insn_rs6000): Delete.
562 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
563 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
564 (print_insn_rs6000): Delete.
566 2018-03-03 Alan Modra <amodra@gmail.com>
568 * sysdep.h (opcodes_error_handler): Define.
569 (_bfd_error_handler): Declare.
570 * Makefile.am: Remove stray #.
571 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
573 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
574 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
575 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
576 opcodes_error_handler to print errors. Standardize error messages.
577 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
578 and include opintl.h.
579 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
580 * i386-gen.c: Standardize error messages.
581 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
582 * Makefile.in: Regenerate.
583 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
584 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
585 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
586 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
587 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
588 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
589 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
590 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
591 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
592 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
593 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
594 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
595 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
597 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
599 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
600 vpsub[bwdq] instructions.
601 * i386-tbl.h: Regenerated.
603 2018-03-01 Alan Modra <amodra@gmail.com>
605 * configure.ac (ALL_LINGUAS): Sort.
606 * configure: Regenerate.
608 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
610 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
611 macro by assignements.
613 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
616 * i386-gen.c (opcode_modifiers): Add Optimize.
617 * i386-opc.h (Optimize): New enum.
618 (i386_opcode_modifier): Add optimize.
619 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
620 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
621 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
622 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
623 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
625 * i386-tbl.h: Regenerated.
627 2018-02-26 Alan Modra <amodra@gmail.com>
629 * crx-dis.c (getregliststring): Allocate a large enough buffer
630 to silence false positive gcc8 warning.
632 2018-02-22 Shea Levy <shea@shealevy.com>
634 * disassemble.c (ARCH_riscv): Define if ARCH_all.
636 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
638 * i386-opc.tbl: Add {rex},
639 * i386-tbl.h: Regenerated.
641 2018-02-20 Maciej W. Rozycki <macro@mips.com>
643 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
644 (mips16_opcodes): Replace `M' with `m' for "restore".
646 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
648 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
650 2018-02-13 Maciej W. Rozycki <macro@mips.com>
652 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
653 variable to `function_index'.
655 2018-02-13 Nick Clifton <nickc@redhat.com>
658 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
659 about truncation of printing.
661 2018-02-12 Henry Wong <henry@stuffedcow.net>
663 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
665 2018-02-05 Nick Clifton <nickc@redhat.com>
667 * po/pt_BR.po: Updated Brazilian Portuguese translation.
669 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
671 * i386-dis.c (enum): Add pconfig.
672 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
673 (cpu_flags): Add CpuPCONFIG.
674 * i386-opc.h (enum): Add CpuPCONFIG.
675 (i386_cpu_flags): Add cpupconfig.
676 * i386-opc.tbl: Add PCONFIG instruction.
677 * i386-init.h: Regenerate.
678 * i386-tbl.h: Likewise.
680 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
682 * i386-dis.c (enum): Add PREFIX_0F09.
683 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
684 (cpu_flags): Add CpuWBNOINVD.
685 * i386-opc.h (enum): Add CpuWBNOINVD.
686 (i386_cpu_flags): Add cpuwbnoinvd.
687 * i386-opc.tbl: Add WBNOINVD instruction.
688 * i386-init.h: Regenerate.
689 * i386-tbl.h: Likewise.
691 2018-01-17 Jim Wilson <jimw@sifive.com>
693 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
695 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
697 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
698 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
699 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
700 (cpu_flags): Add CpuIBT, CpuSHSTK.
701 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
702 (i386_cpu_flags): Add cpuibt, cpushstk.
703 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
704 * i386-init.h: Regenerate.
705 * i386-tbl.h: Likewise.
707 2018-01-16 Nick Clifton <nickc@redhat.com>
709 * po/pt_BR.po: Updated Brazilian Portugese translation.
710 * po/de.po: Updated German translation.
712 2018-01-15 Jim Wilson <jimw@sifive.com>
714 * riscv-opc.c (match_c_nop): New.
715 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
717 2018-01-15 Nick Clifton <nickc@redhat.com>
719 * po/uk.po: Updated Ukranian translation.
721 2018-01-13 Nick Clifton <nickc@redhat.com>
723 * po/opcodes.pot: Regenerated.
725 2018-01-13 Nick Clifton <nickc@redhat.com>
727 * configure: Regenerate.
729 2018-01-13 Nick Clifton <nickc@redhat.com>
733 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
735 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
736 * i386-tbl.h: Regenerate.
738 2018-01-10 Jan Beulich <jbeulich@suse.com>
740 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
741 * i386-tbl.h: Re-generate.
743 2018-01-10 Jan Beulich <jbeulich@suse.com>
745 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
746 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
747 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
748 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
749 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
750 Disp8MemShift of AVX512VL forms.
751 * i386-tbl.h: Re-generate.
753 2018-01-09 Jim Wilson <jimw@sifive.com>
755 * riscv-dis.c (maybe_print_address): If base_reg is zero,
756 then the hi_addr value is zero.
758 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
760 * arm-dis.c (arm_opcodes): Add csdb.
761 (thumb32_opcodes): Add csdb.
763 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
765 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
766 * aarch64-asm-2.c: Regenerate.
767 * aarch64-dis-2.c: Regenerate.
768 * aarch64-opc-2.c: Regenerate.
770 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
773 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
774 Remove AVX512 vmovd with 64-bit operands.
775 * i386-tbl.h: Regenerated.
777 2018-01-05 Jim Wilson <jimw@sifive.com>
779 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
782 2018-01-03 Alan Modra <amodra@gmail.com>
784 Update year range in copyright notice of all files.
786 2018-01-02 Jan Beulich <jbeulich@suse.com>
788 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
789 and OPERAND_TYPE_REGZMM entries.
791 For older changes see ChangeLog-2017
793 Copyright (C) 2018 Free Software Foundation, Inc.
795 Copying and distribution of this file, with or without modification,
796 are permitted in any medium without royalty provided the copyright
797 notice and this notice are preserved.
803 version-control: never