1 2018-12-06 Andrew Burgess <andrew.burgess@embecosm.com>
3 * configure.ac (enable-cgen-maint): Support passing path to cgen
5 * configure: Regenerate.
7 2018-12-06 Andrew Burgess <andrew.burgess@embecosm.com>
9 * disassembler.c (disassemble_init_for_target): Add RISC-V
11 * riscv-dis.c (riscv_symbol_is_valid): New function.
13 2018-12-03 Kito Cheng <kito@andestech.com>
15 * riscv-opc.c: Change the type of xlen, because type of
16 xlen_requirement changed.
18 2018-12-03 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
22 * aarch64-tbl.h (aarch64_opcode_table): Only disassemble an ORR
23 encoding as MOV if the shift operation is a left shift of zero.
25 2018-11-29 Jim Wilson <jimw@sifive.com>
27 * riscv-opc.c (unimp): Mark compressed unimp as INSN_ALIAS.
30 2018-11-27 Jim Wilson <jimw@sifive.com>
32 * riscv-opc.c (ciw): Fix whitespace to align columns.
35 2018-11-21 John Darrington <john@darrington.wattle.id.au>
37 * s12z-dis.c (print_insn_shift) [SB_REG_REG_N]: Enter special case
38 if the postbyte matches the appropriate pattern.
40 2018-11-13 Francois H. Theron <francois.theron@netronome.com>
42 * nfp-dis.c: Fix crc[] disassembly if operands are swapped.
44 2018-11-12 Sudakshina Das <sudi.das@arm.com>
46 * aarch64-opc.c (aarch64_sys_regs_dc): New entries for
47 IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
48 IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
50 (aarch64_sys_ins_reg_supported_p): New check for above.
52 2018-11-12 Sudakshina Das <sudi.das@arm.com>
54 * aarch64-opc.c (aarch64_sys_regs): New entries for TCO,
55 TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12,
57 (aarch64_sys_reg_supported_p): New check for above.
58 (aarch64_pstatefields): New entry for TCO.
59 (aarch64_pstatefield_supported_p): New check for above.
61 2018-11-12 Sudakshina Das <sudi.das@arm.com>
63 * aarch64-asm.c (aarch64_ins_addr_simple_2): New.
64 * aarch64-asm.h (ins_addr_simple_2): Declare the above.
65 * aarch64-dis.c (aarch64_ext_addr_simple_2): New.
66 * aarch64-dis.h (ext_addr_simple_2): Declare the above.
67 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
68 AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
69 (aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2.
70 * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
71 (AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
72 * aarch64-asm-2.c: Regenerated.
73 * aarch64-dis-2.c: Regenerated.
74 * aarch64-opc-2.c: Regenerated.
76 2018-11-12 Sudakshina Das <sudi.das@arm.com>
78 * aarch64-tbl.h (QL_LDG): New.
79 (aarch64_opcode_table): Add ldg.
80 * aarch64-asm-2.c: Regenerated.
81 * aarch64-dis-2.c: Regenerated.
82 * aarch64-opc-2.c: Regenerated.
84 2018-11-12 Sudakshina Das <sudi.das@arm.com>
86 * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
87 for AARCH64_OPND_QLF_imm_tag.
88 (operand_general_constraint_met_p): Add case for
89 AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
90 (aarch64_print_operand): Likewise.
91 * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
92 (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
93 for both offset and pre/post indexed versions.
94 (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
95 * aarch64-asm-2.c: Regenerated.
96 * aarch64-dis-2.c: Regenerated.
97 * aarch64-opc-2.c: Regenerated.
99 2018-11-12 Sudakshina Das <sudi.das@arm.com>
101 * aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp.
102 * aarch64-asm-2.c: Regenerated.
103 * aarch64-dis-2.c: Regenerated.
104 * aarch64-opc-2.c: Regenerated.
106 2018-11-12 Sudakshina Das <sudi.das@arm.com>
108 * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
109 (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
110 * aarch64-opc.c (fields): Add entry for imm4_3.
111 (operand_general_constraint_met_p): Add cases for
112 AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
113 (aarch64_print_operand): Likewise.
114 * aarch64-tbl.h (QL_ADDG): New.
115 (aarch64_opcode_table): Add addg, subg, irg and gmi.
116 (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
117 * aarch64-asm.c (aarch64_ins_imm): Add case for
118 operand_need_shift_by_four.
119 * aarch64-asm-2.c: Regenerated.
120 * aarch64-dis-2.c: Regenerated.
121 * aarch64-opc-2.c: Regenerated.
123 2018-11-12 Sudakshina Das <sudi.das@arm.com>
125 * aarch64-tbl.h (aarch64_feature_memtag): New.
126 (MEMTAG, MEMTAG_INSN): New.
128 2018-11-06 Sudakshina Das <sudi.das@arm.com>
130 * arm-dis.c (select_arm_features): Update bfd_mach_arm_8
131 with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML.
133 2018-11-06 Alan Modra <amodra@gmail.com>
135 * ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls),
136 (insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0),
137 (insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16),
138 (insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd):
139 Don't return zero on error, insert mask bits instead.
140 (insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete.
141 (insert_sh6, extract_sh6): Delete dead code.
142 (insert_sprbat, insert_sprg): Use unsigned comparisions.
143 (powerpc_operands <OIMM>): Set shift count rather than using
145 <SE_SDH, SE_SDW>: Likewise. Don't use insert/extract functions.
147 2018-11-06 Jan Beulich <jbeulich@suse.com>
149 * i386-dis-evex.h (evex_table): Use K suffix instead of %LW for
150 vpbroadcast{d,q} with GPR operand.
152 2018-11-06 Jan Beulich <jbeulich@suse.com>
154 * i386-dis.c (EVEX_W_0F6E_P_2, EVEX_W_0F7E_P_2): Delete.
155 * i386-dis-evex.h (evex_table): Move vmov[dq} with GPR operand
156 cases up one level in the hierarchy.
158 2018-11-06 Jan Beulich <jbeulich@suse.com>
160 * i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0,
161 MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0.
162 (MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold
163 into MOD_VEX_0F93_P_3_LEN_0.
164 (vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR
165 operand cases up one level in the hierarchy.
167 2018-11-06 Jan Beulich <jbeulich@suse.com>
169 * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
170 VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
171 EVEX_W_0F3A22_P_2): Delete.
172 (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
173 entries up one level in the hierarchy.
174 (OP_E_memory): Handle dq_mode when determining Disp8 shift
176 * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
177 entries up one level in the hierarchy.
178 * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
179 VexWIG for AVX flavors.
180 * i386-tbl.h: Re-generate.
182 2018-11-06 Jan Beulich <jbeulich@suse.com>
184 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
185 vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
186 vcvtusi2ss, kmovd): Drop VexW=1.
187 * i386-tbl.h: Re-generate.
189 2018-11-06 Jan Beulich <jbeulich@suse.com>
191 * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
192 EVex512, EVexLIG, EVexDYN): New.
193 (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
194 insns): Use Vex128 instead of Vex=3 (aka VexLIG).
195 (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
196 of EVex=4 (aka EVexLIG).
197 * i386-tbl.h: Re-generate.
199 2018-11-06 Jan Beulich <jbeulich@suse.com>
201 * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
202 (vpmaxub): Re-order attributes on AVX512BW flavor.
203 * i386-tbl.h: Re-generate.
205 2018-11-06 Jan Beulich <jbeulich@suse.com>
207 * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
208 vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
209 Vex=1 on AVX / AVX2 flavors.
210 (vpmaxub): Re-order attributes on AVX512BW flavor.
211 * i386-tbl.h: Re-generate.
213 2018-11-06 Jan Beulich <jbeulich@suse.com>
215 * i386-opc.tbl (VexW0, VexW1): New.
216 (vphadd*, vphsub*): Use VexW0 on XOP variants.
217 * i386-tbl.h: Re-generate.
219 2018-10-22 John Darrington <john@darrington.wattle.id.au>
221 * s12z-dis.c (decode_possible_symbol): Add fallback case.
222 (rel_15_7): Likewise.
224 2018-10-19 Tamar Christina <tamar.christina@arm.com>
226 * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
227 (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
228 (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
230 2018-10-16 Matthew Malcomson <matthew.malcomson@arm.com>
232 * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
233 corresponding to AARCH64_OPND_QLF_S_4B qualifier.
235 2018-10-10 Jan Beulich <jbeulich@suse.com>
237 * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
239 * i386-opc.h (Size16, Size32, Size64): Delete.
241 (SIZE16, SIZE32, SIZE64): Define.
242 (struct i386_opcode_modifier): Drop size16, size32, and size64.
244 * i386-opc.tbl (Size16, Size32, Size64): Define.
245 * i386-tbl.h: Re-generate.
247 2018-10-09 Sudakshina Das <sudi.das@arm.com>
249 * aarch64-opc.c (operand_general_constraint_met_p): Add
250 SSBS in the check for one-bit immediate.
251 (aarch64_sys_regs): New entry for SSBS.
252 (aarch64_sys_reg_supported_p): New check for above.
253 (aarch64_pstatefields): New entry for SSBS.
254 (aarch64_pstatefield_supported_p): New check for above.
256 2018-10-09 Sudakshina Das <sudi.das@arm.com>
258 * aarch64-opc.c (aarch64_sys_regs): New entries for
259 scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
260 (aarch64_sys_reg_supported_p): New checks for above.
262 2018-10-09 Sudakshina Das <sudi.das@arm.com>
264 * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
265 (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
266 with the hint immediate.
267 * aarch64-opc.c (aarch64_hint_options): New entries for
268 c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
269 (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
270 while checking for HINT_OPD_F_NOPRINT flag.
271 * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
273 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
274 (aarch64_opcode_table): Add entry for BTI.
275 (AARCH64_OPERANDS): Add new description for BTI targets.
276 * aarch64-asm-2.c: Regenerate.
277 * aarch64-dis-2.c: Regenerate.
278 * aarch64-opc-2.c: Regenerate.
280 2018-10-09 Sudakshina Das <sudi.das@arm.com>
282 * aarch64-opc.c (aarch64_sys_regs): New entries for
284 (aarch64_sys_reg_supported_p): New check for above.
286 2018-10-09 Sudakshina Das <sudi.das@arm.com>
288 * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
289 (aarch64_sys_ins_reg_supported_p): New check for above.
291 2018-10-09 Sudakshina Das <sudi.das@arm.com>
293 * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
294 AARCH64_OPND_SYSREG_SR.
295 * aarch64-opc.c (aarch64_print_operand): Likewise.
296 (aarch64_sys_regs_sr): Define table.
297 (aarch64_sys_ins_reg_supported_p): Check for RCTX with
298 AARCH64_FEATURE_PREDRES.
299 * aarch64-tbl.h (aarch64_feature_predres): New.
300 (PREDRES, PREDRES_INSN): New.
301 (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
302 (AARCH64_OPERANDS): Add new description for SYSREG_SR.
303 * aarch64-asm-2.c: Regenerate.
304 * aarch64-dis-2.c: Regenerate.
305 * aarch64-opc-2.c: Regenerate.
307 2018-10-09 Sudakshina Das <sudi.das@arm.com>
309 * aarch64-tbl.h (aarch64_feature_sb): New.
311 (aarch64_opcode_table): Add entry for sb.
312 * aarch64-asm-2.c: Regenerate.
313 * aarch64-dis-2.c: Regenerate.
314 * aarch64-opc-2.c: Regenerate.
316 2018-10-09 Sudakshina Das <sudi.das@arm.com>
318 * aarch64-tbl.h (aarch64_feature_flagmanip): New.
319 (aarch64_feature_frintts): New.
320 (FLAGMANIP, FRINTTS): New.
321 (aarch64_opcode_table): Add entries for xaflag, axflag
322 and frint[32,64][x,z] instructions.
323 * aarch64-asm-2.c: Regenerate.
324 * aarch64-dis-2.c: Regenerate.
325 * aarch64-opc-2.c: Regenerate.
327 2018-10-09 Sudakshina Das <sudi.das@arm.com>
329 * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
330 (ARMV8_5, V8_5_INSN): New.
332 2018-10-08 Tamar Christina <tamar.christina@arm.com>
334 * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
336 2018-10-05 H.J. Lu <hongjiu.lu@intel.com>
338 * i386-dis.c (rm_table): Add enclv.
339 * i386-opc.tbl: Add enclv.
340 * i386-tbl.h: Regenerated.
342 2018-10-05 Sudakshina Das <sudi.das@arm.com>
344 * arm-dis.c (arm_opcodes): Add sb.
345 (thumb32_opcodes): Likewise.
347 2018-10-05 Richard Henderson <rth@twiddle.net>
348 Stafford Horne <shorne@gmail.com>
350 * or1k-desc.c: Regenerate.
351 * or1k-desc.h: Regenerate.
352 * or1k-opc.c: Regenerate.
353 * or1k-opc.h: Regenerate.
354 * or1k-opinst.c: Regenerate.
356 2018-10-05 Richard Henderson <rth@twiddle.net>
358 * or1k-asm.c: Regenerated.
359 * or1k-desc.c: Regenerated.
360 * or1k-desc.h: Regenerated.
361 * or1k-dis.c: Regenerated.
362 * or1k-ibld.c: Regenerated.
363 * or1k-opc.c: Regenerated.
364 * or1k-opc.h: Regenerated.
365 * or1k-opinst.c: Regenerated.
367 2018-10-05 Richard Henderson <rth@twiddle.net>
369 * or1k-asm.c: Regenerate.
371 2018-10-03 Tamar Christina <tamar.christina@arm.com>
373 * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
374 * aarch64-dis.c (print_operands): Refactor to take notes.
375 (print_verifier_notes): New.
376 (print_aarch64_insn): Apply constraint verifier.
377 (print_insn_aarch64_word): Update call to print_aarch64_insn.
378 * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
380 2018-10-03 Tamar Christina <tamar.christina@arm.com>
382 * aarch64-opc.c (init_insn_block): New.
383 (verify_constraints, aarch64_is_destructive_by_operands): New.
384 * aarch64-opc.h (verify_constraints): New.
386 2018-10-03 Tamar Christina <tamar.christina@arm.com>
388 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
389 * aarch64-opc.c (verify_ldpsw): Update arguments.
391 2018-10-03 Tamar Christina <tamar.christina@arm.com>
393 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
394 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
396 2018-10-03 Tamar Christina <tamar.christina@arm.com>
398 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
399 * aarch64-dis.c (insn_sequence): New.
401 2018-10-03 Tamar Christina <tamar.christina@arm.com>
403 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
404 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
405 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
406 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
409 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
411 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
413 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
414 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
415 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
416 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
417 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
418 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
419 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
421 2018-10-02 Palmer Dabbelt <palmer@sifive.com>
423 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
425 2018-09-23 Sandra Loosemore <sandra@codesourcery.com>
427 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
428 are used when extracting signed fields and converting them to
429 potentially 64-bit types.
431 2018-09-21 Simon Marchi <simon.marchi@ericsson.com>
433 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
434 * Makefile.in: Re-generate.
435 * aclocal.m4: Re-generate.
436 * configure: Re-generate.
437 * configure.ac: Remove check for -Wno-missing-field-initializers.
438 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
439 (csky_v2_opcodes): Likewise.
441 2018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
443 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
445 2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
447 * nds32-asm.c (operand_fields): Remove the unused fields.
448 (nds32_opcodes): Remove the unused instructions.
449 * nds32-dis.c (nds32_ex9_info): Removed.
450 (nds32_parse_opcode): Updated.
451 (print_insn_nds32): Likewise.
452 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
453 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
454 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
455 build_opcode_hash_table): New functions.
456 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
457 nds32_opcode_table): New.
458 (hw_ktabs): Declare it to a pointer rather than an array.
459 (build_hash_table): Removed.
460 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
461 SYN_ROPT and upadte HW_GPR and HW_INT.
462 * nds32-dis.c (keywords): Remove const.
463 (match_field): New function.
464 (nds32_parse_opcode): Updated.
465 * disassemble.c (disassemble_init_for_target):
466 Add disassemble_init_nds32.
467 * nds32-dis.c (eum map_type): New.
468 (nds32_private_data): Likewise.
469 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
470 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
471 (print_insn_nds32): Updated.
472 * nds32-asm.c (parse_aext_reg): Add new parameter.
473 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
476 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
477 (operand_fields): Add new fields.
478 (nds32_opcodes): Add new instructions.
479 (keyword_aridxi_mx): New keyword.
480 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
482 (ALU2_1, ALU2_2, ALU2_3): New macros.
483 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
485 2018-09-17 Kito Cheng <kito@andestech.com>
487 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
489 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
492 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
493 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
494 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
495 (EVEX_LEN_0F7E_P_1): Likewise.
496 (EVEX_LEN_0F7E_P_2): Likewise.
497 (EVEX_LEN_0FD6_P_2): Likewise.
498 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
499 (EVEX_LEN_TABLE): Likewise.
500 (EVEX_LEN_0F6E_P_2): New enum.
501 (EVEX_LEN_0F7E_P_1): Likewise.
502 (EVEX_LEN_0F7E_P_2): Likewise.
503 (EVEX_LEN_0FD6_P_2): Likewise.
504 (evex_len_table): New.
505 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
506 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
507 * i386-tbl.h: Regenerated.
509 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
512 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
513 VEX_LEN_0F7E_P_2 entries.
514 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
515 * i386-tbl.h: Regenerated.
517 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
519 * i386-dis.c (VZERO_Fixup): Removed.
521 (VEX_LEN_0F10_P_1): Likewise.
522 (VEX_LEN_0F10_P_3): Likewise.
523 (VEX_LEN_0F11_P_1): Likewise.
524 (VEX_LEN_0F11_P_3): Likewise.
525 (VEX_LEN_0F2E_P_0): Likewise.
526 (VEX_LEN_0F2E_P_2): Likewise.
527 (VEX_LEN_0F2F_P_0): Likewise.
528 (VEX_LEN_0F2F_P_2): Likewise.
529 (VEX_LEN_0F51_P_1): Likewise.
530 (VEX_LEN_0F51_P_3): Likewise.
531 (VEX_LEN_0F52_P_1): Likewise.
532 (VEX_LEN_0F53_P_1): Likewise.
533 (VEX_LEN_0F58_P_1): Likewise.
534 (VEX_LEN_0F58_P_3): Likewise.
535 (VEX_LEN_0F59_P_1): Likewise.
536 (VEX_LEN_0F59_P_3): Likewise.
537 (VEX_LEN_0F5A_P_1): Likewise.
538 (VEX_LEN_0F5A_P_3): Likewise.
539 (VEX_LEN_0F5C_P_1): Likewise.
540 (VEX_LEN_0F5C_P_3): Likewise.
541 (VEX_LEN_0F5D_P_1): Likewise.
542 (VEX_LEN_0F5D_P_3): Likewise.
543 (VEX_LEN_0F5E_P_1): Likewise.
544 (VEX_LEN_0F5E_P_3): Likewise.
545 (VEX_LEN_0F5F_P_1): Likewise.
546 (VEX_LEN_0F5F_P_3): Likewise.
547 (VEX_LEN_0FC2_P_1): Likewise.
548 (VEX_LEN_0FC2_P_3): Likewise.
549 (VEX_LEN_0F3A0A_P_2): Likewise.
550 (VEX_LEN_0F3A0B_P_2): Likewise.
551 (VEX_W_0F10_P_0): Likewise.
552 (VEX_W_0F10_P_1): Likewise.
553 (VEX_W_0F10_P_2): Likewise.
554 (VEX_W_0F10_P_3): Likewise.
555 (VEX_W_0F11_P_0): Likewise.
556 (VEX_W_0F11_P_1): Likewise.
557 (VEX_W_0F11_P_2): Likewise.
558 (VEX_W_0F11_P_3): Likewise.
559 (VEX_W_0F12_P_0_M_0): Likewise.
560 (VEX_W_0F12_P_0_M_1): Likewise.
561 (VEX_W_0F12_P_1): Likewise.
562 (VEX_W_0F12_P_2): Likewise.
563 (VEX_W_0F12_P_3): Likewise.
564 (VEX_W_0F13_M_0): Likewise.
565 (VEX_W_0F14): Likewise.
566 (VEX_W_0F15): Likewise.
567 (VEX_W_0F16_P_0_M_0): Likewise.
568 (VEX_W_0F16_P_0_M_1): Likewise.
569 (VEX_W_0F16_P_1): Likewise.
570 (VEX_W_0F16_P_2): Likewise.
571 (VEX_W_0F17_M_0): Likewise.
572 (VEX_W_0F28): Likewise.
573 (VEX_W_0F29): Likewise.
574 (VEX_W_0F2B_M_0): Likewise.
575 (VEX_W_0F2E_P_0): Likewise.
576 (VEX_W_0F2E_P_2): Likewise.
577 (VEX_W_0F2F_P_0): Likewise.
578 (VEX_W_0F2F_P_2): Likewise.
579 (VEX_W_0F50_M_0): Likewise.
580 (VEX_W_0F51_P_0): Likewise.
581 (VEX_W_0F51_P_1): Likewise.
582 (VEX_W_0F51_P_2): Likewise.
583 (VEX_W_0F51_P_3): Likewise.
584 (VEX_W_0F52_P_0): Likewise.
585 (VEX_W_0F52_P_1): Likewise.
586 (VEX_W_0F53_P_0): Likewise.
587 (VEX_W_0F53_P_1): Likewise.
588 (VEX_W_0F58_P_0): Likewise.
589 (VEX_W_0F58_P_1): Likewise.
590 (VEX_W_0F58_P_2): Likewise.
591 (VEX_W_0F58_P_3): Likewise.
592 (VEX_W_0F59_P_0): Likewise.
593 (VEX_W_0F59_P_1): Likewise.
594 (VEX_W_0F59_P_2): Likewise.
595 (VEX_W_0F59_P_3): Likewise.
596 (VEX_W_0F5A_P_0): Likewise.
597 (VEX_W_0F5A_P_1): Likewise.
598 (VEX_W_0F5A_P_3): Likewise.
599 (VEX_W_0F5B_P_0): Likewise.
600 (VEX_W_0F5B_P_1): Likewise.
601 (VEX_W_0F5B_P_2): Likewise.
602 (VEX_W_0F5C_P_0): Likewise.
603 (VEX_W_0F5C_P_1): Likewise.
604 (VEX_W_0F5C_P_2): Likewise.
605 (VEX_W_0F5C_P_3): Likewise.
606 (VEX_W_0F5D_P_0): Likewise.
607 (VEX_W_0F5D_P_1): Likewise.
608 (VEX_W_0F5D_P_2): Likewise.
609 (VEX_W_0F5D_P_3): Likewise.
610 (VEX_W_0F5E_P_0): Likewise.
611 (VEX_W_0F5E_P_1): Likewise.
612 (VEX_W_0F5E_P_2): Likewise.
613 (VEX_W_0F5E_P_3): Likewise.
614 (VEX_W_0F5F_P_0): Likewise.
615 (VEX_W_0F5F_P_1): Likewise.
616 (VEX_W_0F5F_P_2): Likewise.
617 (VEX_W_0F5F_P_3): Likewise.
618 (VEX_W_0F60_P_2): Likewise.
619 (VEX_W_0F61_P_2): Likewise.
620 (VEX_W_0F62_P_2): Likewise.
621 (VEX_W_0F63_P_2): Likewise.
622 (VEX_W_0F64_P_2): Likewise.
623 (VEX_W_0F65_P_2): Likewise.
624 (VEX_W_0F66_P_2): Likewise.
625 (VEX_W_0F67_P_2): Likewise.
626 (VEX_W_0F68_P_2): Likewise.
627 (VEX_W_0F69_P_2): Likewise.
628 (VEX_W_0F6A_P_2): Likewise.
629 (VEX_W_0F6B_P_2): Likewise.
630 (VEX_W_0F6C_P_2): Likewise.
631 (VEX_W_0F6D_P_2): Likewise.
632 (VEX_W_0F6F_P_1): Likewise.
633 (VEX_W_0F6F_P_2): Likewise.
634 (VEX_W_0F70_P_1): Likewise.
635 (VEX_W_0F70_P_2): Likewise.
636 (VEX_W_0F70_P_3): Likewise.
637 (VEX_W_0F71_R_2_P_2): Likewise.
638 (VEX_W_0F71_R_4_P_2): Likewise.
639 (VEX_W_0F71_R_6_P_2): Likewise.
640 (VEX_W_0F72_R_2_P_2): Likewise.
641 (VEX_W_0F72_R_4_P_2): Likewise.
642 (VEX_W_0F72_R_6_P_2): Likewise.
643 (VEX_W_0F73_R_2_P_2): Likewise.
644 (VEX_W_0F73_R_3_P_2): Likewise.
645 (VEX_W_0F73_R_6_P_2): Likewise.
646 (VEX_W_0F73_R_7_P_2): Likewise.
647 (VEX_W_0F74_P_2): Likewise.
648 (VEX_W_0F75_P_2): Likewise.
649 (VEX_W_0F76_P_2): Likewise.
650 (VEX_W_0F77_P_0): Likewise.
651 (VEX_W_0F7C_P_2): Likewise.
652 (VEX_W_0F7C_P_3): Likewise.
653 (VEX_W_0F7D_P_2): Likewise.
654 (VEX_W_0F7D_P_3): Likewise.
655 (VEX_W_0F7E_P_1): Likewise.
656 (VEX_W_0F7F_P_1): Likewise.
657 (VEX_W_0F7F_P_2): Likewise.
658 (VEX_W_0FAE_R_2_M_0): Likewise.
659 (VEX_W_0FAE_R_3_M_0): Likewise.
660 (VEX_W_0FC2_P_0): Likewise.
661 (VEX_W_0FC2_P_1): Likewise.
662 (VEX_W_0FC2_P_2): Likewise.
663 (VEX_W_0FC2_P_3): Likewise.
664 (VEX_W_0FD0_P_2): Likewise.
665 (VEX_W_0FD0_P_3): Likewise.
666 (VEX_W_0FD1_P_2): Likewise.
667 (VEX_W_0FD2_P_2): Likewise.
668 (VEX_W_0FD3_P_2): Likewise.
669 (VEX_W_0FD4_P_2): Likewise.
670 (VEX_W_0FD5_P_2): Likewise.
671 (VEX_W_0FD6_P_2): Likewise.
672 (VEX_W_0FD7_P_2_M_1): Likewise.
673 (VEX_W_0FD8_P_2): Likewise.
674 (VEX_W_0FD9_P_2): Likewise.
675 (VEX_W_0FDA_P_2): Likewise.
676 (VEX_W_0FDB_P_2): Likewise.
677 (VEX_W_0FDC_P_2): Likewise.
678 (VEX_W_0FDD_P_2): Likewise.
679 (VEX_W_0FDE_P_2): Likewise.
680 (VEX_W_0FDF_P_2): Likewise.
681 (VEX_W_0FE0_P_2): Likewise.
682 (VEX_W_0FE1_P_2): Likewise.
683 (VEX_W_0FE2_P_2): Likewise.
684 (VEX_W_0FE3_P_2): Likewise.
685 (VEX_W_0FE4_P_2): Likewise.
686 (VEX_W_0FE5_P_2): Likewise.
687 (VEX_W_0FE6_P_1): Likewise.
688 (VEX_W_0FE6_P_2): Likewise.
689 (VEX_W_0FE6_P_3): Likewise.
690 (VEX_W_0FE7_P_2_M_0): Likewise.
691 (VEX_W_0FE8_P_2): Likewise.
692 (VEX_W_0FE9_P_2): Likewise.
693 (VEX_W_0FEA_P_2): Likewise.
694 (VEX_W_0FEB_P_2): Likewise.
695 (VEX_W_0FEC_P_2): Likewise.
696 (VEX_W_0FED_P_2): Likewise.
697 (VEX_W_0FEE_P_2): Likewise.
698 (VEX_W_0FEF_P_2): Likewise.
699 (VEX_W_0FF0_P_3_M_0): Likewise.
700 (VEX_W_0FF1_P_2): Likewise.
701 (VEX_W_0FF2_P_2): Likewise.
702 (VEX_W_0FF3_P_2): Likewise.
703 (VEX_W_0FF4_P_2): Likewise.
704 (VEX_W_0FF5_P_2): Likewise.
705 (VEX_W_0FF6_P_2): Likewise.
706 (VEX_W_0FF7_P_2): Likewise.
707 (VEX_W_0FF8_P_2): Likewise.
708 (VEX_W_0FF9_P_2): Likewise.
709 (VEX_W_0FFA_P_2): Likewise.
710 (VEX_W_0FFB_P_2): Likewise.
711 (VEX_W_0FFC_P_2): Likewise.
712 (VEX_W_0FFD_P_2): Likewise.
713 (VEX_W_0FFE_P_2): Likewise.
714 (VEX_W_0F3800_P_2): Likewise.
715 (VEX_W_0F3801_P_2): Likewise.
716 (VEX_W_0F3802_P_2): Likewise.
717 (VEX_W_0F3803_P_2): Likewise.
718 (VEX_W_0F3804_P_2): Likewise.
719 (VEX_W_0F3805_P_2): Likewise.
720 (VEX_W_0F3806_P_2): Likewise.
721 (VEX_W_0F3807_P_2): Likewise.
722 (VEX_W_0F3808_P_2): Likewise.
723 (VEX_W_0F3809_P_2): Likewise.
724 (VEX_W_0F380A_P_2): Likewise.
725 (VEX_W_0F380B_P_2): Likewise.
726 (VEX_W_0F3817_P_2): Likewise.
727 (VEX_W_0F381C_P_2): Likewise.
728 (VEX_W_0F381D_P_2): Likewise.
729 (VEX_W_0F381E_P_2): Likewise.
730 (VEX_W_0F3820_P_2): Likewise.
731 (VEX_W_0F3821_P_2): Likewise.
732 (VEX_W_0F3822_P_2): Likewise.
733 (VEX_W_0F3823_P_2): Likewise.
734 (VEX_W_0F3824_P_2): Likewise.
735 (VEX_W_0F3825_P_2): Likewise.
736 (VEX_W_0F3828_P_2): Likewise.
737 (VEX_W_0F3829_P_2): Likewise.
738 (VEX_W_0F382A_P_2_M_0): Likewise.
739 (VEX_W_0F382B_P_2): Likewise.
740 (VEX_W_0F3830_P_2): Likewise.
741 (VEX_W_0F3831_P_2): Likewise.
742 (VEX_W_0F3832_P_2): Likewise.
743 (VEX_W_0F3833_P_2): Likewise.
744 (VEX_W_0F3834_P_2): Likewise.
745 (VEX_W_0F3835_P_2): Likewise.
746 (VEX_W_0F3837_P_2): Likewise.
747 (VEX_W_0F3838_P_2): Likewise.
748 (VEX_W_0F3839_P_2): Likewise.
749 (VEX_W_0F383A_P_2): Likewise.
750 (VEX_W_0F383B_P_2): Likewise.
751 (VEX_W_0F383C_P_2): Likewise.
752 (VEX_W_0F383D_P_2): Likewise.
753 (VEX_W_0F383E_P_2): Likewise.
754 (VEX_W_0F383F_P_2): Likewise.
755 (VEX_W_0F3840_P_2): Likewise.
756 (VEX_W_0F3841_P_2): Likewise.
757 (VEX_W_0F38DB_P_2): Likewise.
758 (VEX_W_0F3A08_P_2): Likewise.
759 (VEX_W_0F3A09_P_2): Likewise.
760 (VEX_W_0F3A0A_P_2): Likewise.
761 (VEX_W_0F3A0B_P_2): Likewise.
762 (VEX_W_0F3A0C_P_2): Likewise.
763 (VEX_W_0F3A0D_P_2): Likewise.
764 (VEX_W_0F3A0E_P_2): Likewise.
765 (VEX_W_0F3A0F_P_2): Likewise.
766 (VEX_W_0F3A21_P_2): Likewise.
767 (VEX_W_0F3A40_P_2): Likewise.
768 (VEX_W_0F3A41_P_2): Likewise.
769 (VEX_W_0F3A42_P_2): Likewise.
770 (VEX_W_0F3A62_P_2): Likewise.
771 (VEX_W_0F3A63_P_2): Likewise.
772 (VEX_W_0F3ADF_P_2): Likewise.
773 (VEX_LEN_0F77_P_0): New.
774 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
775 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
776 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
777 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
778 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
779 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
780 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
781 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
782 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
783 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
784 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
785 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
786 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
787 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
788 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
789 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
790 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
791 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
792 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
793 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
794 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
795 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
796 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
797 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
798 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
799 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
800 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
801 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
802 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
803 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
804 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
805 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
806 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
807 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
808 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
809 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
810 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
811 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
812 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
813 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
814 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
815 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
816 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
817 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
818 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
819 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
820 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
821 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
822 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
823 (vex_table): Update VEX 0F28 and 0F29 entries.
824 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
825 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
826 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
827 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
828 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
829 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
830 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
831 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
832 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
833 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
834 VEX_LEN_0F3A0B_P_2 entries.
835 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
836 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
837 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
838 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
839 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
840 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
841 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
842 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
843 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
844 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
845 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
846 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
847 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
848 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
849 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
850 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
851 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
852 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
853 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
854 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
855 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
856 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
857 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
858 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
859 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
860 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
861 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
862 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
863 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
864 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
865 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
866 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
867 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
868 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
869 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
870 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
871 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
872 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
873 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
874 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
875 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
876 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
877 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
878 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
879 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
880 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
881 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
882 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
883 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
884 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
885 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
886 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
887 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
888 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
889 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
890 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
891 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
892 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
893 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
894 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
895 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
896 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
897 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
898 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
899 VEX_W_0F3ADF_P_2 entries.
900 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
901 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
902 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
904 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
906 * i386-opc.tbl (VexWIG): New.
907 Replace VexW=3 with VexWIG.
909 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
911 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
912 * i386-tbl.h: Regenerated.
914 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
917 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
918 VEX_LEN_0FD6_P_2 entries.
919 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
920 * i386-tbl.h: Regenerated.
922 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
925 * i386-opc.h (VEXWIG): New.
926 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
927 * i386-tbl.h: Regenerated.
929 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
932 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
933 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
934 * i386-dis.c (EXxEVexR64): New.
935 (evex_rounding_64_mode): Likewise.
936 (OP_Rounding): Handle evex_rounding_64_mode.
938 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
941 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
942 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
943 * i386-dis.c (Edqa): New.
944 (dqa_mode): Likewise.
945 (intel_operand_size): Handle dqa_mode as m_mode.
946 (OP_E_register): Handle dqa_mode as dq_mode.
947 (OP_E_memory): Set shift for dqa_mode based on address_mode.
949 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
951 * i386-dis.c (OP_E_memory): Reformat.
953 2018-09-14 Jan Beulich <jbeulich@suse.com>
955 * i386-opc.tbl (crc32): Fold byte and word forms.
956 * i386-tbl.h: Re-generate.
958 2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
960 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
961 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
962 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
963 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
964 * i386-tbl.h: Regenerated.
966 2018-09-13 Jan Beulich <jbeulich@suse.com>
968 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
970 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
971 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
972 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
973 * i386-tbl.h: Re-generate.
975 2018-09-13 Jan Beulich <jbeulich@suse.com>
977 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
979 * i386-tbl.h: Re-generate.
981 2018-09-13 Jan Beulich <jbeulich@suse.com>
983 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
985 * i386-tbl.h: Re-generate.
987 2018-09-13 Jan Beulich <jbeulich@suse.com>
989 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
991 * i386-tbl.h: Re-generate.
993 2018-09-13 Jan Beulich <jbeulich@suse.com>
995 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
997 * i386-tbl.h: Re-generate.
999 2018-09-13 Jan Beulich <jbeulich@suse.com>
1001 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
1003 * i386-tbl.h: Re-generate.
1005 2018-09-13 Jan Beulich <jbeulich@suse.com>
1007 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
1009 * i386-tbl.h: Re-generate.
1011 2018-09-13 Jan Beulich <jbeulich@suse.com>
1013 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
1014 * i386-tbl.h: Re-generate.
1016 2018-09-13 Jan Beulich <jbeulich@suse.com>
1018 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
1019 * i386-tbl.h: Re-generate.
1021 2018-09-13 Jan Beulich <jbeulich@suse.com>
1023 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
1025 * i386-tbl.h: Re-generate.
1027 2018-09-13 Jan Beulich <jbeulich@suse.com>
1029 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
1031 * i386-tbl.h: Re-generate.
1033 2018-09-13 Jan Beulich <jbeulich@suse.com>
1035 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
1036 * i386-tbl.h: Re-generate.
1038 2018-09-13 Jan Beulich <jbeulich@suse.com>
1040 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
1041 * i386-tbl.h: Re-generate.
1043 2018-09-13 Jan Beulich <jbeulich@suse.com>
1045 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
1046 * i386-tbl.h: Re-generate.
1048 2018-09-13 Jan Beulich <jbeulich@suse.com>
1050 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
1052 * i386-tbl.h: Re-generate.
1054 2018-09-13 Jan Beulich <jbeulich@suse.com>
1056 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
1058 * i386-tbl.h: Re-generate.
1060 2018-09-13 Jan Beulich <jbeulich@suse.com>
1062 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
1064 * i386-tbl.h: Re-generate.
1066 2018-09-13 Jan Beulich <jbeulich@suse.com>
1068 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
1069 * i386-tbl.h: Re-generate.
1071 2018-09-13 Jan Beulich <jbeulich@suse.com>
1073 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
1074 * i386-tbl.h: Re-generate.
1076 2018-09-13 Jan Beulich <jbeulich@suse.com>
1078 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
1079 * i386-tbl.h: Re-generate.
1081 2018-09-13 Jan Beulich <jbeulich@suse.com>
1083 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
1084 (vpbroadcastw, rdpid): Drop NoRex64.
1085 * i386-tbl.h: Re-generate.
1087 2018-09-13 Jan Beulich <jbeulich@suse.com>
1089 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
1090 store templates, adding D.
1091 * i386-tbl.h: Re-generate.
1093 2018-09-13 Jan Beulich <jbeulich@suse.com>
1095 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
1096 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
1097 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
1098 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
1099 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
1100 Fold load and store templates where possible, adding D. Drop
1101 IgnoreSize where it was pointlessly present. Drop redundant
1103 * i386-tbl.h: Re-generate.
1105 2018-09-13 Jan Beulich <jbeulich@suse.com>
1107 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
1108 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
1109 (intel_operand_size): Handle v_bndmk_mode.
1110 (OP_E_memory): Likewise. Produce (bad) when also riprel.
1112 2018-09-08 John Darrington <john@darrington.wattle.id.au>
1114 * disassemble.c (ARCH_s12z): Define if ARCH_all.
1116 2018-08-31 Kito Cheng <kito@andestech.com>
1118 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
1119 compressed floating point instructions.
1121 2018-08-30 Kito Cheng <kito@andestech.com>
1123 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
1124 riscv_opcode.xlen_requirement.
1125 * riscv-opc.c (riscv_opcodes): Update for struct change.
1127 2018-08-29 Martin Aberg <maberg@gaisler.com>
1129 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
1130 psr (PWRPSR) instruction.
1132 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1134 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
1136 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1138 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
1140 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1142 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
1143 loongson3a as an alias of gs464 for compatibility.
1144 * mips-opc.c (mips_opcodes): Change Comments.
1146 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1148 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
1150 (print_mips_disassembler_options): Document -M loongson-ext.
1151 * mips-opc.c (LEXT2): New macro.
1152 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
1154 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1156 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
1158 (parse_mips_ase_option): Handle -M loongson-ext option.
1159 (print_mips_disassembler_options): Document -M loongson-ext.
1160 * mips-opc.c (IL3A): Delete.
1161 * mips-opc.c (LEXT): New macro.
1162 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
1165 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1167 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
1169 (parse_mips_ase_option): Handle -M loongson-cam option.
1170 (print_mips_disassembler_options): Document -M loongson-cam.
1171 * mips-opc.c (LCAM): New macro.
1172 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
1175 2018-08-21 Alan Modra <amodra@gmail.com>
1177 * ppc-dis.c (operand_value_powerpc): Init "invalid".
1178 (skip_optional_operands): Count optional operands, and update
1179 ppc_optional_operand_value call.
1180 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
1181 (extract_vlensi): Likewise.
1182 (extract_fxm): Return default value for missing optional operand.
1183 (extract_ls, extract_raq, extract_tbr): Likewise.
1184 (insert_sxl, extract_sxl): New functions.
1185 (insert_esync, extract_esync): Remove Power9 handling and simplify.
1186 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
1187 flag and extra entry.
1188 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
1191 2018-08-20 Alan Modra <amodra@gmail.com>
1193 * sh-opc.h (MASK): Simplify.
1195 2018-08-18 John Darrington <john@darrington.wattle.id.au>
1197 * s12z-dis.c (bm_decode): Deal with cases where the mode is
1198 BM_RESERVED0 or BM_RESERVED1
1199 (bm_rel_decode, bm_n_bytes): Ditto.
1201 2018-08-18 John Darrington <john@darrington.wattle.id.au>
1205 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
1207 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1208 address with the addr32 prefix and without base nor index
1211 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
1213 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1214 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1215 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1216 (cpu_flags): Add CpuCMOV and CpuFXSR.
1217 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1218 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
1219 * i386-init.h: Regenerated.
1220 * i386-tbl.h: Likewise.
1222 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
1224 * arc-regs.h: Update auxiliary registers.
1226 2018-08-06 Jan Beulich <jbeulich@suse.com>
1228 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1229 (RegIP, RegIZ): Define.
1230 * i386-reg.tbl: Adjust comments.
1231 (rip): Use Qword instead of BaseIndex. Use RegIP.
1232 (eip): Use Dword instead of BaseIndex. Use RegIP.
1233 (riz): Add Qword. Use RegIZ.
1234 (eiz): Add Dword. Use RegIZ.
1235 * i386-tbl.h: Re-generate.
1237 2018-08-03 Jan Beulich <jbeulich@suse.com>
1239 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1240 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1241 vpmovzxdq, vpmovzxwd): Remove NoRex64.
1242 * i386-tbl.h: Re-generate.
1244 2018-08-03 Jan Beulich <jbeulich@suse.com>
1246 * i386-gen.c (operand_types): Remove Mem field.
1247 * i386-opc.h (union i386_operand_type): Remove mem field.
1248 * i386-init.h, i386-tbl.h: Re-generate.
1250 2018-08-01 Alan Modra <amodra@gmail.com>
1252 * po/POTFILES.in: Regenerate.
1254 2018-07-31 Nick Clifton <nickc@redhat.com>
1256 * po/sv.po: Updated Swedish translation.
1258 2018-07-31 Jan Beulich <jbeulich@suse.com>
1260 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1261 * i386-init.h, i386-tbl.h: Re-generate.
1263 2018-07-31 Jan Beulich <jbeulich@suse.com>
1265 * i386-opc.h (ZEROING_MASKING) Rename to ...
1266 (DYNAMIC_MASKING): ... this. Adjust comment.
1267 * i386-opc.tbl (MaskingMorZ): Define.
1268 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1269 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1270 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1271 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1272 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1273 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1274 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1275 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1276 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1278 2018-07-31 Jan Beulich <jbeulich@suse.com>
1280 * i386-opc.tbl: Use element rather than vector size for AVX512*
1281 scatter/gather insns.
1282 * i386-tbl.h: Re-generate.
1284 2018-07-31 Jan Beulich <jbeulich@suse.com>
1286 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1287 (cpu_flags): Drop CpuVREX.
1288 * i386-opc.h (CpuVREX): Delete.
1289 (union i386_cpu_flags): Remove cpuvrex.
1290 * i386-init.h, i386-tbl.h: Re-generate.
1292 2018-07-30 Jim Wilson <jimw@sifive.com>
1294 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1296 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1298 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
1300 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1301 * Makefile.in: Regenerated.
1302 * configure.ac: Add C-SKY.
1303 * configure: Regenerated.
1304 * csky-dis.c: New file.
1305 * csky-opc.h: New file.
1306 * disassemble.c (ARCH_csky): Define.
1307 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1308 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1310 2018-07-27 Alan Modra <amodra@gmail.com>
1312 * ppc-opc.c (insert_sprbat): Correct function parameter and
1314 (extract_sprbat): Likewise, variable too.
1316 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
1317 Alan Modra <amodra@gmail.com>
1319 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1320 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1321 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1322 support disjointed BAT.
1323 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
1324 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1325 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1327 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
1328 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1330 * i386-gen.c (adjust_broadcast_modifier): New function.
1331 (process_i386_opcode_modifier): Add an argument for operands.
1332 Adjust the Broadcast value based on operands.
1333 (output_i386_opcode): Pass operand_types to
1334 process_i386_opcode_modifier.
1335 (process_i386_opcodes): Pass NULL as operands to
1336 process_i386_opcode_modifier.
1337 * i386-opc.h (BYTE_BROADCAST): New.
1338 (WORD_BROADCAST): Likewise.
1339 (DWORD_BROADCAST): Likewise.
1340 (QWORD_BROADCAST): Likewise.
1341 (i386_opcode_modifier): Expand broadcast to 3 bits.
1342 * i386-tbl.h: Regenerated.
1344 2018-07-24 Alan Modra <amodra@gmail.com>
1347 * or1k-desc.h: Regenerate.
1349 2018-07-24 Jan Beulich <jbeulich@suse.com>
1351 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1352 vcvtusi2ss, and vcvtusi2sd.
1353 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1354 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1355 * i386-tbl.h: Re-generate.
1357 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1359 * arc-opc.c (extract_w6): Fix extending the sign.
1361 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1363 * arc-tbl.h (vewt): Allow it for ARC EM family.
1365 2018-07-23 Alan Modra <amodra@gmail.com>
1368 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1369 opcode variants for mtspr/mfspr encodings.
1371 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
1372 Maciej W. Rozycki <macro@mips.com>
1374 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1375 loongson3a descriptors.
1376 (parse_mips_ase_option): Handle -M loongson-mmi option.
1377 (print_mips_disassembler_options): Document -M loongson-mmi.
1378 * mips-opc.c (LMMI): New macro.
1379 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1382 2018-07-19 Jan Beulich <jbeulich@suse.com>
1384 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1385 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1386 IgnoreSize and [XYZ]MMword where applicable.
1387 * i386-tbl.h: Re-generate.
1389 2018-07-19 Jan Beulich <jbeulich@suse.com>
1391 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1392 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1393 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1394 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1395 * i386-tbl.h: Re-generate.
1397 2018-07-19 Jan Beulich <jbeulich@suse.com>
1399 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1400 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1401 VPCLMULQDQ templates into their respective AVX512VL counterparts
1402 where possible, using Disp8ShiftVL and CheckRegSize instead of
1403 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1404 * i386-tbl.h: Re-generate.
1406 2018-07-19 Jan Beulich <jbeulich@suse.com>
1408 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1409 AVX512VL counterparts where possible, using Disp8ShiftVL and
1410 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1411 IgnoreSize) as appropriate.
1412 * i386-tbl.h: Re-generate.
1414 2018-07-19 Jan Beulich <jbeulich@suse.com>
1416 * i386-opc.tbl: Fold AVX512BW templates into their respective
1417 AVX512VL counterparts where possible, using Disp8ShiftVL and
1418 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1419 IgnoreSize) as appropriate.
1420 * i386-tbl.h: Re-generate.
1422 2018-07-19 Jan Beulich <jbeulich@suse.com>
1424 * i386-opc.tbl: Fold AVX512CD templates into their respective
1425 AVX512VL counterparts where possible, using Disp8ShiftVL and
1426 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1427 IgnoreSize) as appropriate.
1428 * i386-tbl.h: Re-generate.
1430 2018-07-19 Jan Beulich <jbeulich@suse.com>
1432 * i386-opc.h (DISP8_SHIFT_VL): New.
1433 * i386-opc.tbl (Disp8ShiftVL): Define.
1434 (various): Fold AVX512VL templates into their respective
1435 AVX512F counterparts where possible, using Disp8ShiftVL and
1436 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1437 IgnoreSize) as appropriate.
1438 * i386-tbl.h: Re-generate.
1440 2018-07-19 Jan Beulich <jbeulich@suse.com>
1442 * Makefile.am: Change dependencies and rule for
1443 $(srcdir)/i386-init.h.
1444 * Makefile.in: Re-generate.
1445 * i386-gen.c (process_i386_opcodes): New local variable
1446 "marker". Drop opening of input file. Recognize marker and line
1448 * i386-opc.tbl (OPCODE_I386_H): Define.
1449 (i386-opc.h): Include it.
1452 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1455 * i386-opc.h (Byte): Update comments.
1461 (Xmmword): Likewise.
1462 (Ymmword): Likewise.
1463 (Zmmword): Likewise.
1464 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1466 * i386-tbl.h: Regenerated.
1468 2018-07-12 Sudakshina Das <sudi.das@arm.com>
1470 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1471 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1472 * aarch64-asm-2.c: Regenerate.
1473 * aarch64-dis-2.c: Regenerate.
1474 * aarch64-opc-2.c: Regenerate.
1476 2018-07-12 Tamar Christina <tamar.christina@arm.com>
1479 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1480 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1481 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1482 sqdmulh, sqrdmulh): Use Em16.
1484 2018-07-11 Sudakshina Das <sudi.das@arm.com>
1486 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1487 csdb together with them.
1488 (thumb32_opcodes): Likewise.
1490 2018-07-11 Jan Beulich <jbeulich@suse.com>
1492 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1493 requiring 32-bit registers as operands 2 and 3. Improve
1495 (mwait, mwaitx): Fold templates. Improve comments.
1496 OPERAND_TYPE_INOUTPORTREG.
1497 * i386-tbl.h: Re-generate.
1499 2018-07-11 Jan Beulich <jbeulich@suse.com>
1501 * i386-gen.c (operand_type_init): Remove
1502 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1503 OPERAND_TYPE_INOUTPORTREG.
1504 * i386-init.h: Re-generate.
1506 2018-07-11 Jan Beulich <jbeulich@suse.com>
1508 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1509 (wrssq, wrussq): Add Qword.
1510 * i386-tbl.h: Re-generate.
1512 2018-07-11 Jan Beulich <jbeulich@suse.com>
1514 * i386-opc.h: Rename OTMax to OTNum.
1515 (OTNumOfUints): Adjust calculation.
1516 (OTUnused): Directly alias to OTNum.
1518 2018-07-09 Maciej W. Rozycki <macro@mips.com>
1520 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1522 (lea_reg_xys): Likewise.
1523 (print_insn_loop_primitive): Rename `reg' local variable to
1526 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1529 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1531 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1534 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1535 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1537 2018-07-02 Maciej W. Rozycki <macro@mips.com>
1540 * mips-dis.c (mips_option_arg_t): New enumeration.
1541 (mips_options): New variable.
1542 (disassembler_options_mips): New function.
1543 (print_mips_disassembler_options): Reimplement in terms of
1544 `disassembler_options_mips'.
1545 * arm-dis.c (disassembler_options_arm): Adapt to using the
1546 `disasm_options_and_args_t' structure.
1547 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1548 * s390-dis.c (disassembler_options_s390): Likewise.
1550 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1552 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1554 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1555 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1556 * testsuite/ld-arm/tls-longplt.d: Likewise.
1558 2018-06-29 Tamar Christina <tamar.christina@arm.com>
1561 * aarch64-asm-2.c: Regenerate.
1562 * aarch64-dis-2.c: Likewise.
1563 * aarch64-opc-2.c: Likewise.
1564 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1565 * aarch64-opc.c (operand_general_constraint_met_p,
1566 aarch64_print_operand): Likewise.
1567 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1568 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1570 (AARCH64_OPERANDS): Add Em2.
1572 2018-06-26 Nick Clifton <nickc@redhat.com>
1574 * po/uk.po: Updated Ukranian translation.
1575 * po/de.po: Updated German translation.
1576 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1578 2018-06-26 Nick Clifton <nickc@redhat.com>
1580 * nfp-dis.c: Fix spelling mistake.
1582 2018-06-24 Nick Clifton <nickc@redhat.com>
1584 * configure: Regenerate.
1585 * po/opcodes.pot: Regenerate.
1587 2018-06-24 Nick Clifton <nickc@redhat.com>
1589 2.31 branch created.
1591 2018-06-19 Tamar Christina <tamar.christina@arm.com>
1593 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1594 * aarch64-asm-2.c: Regenerate.
1595 * aarch64-dis-2.c: Likewise.
1597 2018-06-21 Maciej W. Rozycki <macro@mips.com>
1599 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1600 `-M ginv' option description.
1602 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1605 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1608 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1610 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1611 * configure.ac: Remove AC_PREREQ.
1612 * Makefile.in: Re-generate.
1613 * aclocal.m4: Re-generate.
1614 * configure: Re-generate.
1616 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1618 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1619 mips64r6 descriptors.
1620 (parse_mips_ase_option): Handle -Mginv option.
1621 (print_mips_disassembler_options): Document -Mginv.
1622 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1624 (mips_opcodes): Define ginvi and ginvt.
1626 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1627 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1629 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1630 * mips-opc.c (CRC, CRC64): New macros.
1631 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1632 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1635 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1638 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1639 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1641 2018-06-06 Alan Modra <amodra@gmail.com>
1643 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1644 setjmp. Move init for some other vars later too.
1646 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1648 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1649 (dis_private): Add new fields for property section tracking.
1650 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1651 (xtensa_instruction_fits): New functions.
1652 (fetch_data): Bump minimal fetch size to 4.
1653 (print_insn_xtensa): Make struct dis_private static.
1654 Load and prepare property table on section change.
1655 Don't disassemble literals. Don't disassemble instructions that
1656 cross property table boundaries.
1658 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1660 * configure: Regenerated.
1662 2018-06-01 Jan Beulich <jbeulich@suse.com>
1664 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1665 * i386-tbl.h: Re-generate.
1667 2018-06-01 Jan Beulich <jbeulich@suse.com>
1669 * i386-opc.tbl (sldt, str): Add NoRex64.
1670 * i386-tbl.h: Re-generate.
1672 2018-06-01 Jan Beulich <jbeulich@suse.com>
1674 * i386-opc.tbl (invpcid): Add Oword.
1675 * i386-tbl.h: Re-generate.
1677 2018-06-01 Alan Modra <amodra@gmail.com>
1679 * sysdep.h (_bfd_error_handler): Don't declare.
1680 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1681 * rl78-decode.opc: Likewise.
1682 * msp430-decode.c: Regenerate.
1683 * rl78-decode.c: Regenerate.
1685 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1687 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1688 * i386-init.h : Regenerated.
1690 2018-05-25 Alan Modra <amodra@gmail.com>
1692 * Makefile.in: Regenerate.
1693 * po/POTFILES.in: Regenerate.
1695 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1697 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1698 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1699 (insert_bab, extract_bab, insert_btab, extract_btab,
1700 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1701 (BAT, BBA VBA RBS XB6S): Delete macros.
1702 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1703 (BB, BD, RBX, XC6): Update for new macros.
1704 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1705 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1706 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1707 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1709 2018-05-18 John Darrington <john@darrington.wattle.id.au>
1711 * Makefile.am: Add support for s12z architecture.
1712 * configure.ac: Likewise.
1713 * disassemble.c: Likewise.
1714 * disassemble.h: Likewise.
1715 * Makefile.in: Regenerate.
1716 * configure: Regenerate.
1717 * s12z-dis.c: New file.
1720 2018-05-18 Alan Modra <amodra@gmail.com>
1722 * nfp-dis.c: Don't #include libbfd.h.
1723 (init_nfp3200_priv): Use bfd_get_section_contents.
1724 (nit_nfp6000_mecsr_sec): Likewise.
1726 2018-05-17 Nick Clifton <nickc@redhat.com>
1728 * po/zh_CN.po: Updated simplified Chinese translation.
1730 2018-05-16 Tamar Christina <tamar.christina@arm.com>
1733 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1734 * aarch64-dis-2.c: Regenerate.
1736 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1739 * aarch64-asm.c (opintl.h): Include.
1740 (aarch64_ins_sysreg): Enforce read/write constraints.
1741 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1742 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1743 (F_REG_READ, F_REG_WRITE): New.
1744 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1745 AARCH64_OPND_SYSREG.
1746 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1747 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1748 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1749 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1750 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1751 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1752 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1753 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1754 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1755 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1756 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1757 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1758 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1759 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1760 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1761 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1762 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1764 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1767 * aarch64-dis.c (no_notes: New.
1768 (parse_aarch64_dis_option): Support notes.
1769 (aarch64_decode_insn, print_operands): Likewise.
1770 (print_aarch64_disassembler_options): Document notes.
1771 * aarch64-opc.c (aarch64_print_operand): Support notes.
1773 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1776 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1777 and take error struct.
1778 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1779 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1780 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1781 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1782 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1783 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1784 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1785 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1786 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1787 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1788 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1789 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1790 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1791 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1792 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1793 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1794 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1795 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1796 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1797 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1798 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1799 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1800 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1801 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1802 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1803 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1804 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1805 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1806 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1807 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1808 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1809 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1810 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1811 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1812 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1813 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1814 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1815 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1816 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1817 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1818 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1819 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1820 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1821 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1822 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1823 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1824 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1825 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1826 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1827 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1828 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1829 (determine_disassembling_preference, aarch64_decode_insn,
1830 print_insn_aarch64_word, print_insn_data): Take errors struct.
1831 (print_insn_aarch64): Use errors.
1832 * aarch64-asm-2.c: Regenerate.
1833 * aarch64-dis-2.c: Regenerate.
1834 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1835 boolean in aarch64_insert_operan.
1836 (print_operand_extractor): Likewise.
1837 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1839 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
1841 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1843 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1845 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1847 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1849 * cr16-opc.c (cr16_instruction): Comment typo fix.
1850 * hppa-dis.c (print_insn_hppa): Likewise.
1852 2018-05-08 Jim Wilson <jimw@sifive.com>
1854 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1855 (match_c_slli64, match_srxi_as_c_srxi): New.
1856 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1857 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1858 <c.slli, c.srli, c.srai>: Use match_s_slli.
1859 <c.slli64, c.srli64, c.srai64>: New.
1861 2018-05-08 Alan Modra <amodra@gmail.com>
1863 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1864 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1865 partition opcode space for index lookup.
1867 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1869 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1870 <insn_length>: ...with this. Update usage.
1871 Remove duplicate call to *info->memory_error_func.
1873 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1874 H.J. Lu <hongjiu.lu@intel.com>
1876 * i386-dis.c (Gva): New.
1877 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1878 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1879 (prefix_table): New instructions (see prefix above).
1880 (mod_table): New instructions (see prefix above).
1881 (OP_G): Handle va_mode.
1882 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1883 CPU_MOVDIR64B_FLAGS.
1884 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1885 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1886 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1887 * i386-opc.tbl: Add movidir{i,64b}.
1888 * i386-init.h: Regenerated.
1889 * i386-tbl.h: Likewise.
1891 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1893 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1895 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1896 (AddrPrefixOpReg): This.
1897 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1898 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1900 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1902 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1903 (vle_num_opcodes): Likewise.
1904 (spe2_num_opcodes): Likewise.
1905 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1906 initialization loop.
1907 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1908 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1911 2018-05-01 Tamar Christina <tamar.christina@arm.com>
1913 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1915 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
1917 Makefile.am: Added nfp-dis.c.
1918 configure.ac: Added bfd_nfp_arch.
1919 disassemble.h: Added print_insn_nfp prototype.
1920 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1921 nfp-dis.c: New, for NFP support.
1922 po/POTFILES.in: Added nfp-dis.c to the list.
1923 Makefile.in: Regenerate.
1924 configure: Regenerate.
1926 2018-04-26 Jan Beulich <jbeulich@suse.com>
1928 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1929 templates into their base ones.
1930 * i386-tlb.h: Re-generate.
1932 2018-04-26 Jan Beulich <jbeulich@suse.com>
1934 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1935 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1936 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1937 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1938 * i386-init.h: Re-generate.
1940 2018-04-26 Jan Beulich <jbeulich@suse.com>
1942 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1943 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1944 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1945 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1947 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1949 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1951 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1952 cpuregzmm, and cpuregmask.
1953 * i386-init.h: Re-generate.
1954 * i386-tbl.h: Re-generate.
1956 2018-04-26 Jan Beulich <jbeulich@suse.com>
1958 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1959 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1960 * i386-init.h: Re-generate.
1962 2018-04-26 Jan Beulich <jbeulich@suse.com>
1964 * i386-gen.c (VexImmExt): Delete.
1965 * i386-opc.h (VexImmExt, veximmext): Delete.
1966 * i386-opc.tbl: Drop all VexImmExt uses.
1967 * i386-tlb.h: Re-generate.
1969 2018-04-25 Jan Beulich <jbeulich@suse.com>
1971 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1972 register-only forms.
1973 * i386-tlb.h: Re-generate.
1975 2018-04-25 Tamar Christina <tamar.christina@arm.com>
1977 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1979 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1981 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1983 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1984 (cpu_flags): Add CpuCLDEMOTE.
1985 * i386-init.h: Regenerate.
1986 * i386-opc.h (enum): Add CpuCLDEMOTE,
1987 (i386_cpu_flags): Add cpucldemote.
1988 * i386-opc.tbl: Add cldemote.
1989 * i386-tbl.h: Regenerate.
1991 2018-04-16 Alan Modra <amodra@gmail.com>
1993 * Makefile.am: Remove sh5 and sh64 support.
1994 * configure.ac: Likewise.
1995 * disassemble.c: Likewise.
1996 * disassemble.h: Likewise.
1997 * sh-dis.c: Likewise.
1998 * sh64-dis.c: Delete.
1999 * sh64-opc.c: Delete.
2000 * sh64-opc.h: Delete.
2001 * Makefile.in: Regenerate.
2002 * configure: Regenerate.
2003 * po/POTFILES.in: Regenerate.
2005 2018-04-16 Alan Modra <amodra@gmail.com>
2007 * Makefile.am: Remove w65 support.
2008 * configure.ac: Likewise.
2009 * disassemble.c: Likewise.
2010 * disassemble.h: Likewise.
2011 * w65-dis.c: Delete.
2012 * w65-opc.h: Delete.
2013 * Makefile.in: Regenerate.
2014 * configure: Regenerate.
2015 * po/POTFILES.in: Regenerate.
2017 2018-04-16 Alan Modra <amodra@gmail.com>
2019 * configure.ac: Remove we32k support.
2020 * configure: Regenerate.
2022 2018-04-16 Alan Modra <amodra@gmail.com>
2024 * Makefile.am: Remove m88k support.
2025 * configure.ac: Likewise.
2026 * disassemble.c: Likewise.
2027 * disassemble.h: Likewise.
2028 * m88k-dis.c: Delete.
2029 * Makefile.in: Regenerate.
2030 * configure: Regenerate.
2031 * po/POTFILES.in: Regenerate.
2033 2018-04-16 Alan Modra <amodra@gmail.com>
2035 * Makefile.am: Remove i370 support.
2036 * configure.ac: Likewise.
2037 * disassemble.c: Likewise.
2038 * disassemble.h: Likewise.
2039 * i370-dis.c: Delete.
2040 * i370-opc.c: Delete.
2041 * Makefile.in: Regenerate.
2042 * configure: Regenerate.
2043 * po/POTFILES.in: Regenerate.
2045 2018-04-16 Alan Modra <amodra@gmail.com>
2047 * Makefile.am: Remove h8500 support.
2048 * configure.ac: Likewise.
2049 * disassemble.c: Likewise.
2050 * disassemble.h: Likewise.
2051 * h8500-dis.c: Delete.
2052 * h8500-opc.h: Delete.
2053 * Makefile.in: Regenerate.
2054 * configure: Regenerate.
2055 * po/POTFILES.in: Regenerate.
2057 2018-04-16 Alan Modra <amodra@gmail.com>
2059 * configure.ac: Remove tahoe support.
2060 * configure: Regenerate.
2062 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
2064 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
2066 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
2068 * i386-tbl.h: Regenerated.
2070 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2072 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
2073 PREFIX_MOD_1_0FAE_REG_6.
2075 (OP_E_register): Use va_mode.
2076 * i386-dis-evex.h (prefix_table):
2077 New instructions (see prefixes above).
2078 * i386-gen.c (cpu_flag_init): Add WAITPKG.
2079 (cpu_flags): Likewise.
2080 * i386-opc.h (enum): Likewise.
2081 (i386_cpu_flags): Likewise.
2082 * i386-opc.tbl: Add umonitor, umwait, tpause.
2083 * i386-init.h: Regenerate.
2084 * i386-tbl.h: Likewise.
2086 2018-04-11 Alan Modra <amodra@gmail.com>
2088 * opcodes/i860-dis.c: Delete.
2089 * opcodes/i960-dis.c: Delete.
2090 * Makefile.am: Remove i860 and i960 support.
2091 * configure.ac: Likewise.
2092 * disassemble.c: Likewise.
2093 * disassemble.h: Likewise.
2094 * Makefile.in: Regenerate.
2095 * configure: Regenerate.
2096 * po/POTFILES.in: Regenerate.
2098 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
2101 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
2103 (print_insn): Clear vex instead of vex.evex.
2105 2018-04-04 Nick Clifton <nickc@redhat.com>
2107 * po/es.po: Updated Spanish translation.
2109 2018-03-28 Jan Beulich <jbeulich@suse.com>
2111 * i386-gen.c (opcode_modifiers): Delete VecESize.
2112 * i386-opc.h (VecESize): Delete.
2113 (struct i386_opcode_modifier): Delete vecesize.
2114 * i386-opc.tbl: Drop VecESize.
2115 * i386-tlb.h: Re-generate.
2117 2018-03-28 Jan Beulich <jbeulich@suse.com>
2119 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
2120 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
2121 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
2122 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
2123 * i386-tlb.h: Re-generate.
2125 2018-03-28 Jan Beulich <jbeulich@suse.com>
2127 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
2129 * i386-tlb.h: Re-generate.
2131 2018-03-28 Jan Beulich <jbeulich@suse.com>
2133 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
2134 (vex_len_table): Drop Y for vcvt*2si.
2135 (putop): Replace plain 'Y' handling by abort().
2137 2018-03-28 Nick Clifton <nickc@redhat.com>
2140 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
2141 instructions with only a base address register.
2142 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
2143 handle AARHC64_OPND_SVE_ADDR_R.
2144 (aarch64_print_operand): Likewise.
2145 * aarch64-asm-2.c: Regenerate.
2146 * aarch64_dis-2.c: Regenerate.
2147 * aarch64-opc-2.c: Regenerate.
2149 2018-03-22 Jan Beulich <jbeulich@suse.com>
2151 * i386-opc.tbl: Drop VecESize from register only insn forms and
2152 memory forms not allowing broadcast.
2153 * i386-tlb.h: Re-generate.
2155 2018-03-22 Jan Beulich <jbeulich@suse.com>
2157 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
2158 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
2159 sha256*): Drop Disp<N>.
2161 2018-03-22 Jan Beulich <jbeulich@suse.com>
2163 * i386-dis.c (EbndS, bnd_swap_mode): New.
2164 (prefix_table): Use EbndS.
2165 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
2166 * i386-opc.tbl (bndmov): Move misplaced Load.
2167 * i386-tlb.h: Re-generate.
2169 2018-03-22 Jan Beulich <jbeulich@suse.com>
2171 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
2172 templates allowing memory operands and folded ones for register
2174 * i386-tlb.h: Re-generate.
2176 2018-03-22 Jan Beulich <jbeulich@suse.com>
2178 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
2179 256-bit templates. Drop redundant leftover Disp<N>.
2180 * i386-tlb.h: Re-generate.
2182 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
2184 * riscv-opc.c (riscv_insn_types): New.
2186 2018-03-13 Nick Clifton <nickc@redhat.com>
2188 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2190 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2192 * i386-opc.tbl: Add Optimize to clr.
2193 * i386-tbl.h: Regenerated.
2195 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2197 * i386-gen.c (opcode_modifiers): Remove OldGcc.
2198 * i386-opc.h (OldGcc): Removed.
2199 (i386_opcode_modifier): Remove oldgcc.
2200 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2201 instructions for old (<= 2.8.1) versions of gcc.
2202 * i386-tbl.h: Regenerated.
2204 2018-03-08 Jan Beulich <jbeulich@suse.com>
2206 * i386-opc.h (EVEXDYN): New.
2207 * i386-opc.tbl: Fold various AVX512VL templates.
2208 * i386-tlb.h: Re-generate.
2210 2018-03-08 Jan Beulich <jbeulich@suse.com>
2212 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2213 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2214 vpexpandd, vpexpandq): Fold AFX512VF templates.
2215 * i386-tlb.h: Re-generate.
2217 2018-03-08 Jan Beulich <jbeulich@suse.com>
2219 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2220 Fold 128- and 256-bit VEX-encoded templates.
2221 * i386-tlb.h: Re-generate.
2223 2018-03-08 Jan Beulich <jbeulich@suse.com>
2225 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2226 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2227 vpexpandd, vpexpandq): Fold AVX512F templates.
2228 * i386-tlb.h: Re-generate.
2230 2018-03-08 Jan Beulich <jbeulich@suse.com>
2232 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2233 64-bit templates. Drop Disp<N>.
2234 * i386-tlb.h: Re-generate.
2236 2018-03-08 Jan Beulich <jbeulich@suse.com>
2238 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2239 and 256-bit templates.
2240 * i386-tlb.h: Re-generate.
2242 2018-03-08 Jan Beulich <jbeulich@suse.com>
2244 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2245 * i386-tlb.h: Re-generate.
2247 2018-03-08 Jan Beulich <jbeulich@suse.com>
2249 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2251 * i386-tlb.h: Re-generate.
2253 2018-03-08 Jan Beulich <jbeulich@suse.com>
2255 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2256 * i386-tlb.h: Re-generate.
2258 2018-03-08 Jan Beulich <jbeulich@suse.com>
2260 * i386-gen.c (opcode_modifiers): Delete FloatD.
2261 * i386-opc.h (FloatD): Delete.
2262 (struct i386_opcode_modifier): Delete floatd.
2263 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2265 * i386-tlb.h: Re-generate.
2267 2018-03-08 Jan Beulich <jbeulich@suse.com>
2269 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2271 2018-03-08 Jan Beulich <jbeulich@suse.com>
2273 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2274 * i386-tlb.h: Re-generate.
2276 2018-03-08 Jan Beulich <jbeulich@suse.com>
2278 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2280 * i386-tlb.h: Re-generate.
2282 2018-03-07 Alan Modra <amodra@gmail.com>
2284 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2286 * disassemble.h (print_insn_rs6000): Delete.
2287 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2288 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2289 (print_insn_rs6000): Delete.
2291 2018-03-03 Alan Modra <amodra@gmail.com>
2293 * sysdep.h (opcodes_error_handler): Define.
2294 (_bfd_error_handler): Declare.
2295 * Makefile.am: Remove stray #.
2296 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
2298 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2299 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2300 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2301 opcodes_error_handler to print errors. Standardize error messages.
2302 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2303 and include opintl.h.
2304 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2305 * i386-gen.c: Standardize error messages.
2306 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2307 * Makefile.in: Regenerate.
2308 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2309 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2310 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2311 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2312 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2313 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2314 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2315 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2316 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2317 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2318 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2319 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2320 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2322 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
2324 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2325 vpsub[bwdq] instructions.
2326 * i386-tbl.h: Regenerated.
2328 2018-03-01 Alan Modra <amodra@gmail.com>
2330 * configure.ac (ALL_LINGUAS): Sort.
2331 * configure: Regenerate.
2333 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
2335 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2336 macro by assignements.
2338 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
2341 * i386-gen.c (opcode_modifiers): Add Optimize.
2342 * i386-opc.h (Optimize): New enum.
2343 (i386_opcode_modifier): Add optimize.
2344 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2345 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2346 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2347 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2348 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2350 * i386-tbl.h: Regenerated.
2352 2018-02-26 Alan Modra <amodra@gmail.com>
2354 * crx-dis.c (getregliststring): Allocate a large enough buffer
2355 to silence false positive gcc8 warning.
2357 2018-02-22 Shea Levy <shea@shealevy.com>
2359 * disassemble.c (ARCH_riscv): Define if ARCH_all.
2361 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
2363 * i386-opc.tbl: Add {rex},
2364 * i386-tbl.h: Regenerated.
2366 2018-02-20 Maciej W. Rozycki <macro@mips.com>
2368 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2369 (mips16_opcodes): Replace `M' with `m' for "restore".
2371 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
2373 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2375 2018-02-13 Maciej W. Rozycki <macro@mips.com>
2377 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2378 variable to `function_index'.
2380 2018-02-13 Nick Clifton <nickc@redhat.com>
2383 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2384 about truncation of printing.
2386 2018-02-12 Henry Wong <henry@stuffedcow.net>
2388 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2390 2018-02-05 Nick Clifton <nickc@redhat.com>
2392 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2394 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2396 * i386-dis.c (enum): Add pconfig.
2397 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2398 (cpu_flags): Add CpuPCONFIG.
2399 * i386-opc.h (enum): Add CpuPCONFIG.
2400 (i386_cpu_flags): Add cpupconfig.
2401 * i386-opc.tbl: Add PCONFIG instruction.
2402 * i386-init.h: Regenerate.
2403 * i386-tbl.h: Likewise.
2405 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2407 * i386-dis.c (enum): Add PREFIX_0F09.
2408 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2409 (cpu_flags): Add CpuWBNOINVD.
2410 * i386-opc.h (enum): Add CpuWBNOINVD.
2411 (i386_cpu_flags): Add cpuwbnoinvd.
2412 * i386-opc.tbl: Add WBNOINVD instruction.
2413 * i386-init.h: Regenerate.
2414 * i386-tbl.h: Likewise.
2416 2018-01-17 Jim Wilson <jimw@sifive.com>
2418 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2420 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2422 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2423 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2424 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2425 (cpu_flags): Add CpuIBT, CpuSHSTK.
2426 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2427 (i386_cpu_flags): Add cpuibt, cpushstk.
2428 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2429 * i386-init.h: Regenerate.
2430 * i386-tbl.h: Likewise.
2432 2018-01-16 Nick Clifton <nickc@redhat.com>
2434 * po/pt_BR.po: Updated Brazilian Portugese translation.
2435 * po/de.po: Updated German translation.
2437 2018-01-15 Jim Wilson <jimw@sifive.com>
2439 * riscv-opc.c (match_c_nop): New.
2440 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2442 2018-01-15 Nick Clifton <nickc@redhat.com>
2444 * po/uk.po: Updated Ukranian translation.
2446 2018-01-13 Nick Clifton <nickc@redhat.com>
2448 * po/opcodes.pot: Regenerated.
2450 2018-01-13 Nick Clifton <nickc@redhat.com>
2452 * configure: Regenerate.
2454 2018-01-13 Nick Clifton <nickc@redhat.com>
2456 2.30 branch created.
2458 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2460 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2461 * i386-tbl.h: Regenerate.
2463 2018-01-10 Jan Beulich <jbeulich@suse.com>
2465 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2466 * i386-tbl.h: Re-generate.
2468 2018-01-10 Jan Beulich <jbeulich@suse.com>
2470 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2471 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2472 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2473 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2474 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2475 Disp8MemShift of AVX512VL forms.
2476 * i386-tbl.h: Re-generate.
2478 2018-01-09 Jim Wilson <jimw@sifive.com>
2480 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2481 then the hi_addr value is zero.
2483 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2485 * arm-dis.c (arm_opcodes): Add csdb.
2486 (thumb32_opcodes): Add csdb.
2488 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2490 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2491 * aarch64-asm-2.c: Regenerate.
2492 * aarch64-dis-2.c: Regenerate.
2493 * aarch64-opc-2.c: Regenerate.
2495 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2498 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2499 Remove AVX512 vmovd with 64-bit operands.
2500 * i386-tbl.h: Regenerated.
2502 2018-01-05 Jim Wilson <jimw@sifive.com>
2504 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2507 2018-01-03 Alan Modra <amodra@gmail.com>
2509 Update year range in copyright notice of all files.
2511 2018-01-02 Jan Beulich <jbeulich@suse.com>
2513 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2514 and OPERAND_TYPE_REGZMM entries.
2516 For older changes see ChangeLog-2017
2518 Copyright (C) 2018 Free Software Foundation, Inc.
2520 Copying and distribution of this file, with or without modification,
2521 are permitted in any medium without royalty provided the copyright
2522 notice and this notice are preserved.
2528 version-control: never