1 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
2 Kirill Yukhin <kirill.yukhin@intel.com>
3 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
5 * i386-dis.c (BND_Fixup): New.
12 (MOD enum): Add new entries.
13 (PREFIX enum): Likewise.
14 (dis tables): Replace XX with BND for near branch and call
16 (prefix_table): Add new entries.
17 (mod_table): Likewise.
19 (intel_names_bnd): New.
22 (prefix_name): Handle BND_PREFIX.
23 (print_insn): Initialize names_bnd.
24 (intel_operand_size): Handle new modes.
25 (OP_E_register): Likewise.
26 (OP_E_memory): Likewise.
28 * i386-gen.c (cpu_flag_init): Add CpuMPX.
29 (cpu_flags): Add CpuMPX.
30 (operand_type_init): Add RegBND.
31 (opcode_modifiers): Add BNDPrefixOk.
32 (operand_types): Add RegBND.
33 * i386-init.h: Regenerate.
34 * i386-opc.h (CpuMPX): New.
35 (CpuUnused): Comment out.
36 (i386_cpu_flags): Add cpumpx.
38 (i386_opcode_modifier): Add bndprefixok.
40 (i386_operand_type): Add regbnd.
41 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
42 Add MPX instructions and bnd prefix.
43 * i386-reg.tbl: Add bnd0-bnd3 registers.
44 * i386-tbl.h: Regenerate.
46 2013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
48 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
51 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
53 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
55 * Makefile.in: Regenerate.
56 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
59 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
61 * mips16-opc.c: Include mips-formats.h.
62 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
64 (decode_mips16_operand): New function.
65 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
66 (print_insn_arg): Handle OP_ENTRY_EXIT list.
67 Abort for OP_SAVE_RESTORE_LIST.
68 (print_mips16_insn_arg): Change interface. Use mips_operand
69 structures. Delete GET_OP_S. Move GET_OP definition to...
70 (print_insn_mips16): ...here. Call init_print_arg_state.
71 Update the call to print_mips16_insn_arg.
73 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
75 * mips-formats.h: New file.
76 * mips-opc.c: Include mips-formats.h.
77 (reg_0_map): New static array.
78 (decode_mips_operand): New function.
79 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
80 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
81 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
82 (int_c_map): New static arrays.
83 (decode_micromips_operand): New function.
84 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
85 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
86 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
87 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
88 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
89 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
90 (micromips_imm_b_map, micromips_imm_c_map): Delete.
91 (print_reg): New function.
92 (mips_print_arg_state): New structure.
93 (init_print_arg_state, print_insn_arg): New functions.
94 (print_insn_args): Change interface and use mips_operand structures.
95 Delete GET_OP_S. Move GET_OP definition to...
96 (print_insn_mips): ...here. Update the call to print_insn_args.
97 (print_insn_micromips): Use print_insn_args.
99 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
101 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
104 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
106 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
107 ADDA.S, MULA.S and SUBA.S.
109 2013-07-08 H.J. Lu <hongjiu.lu@intel.com>
112 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
113 * i386-tbl.h: Regenerated.
115 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
117 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
118 and SD A(B) macros up.
119 * micromips-opc.c (micromips_opcodes): Likewise.
121 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
123 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
126 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
128 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
129 MDMX-like instructions.
130 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
131 printing "Q" operands for INSN_5400 instructions.
133 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
135 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
137 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
140 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
142 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
144 * mips16-opc.c (mips16_opcodes): Likewise.
145 * micromips-opc.c (micromips_opcodes): Likewise.
146 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
147 (print_insn_mips16): Handle "+i".
148 (print_insn_micromips): Likewise. Conditionally preserve the
149 ISA bit for "a" but not for "+i".
151 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
153 * micromips-opc.c (WR_mhi): Rename to..
155 (micromips_opcodes): Update "movep" entry accordingly. Replace
157 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
158 (micromips_to_32_reg_h_map1): ...this.
159 (micromips_to_32_reg_i_map): Rename to...
160 (micromips_to_32_reg_h_map2): ...this.
161 (print_micromips_insn): Remove "mi" case. Print both registers
162 in the pair for "mh".
164 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
166 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
167 * micromips-opc.c (micromips_opcodes): Likewise.
168 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
169 and "+T" handling. Check for a "0" suffix when deciding whether to
170 use coprocessor 0 names. In that case, also check for ",H" selectors.
172 2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
174 * s390-opc.c (J12_12, J24_24): New macros.
175 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
176 (MASK_MII_UPI): Rename to MASK_MII_UPP.
177 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
179 2013-07-04 Alan Modra <amodra@gmail.com>
181 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
183 2013-06-26 Nick Clifton <nickc@redhat.com>
185 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
186 field when checking for type 2 nop.
187 * rx-decode.c: Regenerate.
189 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
191 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
194 2013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
196 * mips-dis.c (is_mips16_plt_tail): New function.
197 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
199 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
201 2013-06-21 DJ Delorie <dj@redhat.com>
203 * msp430-decode.opc: New.
204 * msp430-decode.c: New/generated.
205 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
206 (MAINTAINER_CLEANFILES): Likewise.
207 Add rule to build msp430-decode.c frommsp430decode.opc
208 using the opc2c program.
209 * Makefile.in: Regenerate.
210 * configure.in: Add msp430-decode.lo to msp430 architecture files.
211 * configure: Regenerate.
213 2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
215 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
216 (SYMTAB_AVAILABLE): Removed.
217 (#include "elf/aarch64.h): Ditto.
219 2013-06-17 Catherine Moore <clm@codesourcery.com>
220 Maciej W. Rozycki <macro@codesourcery.com>
221 Chao-Ying Fu <fu@mips.com>
223 * micromips-opc.c (EVA): Define.
225 (micromips_opcodes): Add EVA opcodes.
226 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
227 (print_insn_args): Handle EVA offsets.
228 (print_insn_micromips): Likewise.
229 * mips-opc.c (EVA): Define.
231 (mips_builtin_opcodes): Add EVA opcodes.
233 2013-06-17 Alan Modra <amodra@gmail.com>
235 * Makefile.am (mips-opc.lo): Add rules to create automatic
236 dependency files. Pass archdefs.
237 (micromips-opc.lo, mips16-opc.lo): Likewise.
238 * Makefile.in: Regenerate.
240 2013-06-14 DJ Delorie <dj@redhat.com>
242 * rx-decode.opc (rx_decode_opcode): Bit operations on
243 registers are 32-bit operations, not 8-bit operations.
244 * rx-decode.c: Regenerate.
246 2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
248 * micromips-opc.c (IVIRT): New define.
249 (IVIRT64): New define.
250 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
251 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
253 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
254 dmtgc0 to print cp0 names.
256 2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
258 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
261 2013-06-08 Catherine Moore <clm@codesourcery.com>
262 Richard Sandiford <rdsandiford@googlemail.com>
264 * micromips-opc.c (D32, D33, MC): Update definitions.
265 (micromips_opcodes): Initialize ase field.
266 * mips-dis.c (mips_arch_choice): Add ase field.
267 (mips_arch_choices): Initialize ase field.
268 (set_default_mips_dis_options): Declare and setup mips_ase.
269 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
270 MT32, MC): Update definitions.
271 (mips_builtin_opcodes): Initialize ase field.
273 2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
275 * s390-opc.txt (flogr): Require a register pair destination.
277 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
279 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
282 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
284 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
286 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
288 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
289 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
290 XLS_MASK, PPCVSX2): New defines.
291 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
292 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
293 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
294 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
295 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
296 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
297 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
298 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
299 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
300 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
301 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
302 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
303 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
304 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
305 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
306 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
307 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
308 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
309 <lxvx, stxvx>: New extended mnemonics.
311 2013-05-17 Alan Modra <amodra@gmail.com>
313 * ia64-raw.tbl: Replace non-ASCII char.
314 * ia64-waw.tbl: Likewise.
315 * ia64-asmtab.c: Regenerate.
317 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
319 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
320 * i386-init.h: Regenerated.
322 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
324 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
325 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
326 check from [0, 255] to [-128, 255].
328 2013-05-09 Andrew Pinski <apinski@cavium.com>
330 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
331 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
332 (parse_mips_dis_option): Handle the virt option.
333 (print_insn_args): Handle "+J".
334 (print_mips_disassembler_options): Print out message about virt64.
335 * mips-opc.c (IVIRT): New define.
336 (IVIRT64): New define.
337 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
338 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
339 Move rfe to the bottom as it conflicts with tlbgp.
341 2013-05-09 Alan Modra <amodra@gmail.com>
343 * ppc-opc.c (extract_vlesi): Properly sign extend.
344 (extract_vlensi): Likewise. Comment reason for setting invalid.
346 2013-05-02 Nick Clifton <nickc@redhat.com>
348 * msp430-dis.c: Add support for MSP430X instructions.
350 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
352 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
355 2013-04-17 Wei-chen Wang <cole945@gmail.com>
358 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
360 (hash_insns_list): Likewise.
362 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
364 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
367 2013-04-08 Jan Beulich <jbeulich@suse.com>
369 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
370 * i386-tbl.h: Re-generate.
372 2013-04-06 David S. Miller <davem@davemloft.net>
374 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
375 of an opcode, prefer the one with F_PREFERRED set.
376 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
377 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
378 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
379 mark existing mnenomics as aliases. Add "cc" suffix to edge
380 instructions generating condition codes, mark existing mnenomics
381 as aliases. Add "fp" prefix to VIS compare instructions, mark
382 existing mnenomics as aliases.
384 2013-04-03 Nick Clifton <nickc@redhat.com>
386 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
387 destination address by subtracting the operand from the current
389 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
390 a positive value in the insn.
391 (extract_u16_loop): Do not negate the returned value.
392 (D16_LOOP): Add V850_INVERSE_PCREL flag.
394 (ceilf.sw): Remove duplicate entry.
395 (cvtf.hs): New entry.
401 (maddf.s): Restrict to E3V5 architectures.
403 (nmaddf.s): Likewise.
404 (nmsubf.s): Likewise.
406 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
408 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
410 (print_insn): Pass sizeflag to get_sib.
412 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
415 * tic6x-dis.c: Add support for displaying 16-bit insns.
417 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
420 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
421 individual msb and lsb halves in src1 & src2 fields. Discard the
422 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
423 follow what Ti SDK does in that case as any value in the src1
424 field yields the same output with SDK disassembler.
426 2013-03-12 Michael Eager <eager@eagercon.com>
428 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
430 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
432 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
434 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
436 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
438 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
440 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
442 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
444 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
445 (thumb32_opcodes): Likewise.
446 (print_insn_thumb32): Handle 'S' control char.
448 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
450 * lm32-desc.c: Regenerate.
452 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
454 * i386-reg.tbl (riz): Add RegRex64.
455 * i386-tbl.h: Regenerated.
457 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
459 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
460 (aarch64_feature_crc): New static.
462 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
463 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
464 * aarch64-asm-2.c: Re-generate.
465 * aarch64-dis-2.c: Ditto.
466 * aarch64-opc-2.c: Ditto.
468 2013-02-27 Alan Modra <amodra@gmail.com>
470 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
471 * rl78-decode.c: Regenerate.
473 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
475 * rl78-decode.opc: Fix encoding of DIVWU insn.
476 * rl78-decode.c: Regenerate.
478 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
481 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
483 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
484 (cpu_flags): Add CpuSMAP.
486 * i386-opc.h (CpuSMAP): New.
487 (i386_cpu_flags): Add cpusmap.
489 * i386-opc.tbl: Add clac and stac.
491 * i386-init.h: Regenerated.
492 * i386-tbl.h: Likewise.
494 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
496 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
497 which also makes the disassembler output be in little
498 endian like it should be.
500 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
502 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
504 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
506 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
508 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
509 section disassembled.
511 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
513 * arm-dis.c: Update strht pattern.
515 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
517 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
518 single-float. Disable ll, lld, sc and scd for EE. Disable the
519 trunc.w.s macro for EE.
521 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
522 Andrew Jenner <andrew@codesourcery.com>
524 Based on patches from Altera Corporation.
526 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
528 * Makefile.in: Regenerated.
529 * configure.in: Add case for bfd_nios2_arch.
530 * configure: Regenerated.
531 * disassemble.c (ARCH_nios2): Define.
532 (disassembler): Add case for bfd_arch_nios2.
533 * nios2-dis.c: New file.
534 * nios2-opc.c: New file.
536 2013-02-04 Alan Modra <amodra@gmail.com>
538 * po/POTFILES.in: Regenerate.
539 * rl78-decode.c: Regenerate.
540 * rx-decode.c: Regenerate.
542 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
544 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
545 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
546 * aarch64-asm.c (convert_xtl_to_shll): New function.
547 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
548 calling convert_xtl_to_shll.
549 * aarch64-dis.c (convert_shll_to_xtl): New function.
550 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
551 calling convert_shll_to_xtl.
552 * aarch64-gen.c: Update copyright year.
553 * aarch64-asm-2.c: Re-generate.
554 * aarch64-dis-2.c: Re-generate.
555 * aarch64-opc-2.c: Re-generate.
557 2013-01-24 Nick Clifton <nickc@redhat.com>
559 * v850-dis.c: Add support for e3v5 architecture.
560 * v850-opc.c: Likewise.
562 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
564 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
565 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
566 * aarch64-opc.c (operand_general_constraint_met_p): For
567 AARCH64_MOD_LSL, move the range check on the shift amount before the
568 alignment check; change to call set_sft_amount_out_of_range_error
569 instead of set_imm_out_of_range_error.
570 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
571 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
572 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
575 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
577 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
579 * i386-init.h: Regenerated.
580 * i386-tbl.h: Likewise.
582 2013-01-15 Nick Clifton <nickc@redhat.com>
584 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
586 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
588 2013-01-14 Will Newton <will.newton@imgtec.com>
590 * metag-dis.c (REG_WIDTH): Increase to 64.
592 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
594 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
595 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
596 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
598 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
599 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
600 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
601 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
603 2013-01-10 Will Newton <will.newton@imgtec.com>
605 * Makefile.am: Add Meta.
606 * configure.in: Add Meta.
607 * disassemble.c: Add Meta support.
608 * metag-dis.c: New file.
609 * Makefile.in: Regenerate.
610 * configure: Regenerate.
612 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
614 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
615 (match_opcode): Rename to cr16_match_opcode.
617 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
619 * mips-dis.c: Add names for CP0 registers of r5900.
620 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
621 instructions sq and lq.
622 Add support for MIPS r5900 CPU.
623 Add support for 128 bit MMI (Multimedia Instructions).
624 Add support for EE instructions (Emotion Engine).
625 Disable unsupported floating point instructions (64 bit and
626 undefined compare operations).
627 Enable instructions of MIPS ISA IV which are supported by r5900.
628 Disable 64 bit co processor instructions.
629 Disable 64 bit multiplication and division instructions.
630 Disable instructions for co-processor 2 and 3, because these are
631 not supported (preparation for later VU0 support (Vector Unit)).
632 Disable cvt.w.s because this behaves like trunc.w.s and the
633 correct execution can't be ensured on r5900.
634 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
635 will confuse less developers and compilers.
637 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
639 * aarch64-opc.c (aarch64_print_operand): Change to print
640 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
642 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
643 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
646 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
648 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
649 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
651 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
653 * i386-gen.c (process_copyright): Update copyright year to 2013.
655 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
657 * cr16-dis.c (match_opcode,make_instruction): Remove static
659 (dwordU,wordU): Moved typedefs to opcode/cr16.h
660 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
662 For older changes see ChangeLog-2012
664 Copyright (C) 2013 Free Software Foundation, Inc.
666 Copying and distribution of this file, with or without modification,
667 are permitted in any medium without royalty provided the copyright
668 notice and this notice are preserved.
674 version-control: never