1 2018-11-06 Alan Modra <amodra@gmail.com>
3 * ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls),
4 (insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0),
5 (insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16),
6 (insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd):
7 Don't return zero on error, insert mask bits instead.
8 (insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete.
9 (insert_sh6, extract_sh6): Delete dead code.
10 (insert_sprbat, insert_sprg): Use unsigned comparisions.
11 (powerpc_operands <OIMM>): Set shift count rather than using
13 <SE_SDH, SE_SDW>: Likewise. Don't use insert/extract functions.
15 2018-11-06 Jan Beulich <jbeulich@suse.com>
17 * i386-dis-evex.h (evex_table): Use K suffix instead of %LW for
18 vpbroadcast{d,q} with GPR operand.
20 2018-11-06 Jan Beulich <jbeulich@suse.com>
22 * i386-dis.c (EVEX_W_0F6E_P_2, EVEX_W_0F7E_P_2): Delete.
23 * i386-dis-evex.h (evex_table): Move vmov[dq} with GPR operand
24 cases up one level in the hierarchy.
26 2018-11-06 Jan Beulich <jbeulich@suse.com>
28 * i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0,
29 MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0.
30 (MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold
31 into MOD_VEX_0F93_P_3_LEN_0.
32 (vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR
33 operand cases up one level in the hierarchy.
35 2018-11-06 Jan Beulich <jbeulich@suse.com>
37 * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
38 VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
39 EVEX_W_0F3A22_P_2): Delete.
40 (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
41 entries up one level in the hierarchy.
42 (OP_E_memory): Handle dq_mode when determining Disp8 shift
44 * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
45 entries up one level in the hierarchy.
46 * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
47 VexWIG for AVX flavors.
48 * i386-tbl.h: Re-generate.
50 2018-11-06 Jan Beulich <jbeulich@suse.com>
52 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
53 vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
54 vcvtusi2ss, kmovd): Drop VexW=1.
55 * i386-tbl.h: Re-generate.
57 2018-11-06 Jan Beulich <jbeulich@suse.com>
59 * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
60 EVex512, EVexLIG, EVexDYN): New.
61 (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
62 insns): Use Vex128 instead of Vex=3 (aka VexLIG).
63 (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
64 of EVex=4 (aka EVexLIG).
65 * i386-tbl.h: Re-generate.
67 2018-11-06 Jan Beulich <jbeulich@suse.com>
69 * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
70 (vpmaxub): Re-order attributes on AVX512BW flavor.
71 * i386-tbl.h: Re-generate.
73 2018-11-06 Jan Beulich <jbeulich@suse.com>
75 * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
76 vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
77 Vex=1 on AVX / AVX2 flavors.
78 (vpmaxub): Re-order attributes on AVX512BW flavor.
79 * i386-tbl.h: Re-generate.
81 2018-11-06 Jan Beulich <jbeulich@suse.com>
83 * i386-opc.tbl (VexW0, VexW1): New.
84 (vphadd*, vphsub*): Use VexW0 on XOP variants.
85 * i386-tbl.h: Re-generate.
87 2018-10-22 John Darrington <john@darrington.wattle.id.au>
89 * s12z-dis.c (decode_possible_symbol): Add fallback case.
92 2018-10-19 Tamar Christina <tamar.christina@arm.com>
94 * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
95 (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
96 (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
98 2018-10-16 Matthew Malcomson <matthew.malcomson@arm.com>
100 * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
101 corresponding to AARCH64_OPND_QLF_S_4B qualifier.
103 2018-10-10 Jan Beulich <jbeulich@suse.com>
105 * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
107 * i386-opc.h (Size16, Size32, Size64): Delete.
109 (SIZE16, SIZE32, SIZE64): Define.
110 (struct i386_opcode_modifier): Drop size16, size32, and size64.
112 * i386-opc.tbl (Size16, Size32, Size64): Define.
113 * i386-tbl.h: Re-generate.
115 2018-10-09 Sudakshina Das <sudi.das@arm.com>
117 * aarch64-opc.c (operand_general_constraint_met_p): Add
118 SSBS in the check for one-bit immediate.
119 (aarch64_sys_regs): New entry for SSBS.
120 (aarch64_sys_reg_supported_p): New check for above.
121 (aarch64_pstatefields): New entry for SSBS.
122 (aarch64_pstatefield_supported_p): New check for above.
124 2018-10-09 Sudakshina Das <sudi.das@arm.com>
126 * aarch64-opc.c (aarch64_sys_regs): New entries for
127 scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
128 (aarch64_sys_reg_supported_p): New checks for above.
130 2018-10-09 Sudakshina Das <sudi.das@arm.com>
132 * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
133 (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
134 with the hint immediate.
135 * aarch64-opc.c (aarch64_hint_options): New entries for
136 c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
137 (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
138 while checking for HINT_OPD_F_NOPRINT flag.
139 * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
141 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
142 (aarch64_opcode_table): Add entry for BTI.
143 (AARCH64_OPERANDS): Add new description for BTI targets.
144 * aarch64-asm-2.c: Regenerate.
145 * aarch64-dis-2.c: Regenerate.
146 * aarch64-opc-2.c: Regenerate.
148 2018-10-09 Sudakshina Das <sudi.das@arm.com>
150 * aarch64-opc.c (aarch64_sys_regs): New entries for
152 (aarch64_sys_reg_supported_p): New check for above.
154 2018-10-09 Sudakshina Das <sudi.das@arm.com>
156 * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
157 (aarch64_sys_ins_reg_supported_p): New check for above.
159 2018-10-09 Sudakshina Das <sudi.das@arm.com>
161 * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
162 AARCH64_OPND_SYSREG_SR.
163 * aarch64-opc.c (aarch64_print_operand): Likewise.
164 (aarch64_sys_regs_sr): Define table.
165 (aarch64_sys_ins_reg_supported_p): Check for RCTX with
166 AARCH64_FEATURE_PREDRES.
167 * aarch64-tbl.h (aarch64_feature_predres): New.
168 (PREDRES, PREDRES_INSN): New.
169 (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
170 (AARCH64_OPERANDS): Add new description for SYSREG_SR.
171 * aarch64-asm-2.c: Regenerate.
172 * aarch64-dis-2.c: Regenerate.
173 * aarch64-opc-2.c: Regenerate.
175 2018-10-09 Sudakshina Das <sudi.das@arm.com>
177 * aarch64-tbl.h (aarch64_feature_sb): New.
179 (aarch64_opcode_table): Add entry for sb.
180 * aarch64-asm-2.c: Regenerate.
181 * aarch64-dis-2.c: Regenerate.
182 * aarch64-opc-2.c: Regenerate.
184 2018-10-09 Sudakshina Das <sudi.das@arm.com>
186 * aarch64-tbl.h (aarch64_feature_flagmanip): New.
187 (aarch64_feature_frintts): New.
188 (FLAGMANIP, FRINTTS): New.
189 (aarch64_opcode_table): Add entries for xaflag, axflag
190 and frint[32,64][x,z] instructions.
191 * aarch64-asm-2.c: Regenerate.
192 * aarch64-dis-2.c: Regenerate.
193 * aarch64-opc-2.c: Regenerate.
195 2018-10-09 Sudakshina Das <sudi.das@arm.com>
197 * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
198 (ARMV8_5, V8_5_INSN): New.
200 2018-10-08 Tamar Christina <tamar.christina@arm.com>
202 * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
204 2018-10-05 H.J. Lu <hongjiu.lu@intel.com>
206 * i386-dis.c (rm_table): Add enclv.
207 * i386-opc.tbl: Add enclv.
208 * i386-tbl.h: Regenerated.
210 2018-10-05 Sudakshina Das <sudi.das@arm.com>
212 * arm-dis.c (arm_opcodes): Add sb.
213 (thumb32_opcodes): Likewise.
215 2018-10-05 Richard Henderson <rth@twiddle.net>
216 Stafford Horne <shorne@gmail.com>
218 * or1k-desc.c: Regenerate.
219 * or1k-desc.h: Regenerate.
220 * or1k-opc.c: Regenerate.
221 * or1k-opc.h: Regenerate.
222 * or1k-opinst.c: Regenerate.
224 2018-10-05 Richard Henderson <rth@twiddle.net>
226 * or1k-asm.c: Regenerated.
227 * or1k-desc.c: Regenerated.
228 * or1k-desc.h: Regenerated.
229 * or1k-dis.c: Regenerated.
230 * or1k-ibld.c: Regenerated.
231 * or1k-opc.c: Regenerated.
232 * or1k-opc.h: Regenerated.
233 * or1k-opinst.c: Regenerated.
235 2018-10-05 Richard Henderson <rth@twiddle.net>
237 * or1k-asm.c: Regenerate.
239 2018-10-03 Tamar Christina <tamar.christina@arm.com>
241 * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
242 * aarch64-dis.c (print_operands): Refactor to take notes.
243 (print_verifier_notes): New.
244 (print_aarch64_insn): Apply constraint verifier.
245 (print_insn_aarch64_word): Update call to print_aarch64_insn.
246 * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
248 2018-10-03 Tamar Christina <tamar.christina@arm.com>
250 * aarch64-opc.c (init_insn_block): New.
251 (verify_constraints, aarch64_is_destructive_by_operands): New.
252 * aarch64-opc.h (verify_constraints): New.
254 2018-10-03 Tamar Christina <tamar.christina@arm.com>
256 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
257 * aarch64-opc.c (verify_ldpsw): Update arguments.
259 2018-10-03 Tamar Christina <tamar.christina@arm.com>
261 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
262 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
264 2018-10-03 Tamar Christina <tamar.christina@arm.com>
266 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
267 * aarch64-dis.c (insn_sequence): New.
269 2018-10-03 Tamar Christina <tamar.christina@arm.com>
271 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
272 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
273 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
274 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
277 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
279 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
281 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
282 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
283 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
284 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
285 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
286 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
287 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
289 2018-10-02 Palmer Dabbelt <palmer@sifive.com>
291 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
293 2018-09-23 Sandra Loosemore <sandra@codesourcery.com>
295 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
296 are used when extracting signed fields and converting them to
297 potentially 64-bit types.
299 2018-09-21 Simon Marchi <simon.marchi@ericsson.com>
301 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
302 * Makefile.in: Re-generate.
303 * aclocal.m4: Re-generate.
304 * configure: Re-generate.
305 * configure.ac: Remove check for -Wno-missing-field-initializers.
306 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
307 (csky_v2_opcodes): Likewise.
309 2018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
311 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
313 2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
315 * nds32-asm.c (operand_fields): Remove the unused fields.
316 (nds32_opcodes): Remove the unused instructions.
317 * nds32-dis.c (nds32_ex9_info): Removed.
318 (nds32_parse_opcode): Updated.
319 (print_insn_nds32): Likewise.
320 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
321 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
322 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
323 build_opcode_hash_table): New functions.
324 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
325 nds32_opcode_table): New.
326 (hw_ktabs): Declare it to a pointer rather than an array.
327 (build_hash_table): Removed.
328 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
329 SYN_ROPT and upadte HW_GPR and HW_INT.
330 * nds32-dis.c (keywords): Remove const.
331 (match_field): New function.
332 (nds32_parse_opcode): Updated.
333 * disassemble.c (disassemble_init_for_target):
334 Add disassemble_init_nds32.
335 * nds32-dis.c (eum map_type): New.
336 (nds32_private_data): Likewise.
337 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
338 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
339 (print_insn_nds32): Updated.
340 * nds32-asm.c (parse_aext_reg): Add new parameter.
341 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
344 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
345 (operand_fields): Add new fields.
346 (nds32_opcodes): Add new instructions.
347 (keyword_aridxi_mx): New keyword.
348 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
350 (ALU2_1, ALU2_2, ALU2_3): New macros.
351 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
353 2018-09-17 Kito Cheng <kito@andestech.com>
355 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
357 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
360 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
361 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
362 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
363 (EVEX_LEN_0F7E_P_1): Likewise.
364 (EVEX_LEN_0F7E_P_2): Likewise.
365 (EVEX_LEN_0FD6_P_2): Likewise.
366 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
367 (EVEX_LEN_TABLE): Likewise.
368 (EVEX_LEN_0F6E_P_2): New enum.
369 (EVEX_LEN_0F7E_P_1): Likewise.
370 (EVEX_LEN_0F7E_P_2): Likewise.
371 (EVEX_LEN_0FD6_P_2): Likewise.
372 (evex_len_table): New.
373 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
374 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
375 * i386-tbl.h: Regenerated.
377 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
380 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
381 VEX_LEN_0F7E_P_2 entries.
382 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
383 * i386-tbl.h: Regenerated.
385 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
387 * i386-dis.c (VZERO_Fixup): Removed.
389 (VEX_LEN_0F10_P_1): Likewise.
390 (VEX_LEN_0F10_P_3): Likewise.
391 (VEX_LEN_0F11_P_1): Likewise.
392 (VEX_LEN_0F11_P_3): Likewise.
393 (VEX_LEN_0F2E_P_0): Likewise.
394 (VEX_LEN_0F2E_P_2): Likewise.
395 (VEX_LEN_0F2F_P_0): Likewise.
396 (VEX_LEN_0F2F_P_2): Likewise.
397 (VEX_LEN_0F51_P_1): Likewise.
398 (VEX_LEN_0F51_P_3): Likewise.
399 (VEX_LEN_0F52_P_1): Likewise.
400 (VEX_LEN_0F53_P_1): Likewise.
401 (VEX_LEN_0F58_P_1): Likewise.
402 (VEX_LEN_0F58_P_3): Likewise.
403 (VEX_LEN_0F59_P_1): Likewise.
404 (VEX_LEN_0F59_P_3): Likewise.
405 (VEX_LEN_0F5A_P_1): Likewise.
406 (VEX_LEN_0F5A_P_3): Likewise.
407 (VEX_LEN_0F5C_P_1): Likewise.
408 (VEX_LEN_0F5C_P_3): Likewise.
409 (VEX_LEN_0F5D_P_1): Likewise.
410 (VEX_LEN_0F5D_P_3): Likewise.
411 (VEX_LEN_0F5E_P_1): Likewise.
412 (VEX_LEN_0F5E_P_3): Likewise.
413 (VEX_LEN_0F5F_P_1): Likewise.
414 (VEX_LEN_0F5F_P_3): Likewise.
415 (VEX_LEN_0FC2_P_1): Likewise.
416 (VEX_LEN_0FC2_P_3): Likewise.
417 (VEX_LEN_0F3A0A_P_2): Likewise.
418 (VEX_LEN_0F3A0B_P_2): Likewise.
419 (VEX_W_0F10_P_0): Likewise.
420 (VEX_W_0F10_P_1): Likewise.
421 (VEX_W_0F10_P_2): Likewise.
422 (VEX_W_0F10_P_3): Likewise.
423 (VEX_W_0F11_P_0): Likewise.
424 (VEX_W_0F11_P_1): Likewise.
425 (VEX_W_0F11_P_2): Likewise.
426 (VEX_W_0F11_P_3): Likewise.
427 (VEX_W_0F12_P_0_M_0): Likewise.
428 (VEX_W_0F12_P_0_M_1): Likewise.
429 (VEX_W_0F12_P_1): Likewise.
430 (VEX_W_0F12_P_2): Likewise.
431 (VEX_W_0F12_P_3): Likewise.
432 (VEX_W_0F13_M_0): Likewise.
433 (VEX_W_0F14): Likewise.
434 (VEX_W_0F15): Likewise.
435 (VEX_W_0F16_P_0_M_0): Likewise.
436 (VEX_W_0F16_P_0_M_1): Likewise.
437 (VEX_W_0F16_P_1): Likewise.
438 (VEX_W_0F16_P_2): Likewise.
439 (VEX_W_0F17_M_0): Likewise.
440 (VEX_W_0F28): Likewise.
441 (VEX_W_0F29): Likewise.
442 (VEX_W_0F2B_M_0): Likewise.
443 (VEX_W_0F2E_P_0): Likewise.
444 (VEX_W_0F2E_P_2): Likewise.
445 (VEX_W_0F2F_P_0): Likewise.
446 (VEX_W_0F2F_P_2): Likewise.
447 (VEX_W_0F50_M_0): Likewise.
448 (VEX_W_0F51_P_0): Likewise.
449 (VEX_W_0F51_P_1): Likewise.
450 (VEX_W_0F51_P_2): Likewise.
451 (VEX_W_0F51_P_3): Likewise.
452 (VEX_W_0F52_P_0): Likewise.
453 (VEX_W_0F52_P_1): Likewise.
454 (VEX_W_0F53_P_0): Likewise.
455 (VEX_W_0F53_P_1): Likewise.
456 (VEX_W_0F58_P_0): Likewise.
457 (VEX_W_0F58_P_1): Likewise.
458 (VEX_W_0F58_P_2): Likewise.
459 (VEX_W_0F58_P_3): Likewise.
460 (VEX_W_0F59_P_0): Likewise.
461 (VEX_W_0F59_P_1): Likewise.
462 (VEX_W_0F59_P_2): Likewise.
463 (VEX_W_0F59_P_3): Likewise.
464 (VEX_W_0F5A_P_0): Likewise.
465 (VEX_W_0F5A_P_1): Likewise.
466 (VEX_W_0F5A_P_3): Likewise.
467 (VEX_W_0F5B_P_0): Likewise.
468 (VEX_W_0F5B_P_1): Likewise.
469 (VEX_W_0F5B_P_2): Likewise.
470 (VEX_W_0F5C_P_0): Likewise.
471 (VEX_W_0F5C_P_1): Likewise.
472 (VEX_W_0F5C_P_2): Likewise.
473 (VEX_W_0F5C_P_3): Likewise.
474 (VEX_W_0F5D_P_0): Likewise.
475 (VEX_W_0F5D_P_1): Likewise.
476 (VEX_W_0F5D_P_2): Likewise.
477 (VEX_W_0F5D_P_3): Likewise.
478 (VEX_W_0F5E_P_0): Likewise.
479 (VEX_W_0F5E_P_1): Likewise.
480 (VEX_W_0F5E_P_2): Likewise.
481 (VEX_W_0F5E_P_3): Likewise.
482 (VEX_W_0F5F_P_0): Likewise.
483 (VEX_W_0F5F_P_1): Likewise.
484 (VEX_W_0F5F_P_2): Likewise.
485 (VEX_W_0F5F_P_3): Likewise.
486 (VEX_W_0F60_P_2): Likewise.
487 (VEX_W_0F61_P_2): Likewise.
488 (VEX_W_0F62_P_2): Likewise.
489 (VEX_W_0F63_P_2): Likewise.
490 (VEX_W_0F64_P_2): Likewise.
491 (VEX_W_0F65_P_2): Likewise.
492 (VEX_W_0F66_P_2): Likewise.
493 (VEX_W_0F67_P_2): Likewise.
494 (VEX_W_0F68_P_2): Likewise.
495 (VEX_W_0F69_P_2): Likewise.
496 (VEX_W_0F6A_P_2): Likewise.
497 (VEX_W_0F6B_P_2): Likewise.
498 (VEX_W_0F6C_P_2): Likewise.
499 (VEX_W_0F6D_P_2): Likewise.
500 (VEX_W_0F6F_P_1): Likewise.
501 (VEX_W_0F6F_P_2): Likewise.
502 (VEX_W_0F70_P_1): Likewise.
503 (VEX_W_0F70_P_2): Likewise.
504 (VEX_W_0F70_P_3): Likewise.
505 (VEX_W_0F71_R_2_P_2): Likewise.
506 (VEX_W_0F71_R_4_P_2): Likewise.
507 (VEX_W_0F71_R_6_P_2): Likewise.
508 (VEX_W_0F72_R_2_P_2): Likewise.
509 (VEX_W_0F72_R_4_P_2): Likewise.
510 (VEX_W_0F72_R_6_P_2): Likewise.
511 (VEX_W_0F73_R_2_P_2): Likewise.
512 (VEX_W_0F73_R_3_P_2): Likewise.
513 (VEX_W_0F73_R_6_P_2): Likewise.
514 (VEX_W_0F73_R_7_P_2): Likewise.
515 (VEX_W_0F74_P_2): Likewise.
516 (VEX_W_0F75_P_2): Likewise.
517 (VEX_W_0F76_P_2): Likewise.
518 (VEX_W_0F77_P_0): Likewise.
519 (VEX_W_0F7C_P_2): Likewise.
520 (VEX_W_0F7C_P_3): Likewise.
521 (VEX_W_0F7D_P_2): Likewise.
522 (VEX_W_0F7D_P_3): Likewise.
523 (VEX_W_0F7E_P_1): Likewise.
524 (VEX_W_0F7F_P_1): Likewise.
525 (VEX_W_0F7F_P_2): Likewise.
526 (VEX_W_0FAE_R_2_M_0): Likewise.
527 (VEX_W_0FAE_R_3_M_0): Likewise.
528 (VEX_W_0FC2_P_0): Likewise.
529 (VEX_W_0FC2_P_1): Likewise.
530 (VEX_W_0FC2_P_2): Likewise.
531 (VEX_W_0FC2_P_3): Likewise.
532 (VEX_W_0FD0_P_2): Likewise.
533 (VEX_W_0FD0_P_3): Likewise.
534 (VEX_W_0FD1_P_2): Likewise.
535 (VEX_W_0FD2_P_2): Likewise.
536 (VEX_W_0FD3_P_2): Likewise.
537 (VEX_W_0FD4_P_2): Likewise.
538 (VEX_W_0FD5_P_2): Likewise.
539 (VEX_W_0FD6_P_2): Likewise.
540 (VEX_W_0FD7_P_2_M_1): Likewise.
541 (VEX_W_0FD8_P_2): Likewise.
542 (VEX_W_0FD9_P_2): Likewise.
543 (VEX_W_0FDA_P_2): Likewise.
544 (VEX_W_0FDB_P_2): Likewise.
545 (VEX_W_0FDC_P_2): Likewise.
546 (VEX_W_0FDD_P_2): Likewise.
547 (VEX_W_0FDE_P_2): Likewise.
548 (VEX_W_0FDF_P_2): Likewise.
549 (VEX_W_0FE0_P_2): Likewise.
550 (VEX_W_0FE1_P_2): Likewise.
551 (VEX_W_0FE2_P_2): Likewise.
552 (VEX_W_0FE3_P_2): Likewise.
553 (VEX_W_0FE4_P_2): Likewise.
554 (VEX_W_0FE5_P_2): Likewise.
555 (VEX_W_0FE6_P_1): Likewise.
556 (VEX_W_0FE6_P_2): Likewise.
557 (VEX_W_0FE6_P_3): Likewise.
558 (VEX_W_0FE7_P_2_M_0): Likewise.
559 (VEX_W_0FE8_P_2): Likewise.
560 (VEX_W_0FE9_P_2): Likewise.
561 (VEX_W_0FEA_P_2): Likewise.
562 (VEX_W_0FEB_P_2): Likewise.
563 (VEX_W_0FEC_P_2): Likewise.
564 (VEX_W_0FED_P_2): Likewise.
565 (VEX_W_0FEE_P_2): Likewise.
566 (VEX_W_0FEF_P_2): Likewise.
567 (VEX_W_0FF0_P_3_M_0): Likewise.
568 (VEX_W_0FF1_P_2): Likewise.
569 (VEX_W_0FF2_P_2): Likewise.
570 (VEX_W_0FF3_P_2): Likewise.
571 (VEX_W_0FF4_P_2): Likewise.
572 (VEX_W_0FF5_P_2): Likewise.
573 (VEX_W_0FF6_P_2): Likewise.
574 (VEX_W_0FF7_P_2): Likewise.
575 (VEX_W_0FF8_P_2): Likewise.
576 (VEX_W_0FF9_P_2): Likewise.
577 (VEX_W_0FFA_P_2): Likewise.
578 (VEX_W_0FFB_P_2): Likewise.
579 (VEX_W_0FFC_P_2): Likewise.
580 (VEX_W_0FFD_P_2): Likewise.
581 (VEX_W_0FFE_P_2): Likewise.
582 (VEX_W_0F3800_P_2): Likewise.
583 (VEX_W_0F3801_P_2): Likewise.
584 (VEX_W_0F3802_P_2): Likewise.
585 (VEX_W_0F3803_P_2): Likewise.
586 (VEX_W_0F3804_P_2): Likewise.
587 (VEX_W_0F3805_P_2): Likewise.
588 (VEX_W_0F3806_P_2): Likewise.
589 (VEX_W_0F3807_P_2): Likewise.
590 (VEX_W_0F3808_P_2): Likewise.
591 (VEX_W_0F3809_P_2): Likewise.
592 (VEX_W_0F380A_P_2): Likewise.
593 (VEX_W_0F380B_P_2): Likewise.
594 (VEX_W_0F3817_P_2): Likewise.
595 (VEX_W_0F381C_P_2): Likewise.
596 (VEX_W_0F381D_P_2): Likewise.
597 (VEX_W_0F381E_P_2): Likewise.
598 (VEX_W_0F3820_P_2): Likewise.
599 (VEX_W_0F3821_P_2): Likewise.
600 (VEX_W_0F3822_P_2): Likewise.
601 (VEX_W_0F3823_P_2): Likewise.
602 (VEX_W_0F3824_P_2): Likewise.
603 (VEX_W_0F3825_P_2): Likewise.
604 (VEX_W_0F3828_P_2): Likewise.
605 (VEX_W_0F3829_P_2): Likewise.
606 (VEX_W_0F382A_P_2_M_0): Likewise.
607 (VEX_W_0F382B_P_2): Likewise.
608 (VEX_W_0F3830_P_2): Likewise.
609 (VEX_W_0F3831_P_2): Likewise.
610 (VEX_W_0F3832_P_2): Likewise.
611 (VEX_W_0F3833_P_2): Likewise.
612 (VEX_W_0F3834_P_2): Likewise.
613 (VEX_W_0F3835_P_2): Likewise.
614 (VEX_W_0F3837_P_2): Likewise.
615 (VEX_W_0F3838_P_2): Likewise.
616 (VEX_W_0F3839_P_2): Likewise.
617 (VEX_W_0F383A_P_2): Likewise.
618 (VEX_W_0F383B_P_2): Likewise.
619 (VEX_W_0F383C_P_2): Likewise.
620 (VEX_W_0F383D_P_2): Likewise.
621 (VEX_W_0F383E_P_2): Likewise.
622 (VEX_W_0F383F_P_2): Likewise.
623 (VEX_W_0F3840_P_2): Likewise.
624 (VEX_W_0F3841_P_2): Likewise.
625 (VEX_W_0F38DB_P_2): Likewise.
626 (VEX_W_0F3A08_P_2): Likewise.
627 (VEX_W_0F3A09_P_2): Likewise.
628 (VEX_W_0F3A0A_P_2): Likewise.
629 (VEX_W_0F3A0B_P_2): Likewise.
630 (VEX_W_0F3A0C_P_2): Likewise.
631 (VEX_W_0F3A0D_P_2): Likewise.
632 (VEX_W_0F3A0E_P_2): Likewise.
633 (VEX_W_0F3A0F_P_2): Likewise.
634 (VEX_W_0F3A21_P_2): Likewise.
635 (VEX_W_0F3A40_P_2): Likewise.
636 (VEX_W_0F3A41_P_2): Likewise.
637 (VEX_W_0F3A42_P_2): Likewise.
638 (VEX_W_0F3A62_P_2): Likewise.
639 (VEX_W_0F3A63_P_2): Likewise.
640 (VEX_W_0F3ADF_P_2): Likewise.
641 (VEX_LEN_0F77_P_0): New.
642 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
643 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
644 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
645 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
646 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
647 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
648 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
649 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
650 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
651 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
652 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
653 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
654 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
655 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
656 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
657 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
658 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
659 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
660 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
661 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
662 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
663 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
664 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
665 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
666 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
667 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
668 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
669 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
670 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
671 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
672 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
673 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
674 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
675 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
676 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
677 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
678 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
679 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
680 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
681 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
682 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
683 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
684 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
685 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
686 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
687 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
688 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
689 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
690 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
691 (vex_table): Update VEX 0F28 and 0F29 entries.
692 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
693 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
694 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
695 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
696 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
697 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
698 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
699 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
700 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
701 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
702 VEX_LEN_0F3A0B_P_2 entries.
703 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
704 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
705 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
706 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
707 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
708 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
709 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
710 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
711 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
712 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
713 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
714 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
715 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
716 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
717 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
718 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
719 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
720 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
721 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
722 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
723 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
724 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
725 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
726 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
727 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
728 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
729 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
730 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
731 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
732 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
733 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
734 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
735 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
736 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
737 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
738 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
739 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
740 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
741 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
742 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
743 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
744 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
745 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
746 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
747 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
748 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
749 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
750 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
751 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
752 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
753 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
754 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
755 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
756 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
757 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
758 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
759 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
760 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
761 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
762 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
763 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
764 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
765 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
766 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
767 VEX_W_0F3ADF_P_2 entries.
768 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
769 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
770 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
772 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
774 * i386-opc.tbl (VexWIG): New.
775 Replace VexW=3 with VexWIG.
777 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
779 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
780 * i386-tbl.h: Regenerated.
782 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
785 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
786 VEX_LEN_0FD6_P_2 entries.
787 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
788 * i386-tbl.h: Regenerated.
790 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
793 * i386-opc.h (VEXWIG): New.
794 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
795 * i386-tbl.h: Regenerated.
797 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
800 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
801 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
802 * i386-dis.c (EXxEVexR64): New.
803 (evex_rounding_64_mode): Likewise.
804 (OP_Rounding): Handle evex_rounding_64_mode.
806 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
809 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
810 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
811 * i386-dis.c (Edqa): New.
812 (dqa_mode): Likewise.
813 (intel_operand_size): Handle dqa_mode as m_mode.
814 (OP_E_register): Handle dqa_mode as dq_mode.
815 (OP_E_memory): Set shift for dqa_mode based on address_mode.
817 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
819 * i386-dis.c (OP_E_memory): Reformat.
821 2018-09-14 Jan Beulich <jbeulich@suse.com>
823 * i386-opc.tbl (crc32): Fold byte and word forms.
824 * i386-tbl.h: Re-generate.
826 2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
828 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
829 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
830 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
831 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
832 * i386-tbl.h: Regenerated.
834 2018-09-13 Jan Beulich <jbeulich@suse.com>
836 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
838 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
839 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
840 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
841 * i386-tbl.h: Re-generate.
843 2018-09-13 Jan Beulich <jbeulich@suse.com>
845 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
847 * i386-tbl.h: Re-generate.
849 2018-09-13 Jan Beulich <jbeulich@suse.com>
851 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
853 * i386-tbl.h: Re-generate.
855 2018-09-13 Jan Beulich <jbeulich@suse.com>
857 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
859 * i386-tbl.h: Re-generate.
861 2018-09-13 Jan Beulich <jbeulich@suse.com>
863 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
865 * i386-tbl.h: Re-generate.
867 2018-09-13 Jan Beulich <jbeulich@suse.com>
869 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
871 * i386-tbl.h: Re-generate.
873 2018-09-13 Jan Beulich <jbeulich@suse.com>
875 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
877 * i386-tbl.h: Re-generate.
879 2018-09-13 Jan Beulich <jbeulich@suse.com>
881 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
882 * i386-tbl.h: Re-generate.
884 2018-09-13 Jan Beulich <jbeulich@suse.com>
886 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
887 * i386-tbl.h: Re-generate.
889 2018-09-13 Jan Beulich <jbeulich@suse.com>
891 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
893 * i386-tbl.h: Re-generate.
895 2018-09-13 Jan Beulich <jbeulich@suse.com>
897 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
899 * i386-tbl.h: Re-generate.
901 2018-09-13 Jan Beulich <jbeulich@suse.com>
903 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
904 * i386-tbl.h: Re-generate.
906 2018-09-13 Jan Beulich <jbeulich@suse.com>
908 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
909 * i386-tbl.h: Re-generate.
911 2018-09-13 Jan Beulich <jbeulich@suse.com>
913 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
914 * i386-tbl.h: Re-generate.
916 2018-09-13 Jan Beulich <jbeulich@suse.com>
918 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
920 * i386-tbl.h: Re-generate.
922 2018-09-13 Jan Beulich <jbeulich@suse.com>
924 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
926 * i386-tbl.h: Re-generate.
928 2018-09-13 Jan Beulich <jbeulich@suse.com>
930 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
932 * i386-tbl.h: Re-generate.
934 2018-09-13 Jan Beulich <jbeulich@suse.com>
936 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
937 * i386-tbl.h: Re-generate.
939 2018-09-13 Jan Beulich <jbeulich@suse.com>
941 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
942 * i386-tbl.h: Re-generate.
944 2018-09-13 Jan Beulich <jbeulich@suse.com>
946 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
947 * i386-tbl.h: Re-generate.
949 2018-09-13 Jan Beulich <jbeulich@suse.com>
951 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
952 (vpbroadcastw, rdpid): Drop NoRex64.
953 * i386-tbl.h: Re-generate.
955 2018-09-13 Jan Beulich <jbeulich@suse.com>
957 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
958 store templates, adding D.
959 * i386-tbl.h: Re-generate.
961 2018-09-13 Jan Beulich <jbeulich@suse.com>
963 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
964 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
965 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
966 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
967 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
968 Fold load and store templates where possible, adding D. Drop
969 IgnoreSize where it was pointlessly present. Drop redundant
971 * i386-tbl.h: Re-generate.
973 2018-09-13 Jan Beulich <jbeulich@suse.com>
975 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
976 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
977 (intel_operand_size): Handle v_bndmk_mode.
978 (OP_E_memory): Likewise. Produce (bad) when also riprel.
980 2018-09-08 John Darrington <john@darrington.wattle.id.au>
982 * disassemble.c (ARCH_s12z): Define if ARCH_all.
984 2018-08-31 Kito Cheng <kito@andestech.com>
986 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
987 compressed floating point instructions.
989 2018-08-30 Kito Cheng <kito@andestech.com>
991 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
992 riscv_opcode.xlen_requirement.
993 * riscv-opc.c (riscv_opcodes): Update for struct change.
995 2018-08-29 Martin Aberg <maberg@gaisler.com>
997 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
998 psr (PWRPSR) instruction.
1000 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1002 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
1004 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1006 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
1008 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1010 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
1011 loongson3a as an alias of gs464 for compatibility.
1012 * mips-opc.c (mips_opcodes): Change Comments.
1014 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1016 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
1018 (print_mips_disassembler_options): Document -M loongson-ext.
1019 * mips-opc.c (LEXT2): New macro.
1020 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
1022 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1024 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
1026 (parse_mips_ase_option): Handle -M loongson-ext option.
1027 (print_mips_disassembler_options): Document -M loongson-ext.
1028 * mips-opc.c (IL3A): Delete.
1029 * mips-opc.c (LEXT): New macro.
1030 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
1033 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1035 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
1037 (parse_mips_ase_option): Handle -M loongson-cam option.
1038 (print_mips_disassembler_options): Document -M loongson-cam.
1039 * mips-opc.c (LCAM): New macro.
1040 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
1043 2018-08-21 Alan Modra <amodra@gmail.com>
1045 * ppc-dis.c (operand_value_powerpc): Init "invalid".
1046 (skip_optional_operands): Count optional operands, and update
1047 ppc_optional_operand_value call.
1048 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
1049 (extract_vlensi): Likewise.
1050 (extract_fxm): Return default value for missing optional operand.
1051 (extract_ls, extract_raq, extract_tbr): Likewise.
1052 (insert_sxl, extract_sxl): New functions.
1053 (insert_esync, extract_esync): Remove Power9 handling and simplify.
1054 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
1055 flag and extra entry.
1056 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
1059 2018-08-20 Alan Modra <amodra@gmail.com>
1061 * sh-opc.h (MASK): Simplify.
1063 2018-08-18 John Darrington <john@darrington.wattle.id.au>
1065 * s12z-dis.c (bm_decode): Deal with cases where the mode is
1066 BM_RESERVED0 or BM_RESERVED1
1067 (bm_rel_decode, bm_n_bytes): Ditto.
1069 2018-08-18 John Darrington <john@darrington.wattle.id.au>
1073 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
1075 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1076 address with the addr32 prefix and without base nor index
1079 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
1081 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1082 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1083 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1084 (cpu_flags): Add CpuCMOV and CpuFXSR.
1085 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1086 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
1087 * i386-init.h: Regenerated.
1088 * i386-tbl.h: Likewise.
1090 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
1092 * arc-regs.h: Update auxiliary registers.
1094 2018-08-06 Jan Beulich <jbeulich@suse.com>
1096 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1097 (RegIP, RegIZ): Define.
1098 * i386-reg.tbl: Adjust comments.
1099 (rip): Use Qword instead of BaseIndex. Use RegIP.
1100 (eip): Use Dword instead of BaseIndex. Use RegIP.
1101 (riz): Add Qword. Use RegIZ.
1102 (eiz): Add Dword. Use RegIZ.
1103 * i386-tbl.h: Re-generate.
1105 2018-08-03 Jan Beulich <jbeulich@suse.com>
1107 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1108 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1109 vpmovzxdq, vpmovzxwd): Remove NoRex64.
1110 * i386-tbl.h: Re-generate.
1112 2018-08-03 Jan Beulich <jbeulich@suse.com>
1114 * i386-gen.c (operand_types): Remove Mem field.
1115 * i386-opc.h (union i386_operand_type): Remove mem field.
1116 * i386-init.h, i386-tbl.h: Re-generate.
1118 2018-08-01 Alan Modra <amodra@gmail.com>
1120 * po/POTFILES.in: Regenerate.
1122 2018-07-31 Nick Clifton <nickc@redhat.com>
1124 * po/sv.po: Updated Swedish translation.
1126 2018-07-31 Jan Beulich <jbeulich@suse.com>
1128 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1129 * i386-init.h, i386-tbl.h: Re-generate.
1131 2018-07-31 Jan Beulich <jbeulich@suse.com>
1133 * i386-opc.h (ZEROING_MASKING) Rename to ...
1134 (DYNAMIC_MASKING): ... this. Adjust comment.
1135 * i386-opc.tbl (MaskingMorZ): Define.
1136 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1137 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1138 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1139 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1140 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1141 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1142 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1143 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1144 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1146 2018-07-31 Jan Beulich <jbeulich@suse.com>
1148 * i386-opc.tbl: Use element rather than vector size for AVX512*
1149 scatter/gather insns.
1150 * i386-tbl.h: Re-generate.
1152 2018-07-31 Jan Beulich <jbeulich@suse.com>
1154 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1155 (cpu_flags): Drop CpuVREX.
1156 * i386-opc.h (CpuVREX): Delete.
1157 (union i386_cpu_flags): Remove cpuvrex.
1158 * i386-init.h, i386-tbl.h: Re-generate.
1160 2018-07-30 Jim Wilson <jimw@sifive.com>
1162 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1164 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1166 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
1168 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1169 * Makefile.in: Regenerated.
1170 * configure.ac: Add C-SKY.
1171 * configure: Regenerated.
1172 * csky-dis.c: New file.
1173 * csky-opc.h: New file.
1174 * disassemble.c (ARCH_csky): Define.
1175 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1176 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1178 2018-07-27 Alan Modra <amodra@gmail.com>
1180 * ppc-opc.c (insert_sprbat): Correct function parameter and
1182 (extract_sprbat): Likewise, variable too.
1184 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
1185 Alan Modra <amodra@gmail.com>
1187 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1188 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1189 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1190 support disjointed BAT.
1191 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
1192 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1193 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1195 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
1196 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1198 * i386-gen.c (adjust_broadcast_modifier): New function.
1199 (process_i386_opcode_modifier): Add an argument for operands.
1200 Adjust the Broadcast value based on operands.
1201 (output_i386_opcode): Pass operand_types to
1202 process_i386_opcode_modifier.
1203 (process_i386_opcodes): Pass NULL as operands to
1204 process_i386_opcode_modifier.
1205 * i386-opc.h (BYTE_BROADCAST): New.
1206 (WORD_BROADCAST): Likewise.
1207 (DWORD_BROADCAST): Likewise.
1208 (QWORD_BROADCAST): Likewise.
1209 (i386_opcode_modifier): Expand broadcast to 3 bits.
1210 * i386-tbl.h: Regenerated.
1212 2018-07-24 Alan Modra <amodra@gmail.com>
1215 * or1k-desc.h: Regenerate.
1217 2018-07-24 Jan Beulich <jbeulich@suse.com>
1219 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1220 vcvtusi2ss, and vcvtusi2sd.
1221 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1222 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1223 * i386-tbl.h: Re-generate.
1225 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1227 * arc-opc.c (extract_w6): Fix extending the sign.
1229 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1231 * arc-tbl.h (vewt): Allow it for ARC EM family.
1233 2018-07-23 Alan Modra <amodra@gmail.com>
1236 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1237 opcode variants for mtspr/mfspr encodings.
1239 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
1240 Maciej W. Rozycki <macro@mips.com>
1242 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1243 loongson3a descriptors.
1244 (parse_mips_ase_option): Handle -M loongson-mmi option.
1245 (print_mips_disassembler_options): Document -M loongson-mmi.
1246 * mips-opc.c (LMMI): New macro.
1247 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1250 2018-07-19 Jan Beulich <jbeulich@suse.com>
1252 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1253 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1254 IgnoreSize and [XYZ]MMword where applicable.
1255 * i386-tbl.h: Re-generate.
1257 2018-07-19 Jan Beulich <jbeulich@suse.com>
1259 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1260 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1261 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1262 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1263 * i386-tbl.h: Re-generate.
1265 2018-07-19 Jan Beulich <jbeulich@suse.com>
1267 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1268 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1269 VPCLMULQDQ templates into their respective AVX512VL counterparts
1270 where possible, using Disp8ShiftVL and CheckRegSize instead of
1271 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1272 * i386-tbl.h: Re-generate.
1274 2018-07-19 Jan Beulich <jbeulich@suse.com>
1276 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1277 AVX512VL counterparts where possible, using Disp8ShiftVL and
1278 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1279 IgnoreSize) as appropriate.
1280 * i386-tbl.h: Re-generate.
1282 2018-07-19 Jan Beulich <jbeulich@suse.com>
1284 * i386-opc.tbl: Fold AVX512BW templates into their respective
1285 AVX512VL counterparts where possible, using Disp8ShiftVL and
1286 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1287 IgnoreSize) as appropriate.
1288 * i386-tbl.h: Re-generate.
1290 2018-07-19 Jan Beulich <jbeulich@suse.com>
1292 * i386-opc.tbl: Fold AVX512CD templates into their respective
1293 AVX512VL counterparts where possible, using Disp8ShiftVL and
1294 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1295 IgnoreSize) as appropriate.
1296 * i386-tbl.h: Re-generate.
1298 2018-07-19 Jan Beulich <jbeulich@suse.com>
1300 * i386-opc.h (DISP8_SHIFT_VL): New.
1301 * i386-opc.tbl (Disp8ShiftVL): Define.
1302 (various): Fold AVX512VL templates into their respective
1303 AVX512F counterparts where possible, using Disp8ShiftVL and
1304 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1305 IgnoreSize) as appropriate.
1306 * i386-tbl.h: Re-generate.
1308 2018-07-19 Jan Beulich <jbeulich@suse.com>
1310 * Makefile.am: Change dependencies and rule for
1311 $(srcdir)/i386-init.h.
1312 * Makefile.in: Re-generate.
1313 * i386-gen.c (process_i386_opcodes): New local variable
1314 "marker". Drop opening of input file. Recognize marker and line
1316 * i386-opc.tbl (OPCODE_I386_H): Define.
1317 (i386-opc.h): Include it.
1320 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1323 * i386-opc.h (Byte): Update comments.
1329 (Xmmword): Likewise.
1330 (Ymmword): Likewise.
1331 (Zmmword): Likewise.
1332 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1334 * i386-tbl.h: Regenerated.
1336 2018-07-12 Sudakshina Das <sudi.das@arm.com>
1338 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1339 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1340 * aarch64-asm-2.c: Regenerate.
1341 * aarch64-dis-2.c: Regenerate.
1342 * aarch64-opc-2.c: Regenerate.
1344 2018-07-12 Tamar Christina <tamar.christina@arm.com>
1347 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1348 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1349 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1350 sqdmulh, sqrdmulh): Use Em16.
1352 2018-07-11 Sudakshina Das <sudi.das@arm.com>
1354 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1355 csdb together with them.
1356 (thumb32_opcodes): Likewise.
1358 2018-07-11 Jan Beulich <jbeulich@suse.com>
1360 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1361 requiring 32-bit registers as operands 2 and 3. Improve
1363 (mwait, mwaitx): Fold templates. Improve comments.
1364 OPERAND_TYPE_INOUTPORTREG.
1365 * i386-tbl.h: Re-generate.
1367 2018-07-11 Jan Beulich <jbeulich@suse.com>
1369 * i386-gen.c (operand_type_init): Remove
1370 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1371 OPERAND_TYPE_INOUTPORTREG.
1372 * i386-init.h: Re-generate.
1374 2018-07-11 Jan Beulich <jbeulich@suse.com>
1376 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1377 (wrssq, wrussq): Add Qword.
1378 * i386-tbl.h: Re-generate.
1380 2018-07-11 Jan Beulich <jbeulich@suse.com>
1382 * i386-opc.h: Rename OTMax to OTNum.
1383 (OTNumOfUints): Adjust calculation.
1384 (OTUnused): Directly alias to OTNum.
1386 2018-07-09 Maciej W. Rozycki <macro@mips.com>
1388 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1390 (lea_reg_xys): Likewise.
1391 (print_insn_loop_primitive): Rename `reg' local variable to
1394 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1397 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1399 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1402 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1403 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1405 2018-07-02 Maciej W. Rozycki <macro@mips.com>
1408 * mips-dis.c (mips_option_arg_t): New enumeration.
1409 (mips_options): New variable.
1410 (disassembler_options_mips): New function.
1411 (print_mips_disassembler_options): Reimplement in terms of
1412 `disassembler_options_mips'.
1413 * arm-dis.c (disassembler_options_arm): Adapt to using the
1414 `disasm_options_and_args_t' structure.
1415 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1416 * s390-dis.c (disassembler_options_s390): Likewise.
1418 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1420 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1422 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1423 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1424 * testsuite/ld-arm/tls-longplt.d: Likewise.
1426 2018-06-29 Tamar Christina <tamar.christina@arm.com>
1429 * aarch64-asm-2.c: Regenerate.
1430 * aarch64-dis-2.c: Likewise.
1431 * aarch64-opc-2.c: Likewise.
1432 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1433 * aarch64-opc.c (operand_general_constraint_met_p,
1434 aarch64_print_operand): Likewise.
1435 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1436 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1438 (AARCH64_OPERANDS): Add Em2.
1440 2018-06-26 Nick Clifton <nickc@redhat.com>
1442 * po/uk.po: Updated Ukranian translation.
1443 * po/de.po: Updated German translation.
1444 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1446 2018-06-26 Nick Clifton <nickc@redhat.com>
1448 * nfp-dis.c: Fix spelling mistake.
1450 2018-06-24 Nick Clifton <nickc@redhat.com>
1452 * configure: Regenerate.
1453 * po/opcodes.pot: Regenerate.
1455 2018-06-24 Nick Clifton <nickc@redhat.com>
1457 2.31 branch created.
1459 2018-06-19 Tamar Christina <tamar.christina@arm.com>
1461 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1462 * aarch64-asm-2.c: Regenerate.
1463 * aarch64-dis-2.c: Likewise.
1465 2018-06-21 Maciej W. Rozycki <macro@mips.com>
1467 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1468 `-M ginv' option description.
1470 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1473 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1476 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1478 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1479 * configure.ac: Remove AC_PREREQ.
1480 * Makefile.in: Re-generate.
1481 * aclocal.m4: Re-generate.
1482 * configure: Re-generate.
1484 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1486 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1487 mips64r6 descriptors.
1488 (parse_mips_ase_option): Handle -Mginv option.
1489 (print_mips_disassembler_options): Document -Mginv.
1490 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1492 (mips_opcodes): Define ginvi and ginvt.
1494 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1495 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1497 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1498 * mips-opc.c (CRC, CRC64): New macros.
1499 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1500 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1503 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1506 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1507 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1509 2018-06-06 Alan Modra <amodra@gmail.com>
1511 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1512 setjmp. Move init for some other vars later too.
1514 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1516 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1517 (dis_private): Add new fields for property section tracking.
1518 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1519 (xtensa_instruction_fits): New functions.
1520 (fetch_data): Bump minimal fetch size to 4.
1521 (print_insn_xtensa): Make struct dis_private static.
1522 Load and prepare property table on section change.
1523 Don't disassemble literals. Don't disassemble instructions that
1524 cross property table boundaries.
1526 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1528 * configure: Regenerated.
1530 2018-06-01 Jan Beulich <jbeulich@suse.com>
1532 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1533 * i386-tbl.h: Re-generate.
1535 2018-06-01 Jan Beulich <jbeulich@suse.com>
1537 * i386-opc.tbl (sldt, str): Add NoRex64.
1538 * i386-tbl.h: Re-generate.
1540 2018-06-01 Jan Beulich <jbeulich@suse.com>
1542 * i386-opc.tbl (invpcid): Add Oword.
1543 * i386-tbl.h: Re-generate.
1545 2018-06-01 Alan Modra <amodra@gmail.com>
1547 * sysdep.h (_bfd_error_handler): Don't declare.
1548 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1549 * rl78-decode.opc: Likewise.
1550 * msp430-decode.c: Regenerate.
1551 * rl78-decode.c: Regenerate.
1553 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1555 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1556 * i386-init.h : Regenerated.
1558 2018-05-25 Alan Modra <amodra@gmail.com>
1560 * Makefile.in: Regenerate.
1561 * po/POTFILES.in: Regenerate.
1563 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1565 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1566 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1567 (insert_bab, extract_bab, insert_btab, extract_btab,
1568 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1569 (BAT, BBA VBA RBS XB6S): Delete macros.
1570 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1571 (BB, BD, RBX, XC6): Update for new macros.
1572 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1573 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1574 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1575 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1577 2018-05-18 John Darrington <john@darrington.wattle.id.au>
1579 * Makefile.am: Add support for s12z architecture.
1580 * configure.ac: Likewise.
1581 * disassemble.c: Likewise.
1582 * disassemble.h: Likewise.
1583 * Makefile.in: Regenerate.
1584 * configure: Regenerate.
1585 * s12z-dis.c: New file.
1588 2018-05-18 Alan Modra <amodra@gmail.com>
1590 * nfp-dis.c: Don't #include libbfd.h.
1591 (init_nfp3200_priv): Use bfd_get_section_contents.
1592 (nit_nfp6000_mecsr_sec): Likewise.
1594 2018-05-17 Nick Clifton <nickc@redhat.com>
1596 * po/zh_CN.po: Updated simplified Chinese translation.
1598 2018-05-16 Tamar Christina <tamar.christina@arm.com>
1601 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1602 * aarch64-dis-2.c: Regenerate.
1604 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1607 * aarch64-asm.c (opintl.h): Include.
1608 (aarch64_ins_sysreg): Enforce read/write constraints.
1609 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1610 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1611 (F_REG_READ, F_REG_WRITE): New.
1612 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1613 AARCH64_OPND_SYSREG.
1614 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1615 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1616 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1617 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1618 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1619 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1620 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1621 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1622 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1623 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1624 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1625 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1626 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1627 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1628 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1629 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1630 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1632 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1635 * aarch64-dis.c (no_notes: New.
1636 (parse_aarch64_dis_option): Support notes.
1637 (aarch64_decode_insn, print_operands): Likewise.
1638 (print_aarch64_disassembler_options): Document notes.
1639 * aarch64-opc.c (aarch64_print_operand): Support notes.
1641 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1644 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1645 and take error struct.
1646 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1647 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1648 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1649 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1650 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1651 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1652 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1653 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1654 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1655 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1656 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1657 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1658 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1659 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1660 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1661 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1662 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1663 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1664 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1665 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1666 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1667 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1668 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1669 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1670 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1671 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1672 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1673 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1674 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1675 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1676 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1677 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1678 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1679 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1680 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1681 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1682 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1683 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1684 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1685 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1686 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1687 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1688 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1689 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1690 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1691 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1692 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1693 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1694 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1695 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1696 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1697 (determine_disassembling_preference, aarch64_decode_insn,
1698 print_insn_aarch64_word, print_insn_data): Take errors struct.
1699 (print_insn_aarch64): Use errors.
1700 * aarch64-asm-2.c: Regenerate.
1701 * aarch64-dis-2.c: Regenerate.
1702 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1703 boolean in aarch64_insert_operan.
1704 (print_operand_extractor): Likewise.
1705 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1707 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
1709 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1711 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1713 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1715 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1717 * cr16-opc.c (cr16_instruction): Comment typo fix.
1718 * hppa-dis.c (print_insn_hppa): Likewise.
1720 2018-05-08 Jim Wilson <jimw@sifive.com>
1722 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1723 (match_c_slli64, match_srxi_as_c_srxi): New.
1724 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1725 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1726 <c.slli, c.srli, c.srai>: Use match_s_slli.
1727 <c.slli64, c.srli64, c.srai64>: New.
1729 2018-05-08 Alan Modra <amodra@gmail.com>
1731 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1732 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1733 partition opcode space for index lookup.
1735 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1737 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1738 <insn_length>: ...with this. Update usage.
1739 Remove duplicate call to *info->memory_error_func.
1741 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1742 H.J. Lu <hongjiu.lu@intel.com>
1744 * i386-dis.c (Gva): New.
1745 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1746 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1747 (prefix_table): New instructions (see prefix above).
1748 (mod_table): New instructions (see prefix above).
1749 (OP_G): Handle va_mode.
1750 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1751 CPU_MOVDIR64B_FLAGS.
1752 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1753 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1754 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1755 * i386-opc.tbl: Add movidir{i,64b}.
1756 * i386-init.h: Regenerated.
1757 * i386-tbl.h: Likewise.
1759 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1761 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1763 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1764 (AddrPrefixOpReg): This.
1765 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1766 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1768 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1770 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1771 (vle_num_opcodes): Likewise.
1772 (spe2_num_opcodes): Likewise.
1773 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1774 initialization loop.
1775 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1776 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1779 2018-05-01 Tamar Christina <tamar.christina@arm.com>
1781 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1783 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
1785 Makefile.am: Added nfp-dis.c.
1786 configure.ac: Added bfd_nfp_arch.
1787 disassemble.h: Added print_insn_nfp prototype.
1788 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1789 nfp-dis.c: New, for NFP support.
1790 po/POTFILES.in: Added nfp-dis.c to the list.
1791 Makefile.in: Regenerate.
1792 configure: Regenerate.
1794 2018-04-26 Jan Beulich <jbeulich@suse.com>
1796 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1797 templates into their base ones.
1798 * i386-tlb.h: Re-generate.
1800 2018-04-26 Jan Beulich <jbeulich@suse.com>
1802 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1803 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1804 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1805 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1806 * i386-init.h: Re-generate.
1808 2018-04-26 Jan Beulich <jbeulich@suse.com>
1810 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1811 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1812 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1813 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1815 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1817 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1819 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1820 cpuregzmm, and cpuregmask.
1821 * i386-init.h: Re-generate.
1822 * i386-tbl.h: Re-generate.
1824 2018-04-26 Jan Beulich <jbeulich@suse.com>
1826 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1827 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1828 * i386-init.h: Re-generate.
1830 2018-04-26 Jan Beulich <jbeulich@suse.com>
1832 * i386-gen.c (VexImmExt): Delete.
1833 * i386-opc.h (VexImmExt, veximmext): Delete.
1834 * i386-opc.tbl: Drop all VexImmExt uses.
1835 * i386-tlb.h: Re-generate.
1837 2018-04-25 Jan Beulich <jbeulich@suse.com>
1839 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1840 register-only forms.
1841 * i386-tlb.h: Re-generate.
1843 2018-04-25 Tamar Christina <tamar.christina@arm.com>
1845 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1847 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1849 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1851 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1852 (cpu_flags): Add CpuCLDEMOTE.
1853 * i386-init.h: Regenerate.
1854 * i386-opc.h (enum): Add CpuCLDEMOTE,
1855 (i386_cpu_flags): Add cpucldemote.
1856 * i386-opc.tbl: Add cldemote.
1857 * i386-tbl.h: Regenerate.
1859 2018-04-16 Alan Modra <amodra@gmail.com>
1861 * Makefile.am: Remove sh5 and sh64 support.
1862 * configure.ac: Likewise.
1863 * disassemble.c: Likewise.
1864 * disassemble.h: Likewise.
1865 * sh-dis.c: Likewise.
1866 * sh64-dis.c: Delete.
1867 * sh64-opc.c: Delete.
1868 * sh64-opc.h: Delete.
1869 * Makefile.in: Regenerate.
1870 * configure: Regenerate.
1871 * po/POTFILES.in: Regenerate.
1873 2018-04-16 Alan Modra <amodra@gmail.com>
1875 * Makefile.am: Remove w65 support.
1876 * configure.ac: Likewise.
1877 * disassemble.c: Likewise.
1878 * disassemble.h: Likewise.
1879 * w65-dis.c: Delete.
1880 * w65-opc.h: Delete.
1881 * Makefile.in: Regenerate.
1882 * configure: Regenerate.
1883 * po/POTFILES.in: Regenerate.
1885 2018-04-16 Alan Modra <amodra@gmail.com>
1887 * configure.ac: Remove we32k support.
1888 * configure: Regenerate.
1890 2018-04-16 Alan Modra <amodra@gmail.com>
1892 * Makefile.am: Remove m88k support.
1893 * configure.ac: Likewise.
1894 * disassemble.c: Likewise.
1895 * disassemble.h: Likewise.
1896 * m88k-dis.c: Delete.
1897 * Makefile.in: Regenerate.
1898 * configure: Regenerate.
1899 * po/POTFILES.in: Regenerate.
1901 2018-04-16 Alan Modra <amodra@gmail.com>
1903 * Makefile.am: Remove i370 support.
1904 * configure.ac: Likewise.
1905 * disassemble.c: Likewise.
1906 * disassemble.h: Likewise.
1907 * i370-dis.c: Delete.
1908 * i370-opc.c: Delete.
1909 * Makefile.in: Regenerate.
1910 * configure: Regenerate.
1911 * po/POTFILES.in: Regenerate.
1913 2018-04-16 Alan Modra <amodra@gmail.com>
1915 * Makefile.am: Remove h8500 support.
1916 * configure.ac: Likewise.
1917 * disassemble.c: Likewise.
1918 * disassemble.h: Likewise.
1919 * h8500-dis.c: Delete.
1920 * h8500-opc.h: Delete.
1921 * Makefile.in: Regenerate.
1922 * configure: Regenerate.
1923 * po/POTFILES.in: Regenerate.
1925 2018-04-16 Alan Modra <amodra@gmail.com>
1927 * configure.ac: Remove tahoe support.
1928 * configure: Regenerate.
1930 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1932 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1934 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1936 * i386-tbl.h: Regenerated.
1938 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1940 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1941 PREFIX_MOD_1_0FAE_REG_6.
1943 (OP_E_register): Use va_mode.
1944 * i386-dis-evex.h (prefix_table):
1945 New instructions (see prefixes above).
1946 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1947 (cpu_flags): Likewise.
1948 * i386-opc.h (enum): Likewise.
1949 (i386_cpu_flags): Likewise.
1950 * i386-opc.tbl: Add umonitor, umwait, tpause.
1951 * i386-init.h: Regenerate.
1952 * i386-tbl.h: Likewise.
1954 2018-04-11 Alan Modra <amodra@gmail.com>
1956 * opcodes/i860-dis.c: Delete.
1957 * opcodes/i960-dis.c: Delete.
1958 * Makefile.am: Remove i860 and i960 support.
1959 * configure.ac: Likewise.
1960 * disassemble.c: Likewise.
1961 * disassemble.h: Likewise.
1962 * Makefile.in: Regenerate.
1963 * configure: Regenerate.
1964 * po/POTFILES.in: Regenerate.
1966 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1969 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1971 (print_insn): Clear vex instead of vex.evex.
1973 2018-04-04 Nick Clifton <nickc@redhat.com>
1975 * po/es.po: Updated Spanish translation.
1977 2018-03-28 Jan Beulich <jbeulich@suse.com>
1979 * i386-gen.c (opcode_modifiers): Delete VecESize.
1980 * i386-opc.h (VecESize): Delete.
1981 (struct i386_opcode_modifier): Delete vecesize.
1982 * i386-opc.tbl: Drop VecESize.
1983 * i386-tlb.h: Re-generate.
1985 2018-03-28 Jan Beulich <jbeulich@suse.com>
1987 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1988 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1989 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1990 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1991 * i386-tlb.h: Re-generate.
1993 2018-03-28 Jan Beulich <jbeulich@suse.com>
1995 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1997 * i386-tlb.h: Re-generate.
1999 2018-03-28 Jan Beulich <jbeulich@suse.com>
2001 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
2002 (vex_len_table): Drop Y for vcvt*2si.
2003 (putop): Replace plain 'Y' handling by abort().
2005 2018-03-28 Nick Clifton <nickc@redhat.com>
2008 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
2009 instructions with only a base address register.
2010 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
2011 handle AARHC64_OPND_SVE_ADDR_R.
2012 (aarch64_print_operand): Likewise.
2013 * aarch64-asm-2.c: Regenerate.
2014 * aarch64_dis-2.c: Regenerate.
2015 * aarch64-opc-2.c: Regenerate.
2017 2018-03-22 Jan Beulich <jbeulich@suse.com>
2019 * i386-opc.tbl: Drop VecESize from register only insn forms and
2020 memory forms not allowing broadcast.
2021 * i386-tlb.h: Re-generate.
2023 2018-03-22 Jan Beulich <jbeulich@suse.com>
2025 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
2026 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
2027 sha256*): Drop Disp<N>.
2029 2018-03-22 Jan Beulich <jbeulich@suse.com>
2031 * i386-dis.c (EbndS, bnd_swap_mode): New.
2032 (prefix_table): Use EbndS.
2033 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
2034 * i386-opc.tbl (bndmov): Move misplaced Load.
2035 * i386-tlb.h: Re-generate.
2037 2018-03-22 Jan Beulich <jbeulich@suse.com>
2039 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
2040 templates allowing memory operands and folded ones for register
2042 * i386-tlb.h: Re-generate.
2044 2018-03-22 Jan Beulich <jbeulich@suse.com>
2046 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
2047 256-bit templates. Drop redundant leftover Disp<N>.
2048 * i386-tlb.h: Re-generate.
2050 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
2052 * riscv-opc.c (riscv_insn_types): New.
2054 2018-03-13 Nick Clifton <nickc@redhat.com>
2056 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2058 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2060 * i386-opc.tbl: Add Optimize to clr.
2061 * i386-tbl.h: Regenerated.
2063 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2065 * i386-gen.c (opcode_modifiers): Remove OldGcc.
2066 * i386-opc.h (OldGcc): Removed.
2067 (i386_opcode_modifier): Remove oldgcc.
2068 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2069 instructions for old (<= 2.8.1) versions of gcc.
2070 * i386-tbl.h: Regenerated.
2072 2018-03-08 Jan Beulich <jbeulich@suse.com>
2074 * i386-opc.h (EVEXDYN): New.
2075 * i386-opc.tbl: Fold various AVX512VL templates.
2076 * i386-tlb.h: Re-generate.
2078 2018-03-08 Jan Beulich <jbeulich@suse.com>
2080 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2081 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2082 vpexpandd, vpexpandq): Fold AFX512VF templates.
2083 * i386-tlb.h: Re-generate.
2085 2018-03-08 Jan Beulich <jbeulich@suse.com>
2087 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2088 Fold 128- and 256-bit VEX-encoded templates.
2089 * i386-tlb.h: Re-generate.
2091 2018-03-08 Jan Beulich <jbeulich@suse.com>
2093 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2094 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2095 vpexpandd, vpexpandq): Fold AVX512F templates.
2096 * i386-tlb.h: Re-generate.
2098 2018-03-08 Jan Beulich <jbeulich@suse.com>
2100 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2101 64-bit templates. Drop Disp<N>.
2102 * i386-tlb.h: Re-generate.
2104 2018-03-08 Jan Beulich <jbeulich@suse.com>
2106 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2107 and 256-bit templates.
2108 * i386-tlb.h: Re-generate.
2110 2018-03-08 Jan Beulich <jbeulich@suse.com>
2112 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2113 * i386-tlb.h: Re-generate.
2115 2018-03-08 Jan Beulich <jbeulich@suse.com>
2117 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2119 * i386-tlb.h: Re-generate.
2121 2018-03-08 Jan Beulich <jbeulich@suse.com>
2123 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2124 * i386-tlb.h: Re-generate.
2126 2018-03-08 Jan Beulich <jbeulich@suse.com>
2128 * i386-gen.c (opcode_modifiers): Delete FloatD.
2129 * i386-opc.h (FloatD): Delete.
2130 (struct i386_opcode_modifier): Delete floatd.
2131 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2133 * i386-tlb.h: Re-generate.
2135 2018-03-08 Jan Beulich <jbeulich@suse.com>
2137 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2139 2018-03-08 Jan Beulich <jbeulich@suse.com>
2141 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2142 * i386-tlb.h: Re-generate.
2144 2018-03-08 Jan Beulich <jbeulich@suse.com>
2146 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2148 * i386-tlb.h: Re-generate.
2150 2018-03-07 Alan Modra <amodra@gmail.com>
2152 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2154 * disassemble.h (print_insn_rs6000): Delete.
2155 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2156 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2157 (print_insn_rs6000): Delete.
2159 2018-03-03 Alan Modra <amodra@gmail.com>
2161 * sysdep.h (opcodes_error_handler): Define.
2162 (_bfd_error_handler): Declare.
2163 * Makefile.am: Remove stray #.
2164 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
2166 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2167 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2168 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2169 opcodes_error_handler to print errors. Standardize error messages.
2170 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2171 and include opintl.h.
2172 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2173 * i386-gen.c: Standardize error messages.
2174 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2175 * Makefile.in: Regenerate.
2176 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2177 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2178 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2179 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2180 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2181 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2182 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2183 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2184 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2185 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2186 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2187 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2188 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2190 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
2192 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2193 vpsub[bwdq] instructions.
2194 * i386-tbl.h: Regenerated.
2196 2018-03-01 Alan Modra <amodra@gmail.com>
2198 * configure.ac (ALL_LINGUAS): Sort.
2199 * configure: Regenerate.
2201 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
2203 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2204 macro by assignements.
2206 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
2209 * i386-gen.c (opcode_modifiers): Add Optimize.
2210 * i386-opc.h (Optimize): New enum.
2211 (i386_opcode_modifier): Add optimize.
2212 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2213 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2214 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2215 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2216 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2218 * i386-tbl.h: Regenerated.
2220 2018-02-26 Alan Modra <amodra@gmail.com>
2222 * crx-dis.c (getregliststring): Allocate a large enough buffer
2223 to silence false positive gcc8 warning.
2225 2018-02-22 Shea Levy <shea@shealevy.com>
2227 * disassemble.c (ARCH_riscv): Define if ARCH_all.
2229 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
2231 * i386-opc.tbl: Add {rex},
2232 * i386-tbl.h: Regenerated.
2234 2018-02-20 Maciej W. Rozycki <macro@mips.com>
2236 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2237 (mips16_opcodes): Replace `M' with `m' for "restore".
2239 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
2241 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2243 2018-02-13 Maciej W. Rozycki <macro@mips.com>
2245 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2246 variable to `function_index'.
2248 2018-02-13 Nick Clifton <nickc@redhat.com>
2251 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2252 about truncation of printing.
2254 2018-02-12 Henry Wong <henry@stuffedcow.net>
2256 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2258 2018-02-05 Nick Clifton <nickc@redhat.com>
2260 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2262 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2264 * i386-dis.c (enum): Add pconfig.
2265 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2266 (cpu_flags): Add CpuPCONFIG.
2267 * i386-opc.h (enum): Add CpuPCONFIG.
2268 (i386_cpu_flags): Add cpupconfig.
2269 * i386-opc.tbl: Add PCONFIG instruction.
2270 * i386-init.h: Regenerate.
2271 * i386-tbl.h: Likewise.
2273 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2275 * i386-dis.c (enum): Add PREFIX_0F09.
2276 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2277 (cpu_flags): Add CpuWBNOINVD.
2278 * i386-opc.h (enum): Add CpuWBNOINVD.
2279 (i386_cpu_flags): Add cpuwbnoinvd.
2280 * i386-opc.tbl: Add WBNOINVD instruction.
2281 * i386-init.h: Regenerate.
2282 * i386-tbl.h: Likewise.
2284 2018-01-17 Jim Wilson <jimw@sifive.com>
2286 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2288 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2290 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2291 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2292 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2293 (cpu_flags): Add CpuIBT, CpuSHSTK.
2294 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2295 (i386_cpu_flags): Add cpuibt, cpushstk.
2296 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2297 * i386-init.h: Regenerate.
2298 * i386-tbl.h: Likewise.
2300 2018-01-16 Nick Clifton <nickc@redhat.com>
2302 * po/pt_BR.po: Updated Brazilian Portugese translation.
2303 * po/de.po: Updated German translation.
2305 2018-01-15 Jim Wilson <jimw@sifive.com>
2307 * riscv-opc.c (match_c_nop): New.
2308 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2310 2018-01-15 Nick Clifton <nickc@redhat.com>
2312 * po/uk.po: Updated Ukranian translation.
2314 2018-01-13 Nick Clifton <nickc@redhat.com>
2316 * po/opcodes.pot: Regenerated.
2318 2018-01-13 Nick Clifton <nickc@redhat.com>
2320 * configure: Regenerate.
2322 2018-01-13 Nick Clifton <nickc@redhat.com>
2324 2.30 branch created.
2326 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2328 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2329 * i386-tbl.h: Regenerate.
2331 2018-01-10 Jan Beulich <jbeulich@suse.com>
2333 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2334 * i386-tbl.h: Re-generate.
2336 2018-01-10 Jan Beulich <jbeulich@suse.com>
2338 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2339 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2340 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2341 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2342 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2343 Disp8MemShift of AVX512VL forms.
2344 * i386-tbl.h: Re-generate.
2346 2018-01-09 Jim Wilson <jimw@sifive.com>
2348 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2349 then the hi_addr value is zero.
2351 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2353 * arm-dis.c (arm_opcodes): Add csdb.
2354 (thumb32_opcodes): Add csdb.
2356 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2358 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2359 * aarch64-asm-2.c: Regenerate.
2360 * aarch64-dis-2.c: Regenerate.
2361 * aarch64-opc-2.c: Regenerate.
2363 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2366 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2367 Remove AVX512 vmovd with 64-bit operands.
2368 * i386-tbl.h: Regenerated.
2370 2018-01-05 Jim Wilson <jimw@sifive.com>
2372 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2375 2018-01-03 Alan Modra <amodra@gmail.com>
2377 Update year range in copyright notice of all files.
2379 2018-01-02 Jan Beulich <jbeulich@suse.com>
2381 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2382 and OPERAND_TYPE_REGZMM entries.
2384 For older changes see ChangeLog-2017
2386 Copyright (C) 2018 Free Software Foundation, Inc.
2388 Copying and distribution of this file, with or without modification,
2389 are permitted in any medium without royalty provided the copyright
2390 notice and this notice are preserved.
2396 version-control: never