1 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
3 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
6 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
8 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
10 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
12 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
13 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
14 XLS_MASK, PPCVSX2): New defines.
15 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
16 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
17 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
18 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
19 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
20 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
21 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
22 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
23 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
24 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
25 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
26 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
27 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
28 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
29 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
30 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
31 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
32 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
33 <lxvx, stxvx>: New extended mnemonics.
35 2013-05-17 Alan Modra <amodra@gmail.com>
37 * ia64-raw.tbl: Replace non-ASCII char.
38 * ia64-waw.tbl: Likewise.
39 * ia64-asmtab.c: Regenerate.
41 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
43 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
44 * i386-init.h: Regenerated.
46 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
48 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
49 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
50 check from [0, 255] to [-128, 255].
52 2013-05-09 Andrew Pinski <apinski@cavium.com>
54 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
55 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
56 (parse_mips_dis_option): Handle the virt option.
57 (print_insn_args): Handle "+J".
58 (print_mips_disassembler_options): Print out message about virt64.
59 * mips-opc.c (IVIRT): New define.
60 (IVIRT64): New define.
61 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
62 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
63 Move rfe to the bottom as it conflicts with tlbgp.
65 2013-05-09 Alan Modra <amodra@gmail.com>
67 * ppc-opc.c (extract_vlesi): Properly sign extend.
68 (extract_vlensi): Likewise. Comment reason for setting invalid.
70 2013-05-02 Nick Clifton <nickc@redhat.com>
72 * msp430-dis.c: Add support for MSP430X instructions.
74 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
76 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
79 2013-04-17 Wei-chen Wang <cole945@gmail.com>
82 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
84 (hash_insns_list): Likewise.
86 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
88 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
91 2013-04-08 Jan Beulich <jbeulich@suse.com>
93 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
94 * i386-tbl.h: Re-generate.
96 2013-04-06 David S. Miller <davem@davemloft.net>
98 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
99 of an opcode, prefer the one with F_PREFERRED set.
100 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
101 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
102 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
103 mark existing mnenomics as aliases. Add "cc" suffix to edge
104 instructions generating condition codes, mark existing mnenomics
105 as aliases. Add "fp" prefix to VIS compare instructions, mark
106 existing mnenomics as aliases.
108 2013-04-03 Nick Clifton <nickc@redhat.com>
110 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
111 destination address by subtracting the operand from the current
113 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
114 a positive value in the insn.
115 (extract_u16_loop): Do not negate the returned value.
116 (D16_LOOP): Add V850_INVERSE_PCREL flag.
118 (ceilf.sw): Remove duplicate entry.
119 (cvtf.hs): New entry.
125 (maddf.s): Restrict to E3V5 architectures.
127 (nmaddf.s): Likewise.
128 (nmsubf.s): Likewise.
130 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
132 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
134 (print_insn): Pass sizeflag to get_sib.
136 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
139 * tic6x-dis.c: Add support for displaying 16-bit insns.
141 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
144 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
145 individual msb and lsb halves in src1 & src2 fields. Discard the
146 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
147 follow what Ti SDK does in that case as any value in the src1
148 field yields the same output with SDK disassembler.
150 2013-03-12 Michael Eager <eager@eagercon.com>
152 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
154 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
156 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
158 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
160 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
162 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
164 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
166 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
168 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
169 (thumb32_opcodes): Likewise.
170 (print_insn_thumb32): Handle 'S' control char.
172 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
174 * lm32-desc.c: Regenerate.
176 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
178 * i386-reg.tbl (riz): Add RegRex64.
179 * i386-tbl.h: Regenerated.
181 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
183 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
184 (aarch64_feature_crc): New static.
186 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
187 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
188 * aarch64-asm-2.c: Re-generate.
189 * aarch64-dis-2.c: Ditto.
190 * aarch64-opc-2.c: Ditto.
192 2013-02-27 Alan Modra <amodra@gmail.com>
194 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
195 * rl78-decode.c: Regenerate.
197 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
199 * rl78-decode.opc: Fix encoding of DIVWU insn.
200 * rl78-decode.c: Regenerate.
202 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
205 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
207 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
208 (cpu_flags): Add CpuSMAP.
210 * i386-opc.h (CpuSMAP): New.
211 (i386_cpu_flags): Add cpusmap.
213 * i386-opc.tbl: Add clac and stac.
215 * i386-init.h: Regenerated.
216 * i386-tbl.h: Likewise.
218 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
220 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
221 which also makes the disassembler output be in little
222 endian like it should be.
224 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
226 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
228 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
230 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
232 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
233 section disassembled.
235 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
237 * arm-dis.c: Update strht pattern.
239 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
241 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
242 single-float. Disable ll, lld, sc and scd for EE. Disable the
243 trunc.w.s macro for EE.
245 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
246 Andrew Jenner <andrew@codesourcery.com>
248 Based on patches from Altera Corporation.
250 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
252 * Makefile.in: Regenerated.
253 * configure.in: Add case for bfd_nios2_arch.
254 * configure: Regenerated.
255 * disassemble.c (ARCH_nios2): Define.
256 (disassembler): Add case for bfd_arch_nios2.
257 * nios2-dis.c: New file.
258 * nios2-opc.c: New file.
260 2013-02-04 Alan Modra <amodra@gmail.com>
262 * po/POTFILES.in: Regenerate.
263 * rl78-decode.c: Regenerate.
264 * rx-decode.c: Regenerate.
266 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
268 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
269 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
270 * aarch64-asm.c (convert_xtl_to_shll): New function.
271 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
272 calling convert_xtl_to_shll.
273 * aarch64-dis.c (convert_shll_to_xtl): New function.
274 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
275 calling convert_shll_to_xtl.
276 * aarch64-gen.c: Update copyright year.
277 * aarch64-asm-2.c: Re-generate.
278 * aarch64-dis-2.c: Re-generate.
279 * aarch64-opc-2.c: Re-generate.
281 2013-01-24 Nick Clifton <nickc@redhat.com>
283 * v850-dis.c: Add support for e3v5 architecture.
284 * v850-opc.c: Likewise.
286 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
288 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
289 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
290 * aarch64-opc.c (operand_general_constraint_met_p): For
291 AARCH64_MOD_LSL, move the range check on the shift amount before the
292 alignment check; change to call set_sft_amount_out_of_range_error
293 instead of set_imm_out_of_range_error.
294 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
295 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
296 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
299 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
301 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
303 * i386-init.h: Regenerated.
304 * i386-tbl.h: Likewise.
306 2013-01-15 Nick Clifton <nickc@redhat.com>
308 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
310 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
312 2013-01-14 Will Newton <will.newton@imgtec.com>
314 * metag-dis.c (REG_WIDTH): Increase to 64.
316 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
318 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
319 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
320 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
322 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
323 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
324 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
325 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
327 2013-01-10 Will Newton <will.newton@imgtec.com>
329 * Makefile.am: Add Meta.
330 * configure.in: Add Meta.
331 * disassemble.c: Add Meta support.
332 * metag-dis.c: New file.
333 * Makefile.in: Regenerate.
334 * configure: Regenerate.
336 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
338 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
339 (match_opcode): Rename to cr16_match_opcode.
341 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
343 * mips-dis.c: Add names for CP0 registers of r5900.
344 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
345 instructions sq and lq.
346 Add support for MIPS r5900 CPU.
347 Add support for 128 bit MMI (Multimedia Instructions).
348 Add support for EE instructions (Emotion Engine).
349 Disable unsupported floating point instructions (64 bit and
350 undefined compare operations).
351 Enable instructions of MIPS ISA IV which are supported by r5900.
352 Disable 64 bit co processor instructions.
353 Disable 64 bit multiplication and division instructions.
354 Disable instructions for co-processor 2 and 3, because these are
355 not supported (preparation for later VU0 support (Vector Unit)).
356 Disable cvt.w.s because this behaves like trunc.w.s and the
357 correct execution can't be ensured on r5900.
358 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
359 will confuse less developers and compilers.
361 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
363 * aarch64-opc.c (aarch64_print_operand): Change to print
364 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
366 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
367 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
370 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
372 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
373 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
375 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
377 * i386-gen.c (process_copyright): Update copyright year to 2013.
379 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
381 * cr16-dis.c (match_opcode,make_instruction): Remove static
383 (dwordU,wordU): Moved typedefs to opcode/cr16.h
384 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
386 For older changes see ChangeLog-2012
388 Copyright (C) 2013 Free Software Foundation, Inc.
390 Copying and distribution of this file, with or without modification,
391 are permitted in any medium without royalty provided the copyright
392 notice and this notice are preserved.
398 version-control: never