1 2018-07-19 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
4 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
5 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
6 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
7 * i386-tbl.h: Re-generate.
9 2018-07-19 Jan Beulich <jbeulich@suse.com>
11 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
12 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
13 VPCLMULQDQ templates into their respective AVX512VL counterparts
14 where possible, using Disp8ShiftVL and CheckRegSize instead of
15 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
16 * i386-tbl.h: Re-generate.
18 2018-07-19 Jan Beulich <jbeulich@suse.com>
20 * i386-opc.tbl: Fold AVX512DQ templates into their respective
21 AVX512VL counterparts where possible, using Disp8ShiftVL and
22 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
23 IgnoreSize) as appropriate.
24 * i386-tbl.h: Re-generate.
26 2018-07-19 Jan Beulich <jbeulich@suse.com>
28 * i386-opc.tbl: Fold AVX512BW templates into their respective
29 AVX512VL counterparts where possible, using Disp8ShiftVL and
30 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
31 IgnoreSize) as appropriate.
32 * i386-tbl.h: Re-generate.
34 2018-07-19 Jan Beulich <jbeulich@suse.com>
36 * i386-opc.tbl: Fold AVX512CD templates into their respective
37 AVX512VL counterparts where possible, using Disp8ShiftVL and
38 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
39 IgnoreSize) as appropriate.
40 * i386-tbl.h: Re-generate.
42 2018-07-19 Jan Beulich <jbeulich@suse.com>
44 * i386-opc.h (DISP8_SHIFT_VL): New.
45 * i386-opc.tbl (Disp8ShiftVL): Define.
46 (various): Fold AVX512VL templates into their respective
47 AVX512F counterparts where possible, using Disp8ShiftVL and
48 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
49 IgnoreSize) as appropriate.
50 * i386-tbl.h: Re-generate.
52 2018-07-19 Jan Beulich <jbeulich@suse.com>
54 * Makefile.am: Change dependencies and rule for
55 $(srcdir)/i386-init.h.
56 * Makefile.in: Re-generate.
57 * i386-gen.c (process_i386_opcodes): New local variable
58 "marker". Drop opening of input file. Recognize marker and line
60 * i386-opc.tbl (OPCODE_I386_H): Define.
61 (i386-opc.h): Include it.
64 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
67 * i386-opc.h (Byte): Update comments.
76 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
78 * i386-tbl.h: Regenerated.
80 2018-07-12 Sudakshina Das <sudi.das@arm.com>
82 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
83 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
84 * aarch64-asm-2.c: Regenerate.
85 * aarch64-dis-2.c: Regenerate.
86 * aarch64-opc-2.c: Regenerate.
88 2018-07-12 Tamar Christina <tamar.christina@arm.com>
91 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
92 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
93 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
94 sqdmulh, sqrdmulh): Use Em16.
96 2018-07-11 Sudakshina Das <sudi.das@arm.com>
98 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
99 csdb together with them.
100 (thumb32_opcodes): Likewise.
102 2018-07-11 Jan Beulich <jbeulich@suse.com>
104 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
105 requiring 32-bit registers as operands 2 and 3. Improve
107 (mwait, mwaitx): Fold templates. Improve comments.
108 OPERAND_TYPE_INOUTPORTREG.
109 * i386-tbl.h: Re-generate.
111 2018-07-11 Jan Beulich <jbeulich@suse.com>
113 * i386-gen.c (operand_type_init): Remove
114 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
115 OPERAND_TYPE_INOUTPORTREG.
116 * i386-init.h: Re-generate.
118 2018-07-11 Jan Beulich <jbeulich@suse.com>
120 * i386-opc.tbl (wrssd, wrussd): Add Dword.
121 (wrssq, wrussq): Add Qword.
122 * i386-tbl.h: Re-generate.
124 2018-07-11 Jan Beulich <jbeulich@suse.com>
126 * i386-opc.h: Rename OTMax to OTNum.
127 (OTNumOfUints): Adjust calculation.
128 (OTUnused): Directly alias to OTNum.
130 2018-07-09 Maciej W. Rozycki <macro@mips.com>
132 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
134 (lea_reg_xys): Likewise.
135 (print_insn_loop_primitive): Rename `reg' local variable to
138 2018-07-06 Tamar Christina <tamar.christina@arm.com>
141 * aarch64-tbl.h (ldarh): Fix disassembly mask.
143 2018-07-06 Tamar Christina <tamar.christina@arm.com>
146 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
147 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
149 2018-07-02 Maciej W. Rozycki <macro@mips.com>
152 * mips-dis.c (mips_option_arg_t): New enumeration.
153 (mips_options): New variable.
154 (disassembler_options_mips): New function.
155 (print_mips_disassembler_options): Reimplement in terms of
156 `disassembler_options_mips'.
157 * arm-dis.c (disassembler_options_arm): Adapt to using the
158 `disasm_options_and_args_t' structure.
159 * ppc-dis.c (disassembler_options_powerpc): Likewise.
160 * s390-dis.c (disassembler_options_s390): Likewise.
162 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
164 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
166 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
167 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
168 * testsuite/ld-arm/tls-longplt.d: Likewise.
170 2018-06-29 Tamar Christina <tamar.christina@arm.com>
173 * aarch64-asm-2.c: Regenerate.
174 * aarch64-dis-2.c: Likewise.
175 * aarch64-opc-2.c: Likewise.
176 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
177 * aarch64-opc.c (operand_general_constraint_met_p,
178 aarch64_print_operand): Likewise.
179 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
180 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
182 (AARCH64_OPERANDS): Add Em2.
184 2018-06-26 Nick Clifton <nickc@redhat.com>
186 * po/uk.po: Updated Ukranian translation.
187 * po/de.po: Updated German translation.
188 * po/pt_BR.po: Updated Brazilian Portuguese translation.
190 2018-06-26 Nick Clifton <nickc@redhat.com>
192 * nfp-dis.c: Fix spelling mistake.
194 2018-06-24 Nick Clifton <nickc@redhat.com>
196 * configure: Regenerate.
197 * po/opcodes.pot: Regenerate.
199 2018-06-24 Nick Clifton <nickc@redhat.com>
203 2018-06-19 Tamar Christina <tamar.christina@arm.com>
205 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
206 * aarch64-asm-2.c: Regenerate.
207 * aarch64-dis-2.c: Likewise.
209 2018-06-21 Maciej W. Rozycki <macro@mips.com>
211 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
212 `-M ginv' option description.
214 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
217 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
220 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
222 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
223 * configure.ac: Remove AC_PREREQ.
224 * Makefile.in: Re-generate.
225 * aclocal.m4: Re-generate.
226 * configure: Re-generate.
228 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
230 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
231 mips64r6 descriptors.
232 (parse_mips_ase_option): Handle -Mginv option.
233 (print_mips_disassembler_options): Document -Mginv.
234 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
236 (mips_opcodes): Define ginvi and ginvt.
238 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
239 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
241 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
242 * mips-opc.c (CRC, CRC64): New macros.
243 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
244 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
247 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
250 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
251 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
253 2018-06-06 Alan Modra <amodra@gmail.com>
255 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
256 setjmp. Move init for some other vars later too.
258 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
260 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
261 (dis_private): Add new fields for property section tracking.
262 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
263 (xtensa_instruction_fits): New functions.
264 (fetch_data): Bump minimal fetch size to 4.
265 (print_insn_xtensa): Make struct dis_private static.
266 Load and prepare property table on section change.
267 Don't disassemble literals. Don't disassemble instructions that
268 cross property table boundaries.
270 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
272 * configure: Regenerated.
274 2018-06-01 Jan Beulich <jbeulich@suse.com>
276 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
277 * i386-tbl.h: Re-generate.
279 2018-06-01 Jan Beulich <jbeulich@suse.com>
281 * i386-opc.tbl (sldt, str): Add NoRex64.
282 * i386-tbl.h: Re-generate.
284 2018-06-01 Jan Beulich <jbeulich@suse.com>
286 * i386-opc.tbl (invpcid): Add Oword.
287 * i386-tbl.h: Re-generate.
289 2018-06-01 Alan Modra <amodra@gmail.com>
291 * sysdep.h (_bfd_error_handler): Don't declare.
292 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
293 * rl78-decode.opc: Likewise.
294 * msp430-decode.c: Regenerate.
295 * rl78-decode.c: Regenerate.
297 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
299 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
300 * i386-init.h : Regenerated.
302 2018-05-25 Alan Modra <amodra@gmail.com>
304 * Makefile.in: Regenerate.
305 * po/POTFILES.in: Regenerate.
307 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
309 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
310 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
311 (insert_bab, extract_bab, insert_btab, extract_btab,
312 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
313 (BAT, BBA VBA RBS XB6S): Delete macros.
314 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
315 (BB, BD, RBX, XC6): Update for new macros.
316 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
317 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
318 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
319 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
321 2018-05-18 John Darrington <john@darrington.wattle.id.au>
323 * Makefile.am: Add support for s12z architecture.
324 * configure.ac: Likewise.
325 * disassemble.c: Likewise.
326 * disassemble.h: Likewise.
327 * Makefile.in: Regenerate.
328 * configure: Regenerate.
329 * s12z-dis.c: New file.
332 2018-05-18 Alan Modra <amodra@gmail.com>
334 * nfp-dis.c: Don't #include libbfd.h.
335 (init_nfp3200_priv): Use bfd_get_section_contents.
336 (nit_nfp6000_mecsr_sec): Likewise.
338 2018-05-17 Nick Clifton <nickc@redhat.com>
340 * po/zh_CN.po: Updated simplified Chinese translation.
342 2018-05-16 Tamar Christina <tamar.christina@arm.com>
345 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
346 * aarch64-dis-2.c: Regenerate.
348 2018-05-15 Tamar Christina <tamar.christina@arm.com>
351 * aarch64-asm.c (opintl.h): Include.
352 (aarch64_ins_sysreg): Enforce read/write constraints.
353 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
354 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
355 (F_REG_READ, F_REG_WRITE): New.
356 * aarch64-opc.c (aarch64_print_operand): Generate notes for
358 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
359 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
360 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
361 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
362 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
363 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
364 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
365 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
366 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
367 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
368 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
369 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
370 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
371 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
372 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
373 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
374 msr (F_SYS_WRITE), mrs (F_SYS_READ).
376 2018-05-15 Tamar Christina <tamar.christina@arm.com>
379 * aarch64-dis.c (no_notes: New.
380 (parse_aarch64_dis_option): Support notes.
381 (aarch64_decode_insn, print_operands): Likewise.
382 (print_aarch64_disassembler_options): Document notes.
383 * aarch64-opc.c (aarch64_print_operand): Support notes.
385 2018-05-15 Tamar Christina <tamar.christina@arm.com>
388 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
389 and take error struct.
390 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
391 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
392 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
393 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
394 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
395 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
396 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
397 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
398 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
399 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
400 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
401 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
402 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
403 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
404 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
405 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
406 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
407 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
408 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
409 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
410 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
411 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
412 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
413 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
414 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
415 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
416 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
417 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
418 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
419 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
420 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
421 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
422 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
423 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
424 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
425 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
426 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
427 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
428 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
429 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
430 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
431 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
432 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
433 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
434 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
435 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
436 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
437 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
438 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
439 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
440 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
441 (determine_disassembling_preference, aarch64_decode_insn,
442 print_insn_aarch64_word, print_insn_data): Take errors struct.
443 (print_insn_aarch64): Use errors.
444 * aarch64-asm-2.c: Regenerate.
445 * aarch64-dis-2.c: Regenerate.
446 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
447 boolean in aarch64_insert_operan.
448 (print_operand_extractor): Likewise.
449 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
451 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
453 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
455 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
457 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
459 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
461 * cr16-opc.c (cr16_instruction): Comment typo fix.
462 * hppa-dis.c (print_insn_hppa): Likewise.
464 2018-05-08 Jim Wilson <jimw@sifive.com>
466 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
467 (match_c_slli64, match_srxi_as_c_srxi): New.
468 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
469 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
470 <c.slli, c.srli, c.srai>: Use match_s_slli.
471 <c.slli64, c.srli64, c.srai64>: New.
473 2018-05-08 Alan Modra <amodra@gmail.com>
475 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
476 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
477 partition opcode space for index lookup.
479 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
481 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
482 <insn_length>: ...with this. Update usage.
483 Remove duplicate call to *info->memory_error_func.
485 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
486 H.J. Lu <hongjiu.lu@intel.com>
488 * i386-dis.c (Gva): New.
489 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
490 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
491 (prefix_table): New instructions (see prefix above).
492 (mod_table): New instructions (see prefix above).
493 (OP_G): Handle va_mode.
494 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
496 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
497 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
498 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
499 * i386-opc.tbl: Add movidir{i,64b}.
500 * i386-init.h: Regenerated.
501 * i386-tbl.h: Likewise.
503 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
505 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
507 * i386-opc.h (AddrPrefixOp0): Renamed to ...
508 (AddrPrefixOpReg): This.
509 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
510 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
512 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
514 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
515 (vle_num_opcodes): Likewise.
516 (spe2_num_opcodes): Likewise.
517 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
519 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
520 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
523 2018-05-01 Tamar Christina <tamar.christina@arm.com>
525 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
527 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
529 Makefile.am: Added nfp-dis.c.
530 configure.ac: Added bfd_nfp_arch.
531 disassemble.h: Added print_insn_nfp prototype.
532 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
533 nfp-dis.c: New, for NFP support.
534 po/POTFILES.in: Added nfp-dis.c to the list.
535 Makefile.in: Regenerate.
536 configure: Regenerate.
538 2018-04-26 Jan Beulich <jbeulich@suse.com>
540 * i386-opc.tbl: Fold various non-memory operand AVX512VL
541 templates into their base ones.
542 * i386-tlb.h: Re-generate.
544 2018-04-26 Jan Beulich <jbeulich@suse.com>
546 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
547 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
548 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
549 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
550 * i386-init.h: Re-generate.
552 2018-04-26 Jan Beulich <jbeulich@suse.com>
554 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
555 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
556 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
557 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
559 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
561 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
563 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
564 cpuregzmm, and cpuregmask.
565 * i386-init.h: Re-generate.
566 * i386-tbl.h: Re-generate.
568 2018-04-26 Jan Beulich <jbeulich@suse.com>
570 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
571 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
572 * i386-init.h: Re-generate.
574 2018-04-26 Jan Beulich <jbeulich@suse.com>
576 * i386-gen.c (VexImmExt): Delete.
577 * i386-opc.h (VexImmExt, veximmext): Delete.
578 * i386-opc.tbl: Drop all VexImmExt uses.
579 * i386-tlb.h: Re-generate.
581 2018-04-25 Jan Beulich <jbeulich@suse.com>
583 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
585 * i386-tlb.h: Re-generate.
587 2018-04-25 Tamar Christina <tamar.christina@arm.com>
589 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
591 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
593 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
595 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
596 (cpu_flags): Add CpuCLDEMOTE.
597 * i386-init.h: Regenerate.
598 * i386-opc.h (enum): Add CpuCLDEMOTE,
599 (i386_cpu_flags): Add cpucldemote.
600 * i386-opc.tbl: Add cldemote.
601 * i386-tbl.h: Regenerate.
603 2018-04-16 Alan Modra <amodra@gmail.com>
605 * Makefile.am: Remove sh5 and sh64 support.
606 * configure.ac: Likewise.
607 * disassemble.c: Likewise.
608 * disassemble.h: Likewise.
609 * sh-dis.c: Likewise.
610 * sh64-dis.c: Delete.
611 * sh64-opc.c: Delete.
612 * sh64-opc.h: Delete.
613 * Makefile.in: Regenerate.
614 * configure: Regenerate.
615 * po/POTFILES.in: Regenerate.
617 2018-04-16 Alan Modra <amodra@gmail.com>
619 * Makefile.am: Remove w65 support.
620 * configure.ac: Likewise.
621 * disassemble.c: Likewise.
622 * disassemble.h: Likewise.
625 * Makefile.in: Regenerate.
626 * configure: Regenerate.
627 * po/POTFILES.in: Regenerate.
629 2018-04-16 Alan Modra <amodra@gmail.com>
631 * configure.ac: Remove we32k support.
632 * configure: Regenerate.
634 2018-04-16 Alan Modra <amodra@gmail.com>
636 * Makefile.am: Remove m88k support.
637 * configure.ac: Likewise.
638 * disassemble.c: Likewise.
639 * disassemble.h: Likewise.
640 * m88k-dis.c: Delete.
641 * Makefile.in: Regenerate.
642 * configure: Regenerate.
643 * po/POTFILES.in: Regenerate.
645 2018-04-16 Alan Modra <amodra@gmail.com>
647 * Makefile.am: Remove i370 support.
648 * configure.ac: Likewise.
649 * disassemble.c: Likewise.
650 * disassemble.h: Likewise.
651 * i370-dis.c: Delete.
652 * i370-opc.c: Delete.
653 * Makefile.in: Regenerate.
654 * configure: Regenerate.
655 * po/POTFILES.in: Regenerate.
657 2018-04-16 Alan Modra <amodra@gmail.com>
659 * Makefile.am: Remove h8500 support.
660 * configure.ac: Likewise.
661 * disassemble.c: Likewise.
662 * disassemble.h: Likewise.
663 * h8500-dis.c: Delete.
664 * h8500-opc.h: Delete.
665 * Makefile.in: Regenerate.
666 * configure: Regenerate.
667 * po/POTFILES.in: Regenerate.
669 2018-04-16 Alan Modra <amodra@gmail.com>
671 * configure.ac: Remove tahoe support.
672 * configure: Regenerate.
674 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
676 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
678 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
680 * i386-tbl.h: Regenerated.
682 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
684 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
685 PREFIX_MOD_1_0FAE_REG_6.
687 (OP_E_register): Use va_mode.
688 * i386-dis-evex.h (prefix_table):
689 New instructions (see prefixes above).
690 * i386-gen.c (cpu_flag_init): Add WAITPKG.
691 (cpu_flags): Likewise.
692 * i386-opc.h (enum): Likewise.
693 (i386_cpu_flags): Likewise.
694 * i386-opc.tbl: Add umonitor, umwait, tpause.
695 * i386-init.h: Regenerate.
696 * i386-tbl.h: Likewise.
698 2018-04-11 Alan Modra <amodra@gmail.com>
700 * opcodes/i860-dis.c: Delete.
701 * opcodes/i960-dis.c: Delete.
702 * Makefile.am: Remove i860 and i960 support.
703 * configure.ac: Likewise.
704 * disassemble.c: Likewise.
705 * disassemble.h: Likewise.
706 * Makefile.in: Regenerate.
707 * configure: Regenerate.
708 * po/POTFILES.in: Regenerate.
710 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
713 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
715 (print_insn): Clear vex instead of vex.evex.
717 2018-04-04 Nick Clifton <nickc@redhat.com>
719 * po/es.po: Updated Spanish translation.
721 2018-03-28 Jan Beulich <jbeulich@suse.com>
723 * i386-gen.c (opcode_modifiers): Delete VecESize.
724 * i386-opc.h (VecESize): Delete.
725 (struct i386_opcode_modifier): Delete vecesize.
726 * i386-opc.tbl: Drop VecESize.
727 * i386-tlb.h: Re-generate.
729 2018-03-28 Jan Beulich <jbeulich@suse.com>
731 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
732 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
733 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
734 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
735 * i386-tlb.h: Re-generate.
737 2018-03-28 Jan Beulich <jbeulich@suse.com>
739 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
741 * i386-tlb.h: Re-generate.
743 2018-03-28 Jan Beulich <jbeulich@suse.com>
745 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
746 (vex_len_table): Drop Y for vcvt*2si.
747 (putop): Replace plain 'Y' handling by abort().
749 2018-03-28 Nick Clifton <nickc@redhat.com>
752 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
753 instructions with only a base address register.
754 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
755 handle AARHC64_OPND_SVE_ADDR_R.
756 (aarch64_print_operand): Likewise.
757 * aarch64-asm-2.c: Regenerate.
758 * aarch64_dis-2.c: Regenerate.
759 * aarch64-opc-2.c: Regenerate.
761 2018-03-22 Jan Beulich <jbeulich@suse.com>
763 * i386-opc.tbl: Drop VecESize from register only insn forms and
764 memory forms not allowing broadcast.
765 * i386-tlb.h: Re-generate.
767 2018-03-22 Jan Beulich <jbeulich@suse.com>
769 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
770 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
771 sha256*): Drop Disp<N>.
773 2018-03-22 Jan Beulich <jbeulich@suse.com>
775 * i386-dis.c (EbndS, bnd_swap_mode): New.
776 (prefix_table): Use EbndS.
777 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
778 * i386-opc.tbl (bndmov): Move misplaced Load.
779 * i386-tlb.h: Re-generate.
781 2018-03-22 Jan Beulich <jbeulich@suse.com>
783 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
784 templates allowing memory operands and folded ones for register
786 * i386-tlb.h: Re-generate.
788 2018-03-22 Jan Beulich <jbeulich@suse.com>
790 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
791 256-bit templates. Drop redundant leftover Disp<N>.
792 * i386-tlb.h: Re-generate.
794 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
796 * riscv-opc.c (riscv_insn_types): New.
798 2018-03-13 Nick Clifton <nickc@redhat.com>
800 * po/pt_BR.po: Updated Brazilian Portuguese translation.
802 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
804 * i386-opc.tbl: Add Optimize to clr.
805 * i386-tbl.h: Regenerated.
807 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
809 * i386-gen.c (opcode_modifiers): Remove OldGcc.
810 * i386-opc.h (OldGcc): Removed.
811 (i386_opcode_modifier): Remove oldgcc.
812 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
813 instructions for old (<= 2.8.1) versions of gcc.
814 * i386-tbl.h: Regenerated.
816 2018-03-08 Jan Beulich <jbeulich@suse.com>
818 * i386-opc.h (EVEXDYN): New.
819 * i386-opc.tbl: Fold various AVX512VL templates.
820 * i386-tlb.h: Re-generate.
822 2018-03-08 Jan Beulich <jbeulich@suse.com>
824 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
825 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
826 vpexpandd, vpexpandq): Fold AFX512VF templates.
827 * i386-tlb.h: Re-generate.
829 2018-03-08 Jan Beulich <jbeulich@suse.com>
831 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
832 Fold 128- and 256-bit VEX-encoded templates.
833 * i386-tlb.h: Re-generate.
835 2018-03-08 Jan Beulich <jbeulich@suse.com>
837 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
838 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
839 vpexpandd, vpexpandq): Fold AVX512F templates.
840 * i386-tlb.h: Re-generate.
842 2018-03-08 Jan Beulich <jbeulich@suse.com>
844 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
845 64-bit templates. Drop Disp<N>.
846 * i386-tlb.h: Re-generate.
848 2018-03-08 Jan Beulich <jbeulich@suse.com>
850 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
851 and 256-bit templates.
852 * i386-tlb.h: Re-generate.
854 2018-03-08 Jan Beulich <jbeulich@suse.com>
856 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
857 * i386-tlb.h: Re-generate.
859 2018-03-08 Jan Beulich <jbeulich@suse.com>
861 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
863 * i386-tlb.h: Re-generate.
865 2018-03-08 Jan Beulich <jbeulich@suse.com>
867 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
868 * i386-tlb.h: Re-generate.
870 2018-03-08 Jan Beulich <jbeulich@suse.com>
872 * i386-gen.c (opcode_modifiers): Delete FloatD.
873 * i386-opc.h (FloatD): Delete.
874 (struct i386_opcode_modifier): Delete floatd.
875 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
877 * i386-tlb.h: Re-generate.
879 2018-03-08 Jan Beulich <jbeulich@suse.com>
881 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
883 2018-03-08 Jan Beulich <jbeulich@suse.com>
885 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
886 * i386-tlb.h: Re-generate.
888 2018-03-08 Jan Beulich <jbeulich@suse.com>
890 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
892 * i386-tlb.h: Re-generate.
894 2018-03-07 Alan Modra <amodra@gmail.com>
896 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
898 * disassemble.h (print_insn_rs6000): Delete.
899 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
900 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
901 (print_insn_rs6000): Delete.
903 2018-03-03 Alan Modra <amodra@gmail.com>
905 * sysdep.h (opcodes_error_handler): Define.
906 (_bfd_error_handler): Declare.
907 * Makefile.am: Remove stray #.
908 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
910 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
911 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
912 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
913 opcodes_error_handler to print errors. Standardize error messages.
914 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
915 and include opintl.h.
916 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
917 * i386-gen.c: Standardize error messages.
918 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
919 * Makefile.in: Regenerate.
920 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
921 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
922 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
923 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
924 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
925 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
926 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
927 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
928 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
929 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
930 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
931 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
932 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
934 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
936 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
937 vpsub[bwdq] instructions.
938 * i386-tbl.h: Regenerated.
940 2018-03-01 Alan Modra <amodra@gmail.com>
942 * configure.ac (ALL_LINGUAS): Sort.
943 * configure: Regenerate.
945 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
947 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
948 macro by assignements.
950 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
953 * i386-gen.c (opcode_modifiers): Add Optimize.
954 * i386-opc.h (Optimize): New enum.
955 (i386_opcode_modifier): Add optimize.
956 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
957 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
958 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
959 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
960 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
962 * i386-tbl.h: Regenerated.
964 2018-02-26 Alan Modra <amodra@gmail.com>
966 * crx-dis.c (getregliststring): Allocate a large enough buffer
967 to silence false positive gcc8 warning.
969 2018-02-22 Shea Levy <shea@shealevy.com>
971 * disassemble.c (ARCH_riscv): Define if ARCH_all.
973 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
975 * i386-opc.tbl: Add {rex},
976 * i386-tbl.h: Regenerated.
978 2018-02-20 Maciej W. Rozycki <macro@mips.com>
980 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
981 (mips16_opcodes): Replace `M' with `m' for "restore".
983 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
985 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
987 2018-02-13 Maciej W. Rozycki <macro@mips.com>
989 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
990 variable to `function_index'.
992 2018-02-13 Nick Clifton <nickc@redhat.com>
995 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
996 about truncation of printing.
998 2018-02-12 Henry Wong <henry@stuffedcow.net>
1000 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1002 2018-02-05 Nick Clifton <nickc@redhat.com>
1004 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1006 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1008 * i386-dis.c (enum): Add pconfig.
1009 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1010 (cpu_flags): Add CpuPCONFIG.
1011 * i386-opc.h (enum): Add CpuPCONFIG.
1012 (i386_cpu_flags): Add cpupconfig.
1013 * i386-opc.tbl: Add PCONFIG instruction.
1014 * i386-init.h: Regenerate.
1015 * i386-tbl.h: Likewise.
1017 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1019 * i386-dis.c (enum): Add PREFIX_0F09.
1020 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1021 (cpu_flags): Add CpuWBNOINVD.
1022 * i386-opc.h (enum): Add CpuWBNOINVD.
1023 (i386_cpu_flags): Add cpuwbnoinvd.
1024 * i386-opc.tbl: Add WBNOINVD instruction.
1025 * i386-init.h: Regenerate.
1026 * i386-tbl.h: Likewise.
1028 2018-01-17 Jim Wilson <jimw@sifive.com>
1030 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1032 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1034 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1035 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1036 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1037 (cpu_flags): Add CpuIBT, CpuSHSTK.
1038 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1039 (i386_cpu_flags): Add cpuibt, cpushstk.
1040 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1041 * i386-init.h: Regenerate.
1042 * i386-tbl.h: Likewise.
1044 2018-01-16 Nick Clifton <nickc@redhat.com>
1046 * po/pt_BR.po: Updated Brazilian Portugese translation.
1047 * po/de.po: Updated German translation.
1049 2018-01-15 Jim Wilson <jimw@sifive.com>
1051 * riscv-opc.c (match_c_nop): New.
1052 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1054 2018-01-15 Nick Clifton <nickc@redhat.com>
1056 * po/uk.po: Updated Ukranian translation.
1058 2018-01-13 Nick Clifton <nickc@redhat.com>
1060 * po/opcodes.pot: Regenerated.
1062 2018-01-13 Nick Clifton <nickc@redhat.com>
1064 * configure: Regenerate.
1066 2018-01-13 Nick Clifton <nickc@redhat.com>
1068 2.30 branch created.
1070 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1072 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1073 * i386-tbl.h: Regenerate.
1075 2018-01-10 Jan Beulich <jbeulich@suse.com>
1077 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1078 * i386-tbl.h: Re-generate.
1080 2018-01-10 Jan Beulich <jbeulich@suse.com>
1082 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1083 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1084 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1085 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1086 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1087 Disp8MemShift of AVX512VL forms.
1088 * i386-tbl.h: Re-generate.
1090 2018-01-09 Jim Wilson <jimw@sifive.com>
1092 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1093 then the hi_addr value is zero.
1095 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1097 * arm-dis.c (arm_opcodes): Add csdb.
1098 (thumb32_opcodes): Add csdb.
1100 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1102 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1103 * aarch64-asm-2.c: Regenerate.
1104 * aarch64-dis-2.c: Regenerate.
1105 * aarch64-opc-2.c: Regenerate.
1107 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1110 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1111 Remove AVX512 vmovd with 64-bit operands.
1112 * i386-tbl.h: Regenerated.
1114 2018-01-05 Jim Wilson <jimw@sifive.com>
1116 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1119 2018-01-03 Alan Modra <amodra@gmail.com>
1121 Update year range in copyright notice of all files.
1123 2018-01-02 Jan Beulich <jbeulich@suse.com>
1125 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1126 and OPERAND_TYPE_REGZMM entries.
1128 For older changes see ChangeLog-2017
1130 Copyright (C) 2018 Free Software Foundation, Inc.
1132 Copying and distribution of this file, with or without modification,
1133 are permitted in any medium without royalty provided the copyright
1134 notice and this notice are preserved.
1140 version-control: never