1 2013-04-08 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
4 * i386-tbl.h: Re-generate.
6 2013-04-06 David S. Miller <davem@davemloft.net>
8 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
9 of an opcode, prefer the one with F_PREFERRED set.
10 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
11 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
12 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
13 mark existing mnenomics as aliases. Add "cc" suffix to edge
14 instructions generating condition codes, mark existing mnenomics
15 as aliases. Add "fp" prefix to VIS compare instructions, mark
16 existing mnenomics as aliases.
18 2013-04-03 Nick Clifton <nickc@redhat.com>
20 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
21 destination address by subtracting the operand from the current
23 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
24 a positive value in the insn.
25 (extract_u16_loop): Do not negate the returned value.
26 (D16_LOOP): Add V850_INVERSE_PCREL flag.
28 (ceilf.sw): Remove duplicate entry.
35 (maddf.s): Restrict to E3V5 architectures.
40 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
42 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
44 (print_insn): Pass sizeflag to get_sib.
46 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
49 * tic6x-dis.c: Add support for displaying 16-bit insns.
51 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
54 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
55 individual msb and lsb halves in src1 & src2 fields. Discard the
56 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
57 follow what Ti SDK does in that case as any value in the src1
58 field yields the same output with SDK disassembler.
60 2013-03-12 Michael Eager <eager@eagercon.com>
62 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
64 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
66 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
68 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
70 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
72 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
74 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
76 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
78 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
79 (thumb32_opcodes): Likewise.
80 (print_insn_thumb32): Handle 'S' control char.
82 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
84 * lm32-desc.c: Regenerate.
86 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
88 * i386-reg.tbl (riz): Add RegRex64.
89 * i386-tbl.h: Regenerated.
91 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
93 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
94 (aarch64_feature_crc): New static.
96 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
97 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
98 * aarch64-asm-2.c: Re-generate.
99 * aarch64-dis-2.c: Ditto.
100 * aarch64-opc-2.c: Ditto.
102 2013-02-27 Alan Modra <amodra@gmail.com>
104 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
105 * rl78-decode.c: Regenerate.
107 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
109 * rl78-decode.opc: Fix encoding of DIVWU insn.
110 * rl78-decode.c: Regenerate.
112 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
115 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
117 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
118 (cpu_flags): Add CpuSMAP.
120 * i386-opc.h (CpuSMAP): New.
121 (i386_cpu_flags): Add cpusmap.
123 * i386-opc.tbl: Add clac and stac.
125 * i386-init.h: Regenerated.
126 * i386-tbl.h: Likewise.
128 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
130 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
131 which also makes the disassembler output be in little
132 endian like it should be.
134 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
136 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
138 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
140 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
142 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
143 section disassembled.
145 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
147 * arm-dis.c: Update strht pattern.
149 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
151 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
152 single-float. Disable ll, lld, sc and scd for EE. Disable the
153 trunc.w.s macro for EE.
155 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
156 Andrew Jenner <andrew@codesourcery.com>
158 Based on patches from Altera Corporation.
160 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
162 * Makefile.in: Regenerated.
163 * configure.in: Add case for bfd_nios2_arch.
164 * configure: Regenerated.
165 * disassemble.c (ARCH_nios2): Define.
166 (disassembler): Add case for bfd_arch_nios2.
167 * nios2-dis.c: New file.
168 * nios2-opc.c: New file.
170 2013-02-04 Alan Modra <amodra@gmail.com>
172 * po/POTFILES.in: Regenerate.
173 * rl78-decode.c: Regenerate.
174 * rx-decode.c: Regenerate.
176 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
178 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
179 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
180 * aarch64-asm.c (convert_xtl_to_shll): New function.
181 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
182 calling convert_xtl_to_shll.
183 * aarch64-dis.c (convert_shll_to_xtl): New function.
184 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
185 calling convert_shll_to_xtl.
186 * aarch64-gen.c: Update copyright year.
187 * aarch64-asm-2.c: Re-generate.
188 * aarch64-dis-2.c: Re-generate.
189 * aarch64-opc-2.c: Re-generate.
191 2013-01-24 Nick Clifton <nickc@redhat.com>
193 * v850-dis.c: Add support for e3v5 architecture.
194 * v850-opc.c: Likewise.
196 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
198 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
199 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
200 * aarch64-opc.c (operand_general_constraint_met_p): For
201 AARCH64_MOD_LSL, move the range check on the shift amount before the
202 alignment check; change to call set_sft_amount_out_of_range_error
203 instead of set_imm_out_of_range_error.
204 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
205 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
206 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
209 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
211 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
213 * i386-init.h: Regenerated.
214 * i386-tbl.h: Likewise.
216 2013-01-15 Nick Clifton <nickc@redhat.com>
218 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
220 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
222 2013-01-14 Will Newton <will.newton@imgtec.com>
224 * metag-dis.c (REG_WIDTH): Increase to 64.
226 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
228 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
229 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
230 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
232 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
233 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
234 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
235 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
237 2013-01-10 Will Newton <will.newton@imgtec.com>
239 * Makefile.am: Add Meta.
240 * configure.in: Add Meta.
241 * disassemble.c: Add Meta support.
242 * metag-dis.c: New file.
243 * Makefile.in: Regenerate.
244 * configure: Regenerate.
246 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
248 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
249 (match_opcode): Rename to cr16_match_opcode.
251 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
253 * mips-dis.c: Add names for CP0 registers of r5900.
254 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
255 instructions sq and lq.
256 Add support for MIPS r5900 CPU.
257 Add support for 128 bit MMI (Multimedia Instructions).
258 Add support for EE instructions (Emotion Engine).
259 Disable unsupported floating point instructions (64 bit and
260 undefined compare operations).
261 Enable instructions of MIPS ISA IV which are supported by r5900.
262 Disable 64 bit co processor instructions.
263 Disable 64 bit multiplication and division instructions.
264 Disable instructions for co-processor 2 and 3, because these are
265 not supported (preparation for later VU0 support (Vector Unit)).
266 Disable cvt.w.s because this behaves like trunc.w.s and the
267 correct execution can't be ensured on r5900.
268 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
269 will confuse less developers and compilers.
271 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
273 * aarch64-opc.c (aarch64_print_operand): Change to print
274 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
276 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
277 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
280 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
282 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
283 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
285 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
287 * i386-gen.c (process_copyright): Update copyright year to 2013.
289 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
291 * cr16-dis.c (match_opcode,make_instruction): Remove static
293 (dwordU,wordU): Moved typedefs to opcode/cr16.h
294 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
296 For older changes see ChangeLog-2012
298 Copyright (C) 2013 Free Software Foundation, Inc.
300 Copying and distribution of this file, with or without modification,
301 are permitted in any medium without royalty provided the copyright
302 notice and this notice are preserved.
308 version-control: never