1 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
3 * mips-dis.c (mips_convert_abiflags_ases): New function.
4 (set_default_mips_dis_options): Also infer ASE flags from ELF
7 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
9 * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
10 header flag interpretation code.
12 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
14 * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
15 `pinfo2' with SP-relative "sd" entries.
17 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
19 * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
22 2016-12-13 Renlin Li <renlin.li@arm.com>
24 * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
26 (operand_general_constraint_met_p): Remove case for CP_REG.
27 (aarch64_print_operand): Print CRn, CRm operand using imm field.
28 * aarch64-tbl.h (QL_SYS): Use CR qualifier.
30 (aarch64_opcode_table): Change CRn, CRm operand class and type.
31 * aarch64-opc-2.c : Regenerate.
32 * aarch64-asm-2.c : Likewise.
33 * aarch64-dis-2.c : Likewise.
35 2016-12-12 Yao Qi <yao.qi@linaro.org>
37 * rx-dis.c: Include <setjmp.h>
38 (struct private): New.
39 (rx_get_byte): Check return value of read_memory_func, and
40 call memory_error_func and OPCODES_SIGLONGJMP on error.
41 (print_insn_rx): Call OPCODES_SIGSETJMP.
43 2016-12-12 Yao Qi <yao.qi@linaro.org>
45 * rl78-dis.c: Include <setjmp.h>.
46 (struct private): New.
47 (rl78_get_byte): Check return value of read_memory_func, and
48 call memory_error_func and OPCODES_SIGLONGJMP on error.
49 (print_insn_rl78_common): Call OPCODES_SIGJMP.
51 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
53 * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
55 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
57 * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
60 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
62 * mips-dis.c (print_insn_mips16): Use a tab rather than a space
63 to separate `extend' and its uninterpreted argument output.
64 Separate hexadecimal halves of undecoded extended instructions
67 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
69 * mips-dis.c (print_mips16_insn_arg): Remove extraneous
70 indentation space across.
72 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
74 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
75 adjustment for PC-relative operations following MIPS16e compact
76 jumps or undefined RR/J(AL)R(C) encodings.
78 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
80 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
81 variable to `reglane_index'.
83 2016-12-08 Luis Machado <lgustavo@codesourcery.com>
85 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
87 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
89 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
91 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
93 * mips16-opc.c (mips16_opcodes): Update comment naming structure
96 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
98 * mips-dis.c (print_mips_disassembler_options): Reformat output.
100 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
102 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
103 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
105 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
107 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
109 2016-12-01 Nick Clifton <nickc@redhat.com>
112 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
115 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
117 * arc-opc.c (insert_ra_chk): New function.
118 (insert_rb_chk): Likewise.
119 (insert_rad): Update text error message.
120 (insert_rcd): Likewise.
121 (insert_rhv2): Likewise.
122 (insert_r0): Likewise.
123 (insert_r1): Likewise.
124 (insert_r2): Likewise.
125 (insert_r3): Likewise.
126 (insert_sp): Likewise.
127 (insert_gp): Likewise.
128 (insert_pcl): Likewise.
129 (insert_blink): Likewise.
130 (insert_ilink1): Likewise.
131 (insert_ilink2): Likewise.
132 (insert_ras): Likewise.
133 (insert_rbs): Likewise.
134 (insert_rcs): Likewise.
135 (insert_simm3s): Likewise.
136 (insert_rrange): Likewise.
137 (insert_fpel): Likewise.
138 (insert_blinkel): Likewise.
139 (insert_pcel): Likewise.
140 (insert_nps_3bit_dst): Likewise.
141 (insert_nps_3bit_dst_short): Likewise.
142 (insert_nps_3bit_src2_short): Likewise.
143 (insert_nps_bitop_size_2b): Likewise.
144 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
149 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
150 * arc-tbl.h (div, divu): All instructions are DIVREM class.
151 Change first insn argument to check for LP_COUNT usage.
153 (ld, ldd): All instructions are LOAD class. Change first insn
154 argument to check for LP_COUNT usage.
155 (st, std): All instructions are STORE class.
156 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
157 Change first insn argument to check for LP_COUNT usage.
158 (mov): All instructions are MOVE class. Change first insn
159 argument to check for LP_COUNT usage.
161 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
163 * arc-dis.c (is_compatible_p): Remove function.
164 (skip_this_opcode): Don't add any decoding class to decode list.
166 (find_format_from_table): Go through all opcodes, and warn if we
167 use a guessed mnemonic.
169 2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
170 Amit Pawar <amit.pawar@amd.com>
173 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
176 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
178 * configure: Regenerate.
180 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
182 * sparc-opc.c (HWS_V8): Definition moved from
183 gas/config/tc-sparc.c.
193 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
196 2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
198 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
201 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
203 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
204 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
205 (aarch64_opcode_table): Add fcmla and fcadd.
206 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
207 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
208 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
209 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
210 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
211 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
212 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
213 (operand_general_constraint_met_p): Rotate and index range check.
214 (aarch64_print_operand): Handle rotate operand.
215 * aarch64-asm-2.c: Regenerate.
216 * aarch64-dis-2.c: Likewise.
217 * aarch64-opc-2.c: Likewise.
219 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
221 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
222 * aarch64-asm-2.c: Regenerate.
223 * aarch64-dis-2.c: Regenerate.
224 * aarch64-opc-2.c: Regenerate.
226 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
228 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
229 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
230 * aarch64-asm-2.c: Regenerate.
231 * aarch64-dis-2.c: Regenerate.
232 * aarch64-opc-2.c: Regenerate.
234 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
236 * aarch64-tbl.h (QL_X1NIL): New.
237 (arch64_opcode_table): Add ldraa, ldrab.
238 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
239 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
240 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
241 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
242 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
243 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
244 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
245 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
246 (aarch64_print_operand): Likewise.
247 * aarch64-asm-2.c: Regenerate.
248 * aarch64-dis-2.c: Regenerate.
249 * aarch64-opc-2.c: Regenerate.
251 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
253 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
254 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
255 * aarch64-asm-2.c: Regenerate.
256 * aarch64-dis-2.c: Regenerate.
257 * aarch64-opc-2.c: Regenerate.
259 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
261 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
262 (AARCH64_OPERANDS): Add Rm_SP.
263 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
264 * aarch64-asm-2.c: Regenerate.
265 * aarch64-dis-2.c: Regenerate.
266 * aarch64-opc-2.c: Regenerate.
268 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
270 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
271 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
272 autdzb, xpaci, xpacd.
273 * aarch64-asm-2.c: Regenerate.
274 * aarch64-dis-2.c: Regenerate.
275 * aarch64-opc-2.c: Regenerate.
277 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
279 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
280 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
281 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
282 (aarch64_sys_reg_supported_p): Add feature test for new registers.
284 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
286 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
287 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
288 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
290 * aarch64-asm-2.c: Regenerate.
291 * aarch64-dis-2.c: Regenerate.
293 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
295 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
297 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
300 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
301 * i386-dis.c (EdqwS): Removed.
302 (dqw_swap_mode): Likewise.
303 (intel_operand_size): Don't check dqw_swap_mode.
304 (OP_E_register): Likewise.
305 (OP_E_memory): Likewise.
308 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
309 * i386-tbl.h: Regerated.
311 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
313 * i386-opc.tbl: Merge AVX512F vmovq.
314 * i386-tbl.h: Regerated.
316 2016-11-08 H.J. Lu <hongjiu.lu@intel.com>
319 * i386-dis.c (THREE_BYTE_0F7A): Removed.
320 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
321 (three_byte_table): Remove THREE_BYTE_0F7A.
323 2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
326 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
327 (FGRPd9_4): Replace 1 with 2.
328 (FGRPd9_5): Replace 2 with 3.
329 (FGRPd9_6): Replace 3 with 4.
330 (FGRPd9_7): Replace 4 with 5.
331 (FGRPda_5): Replace 5 with 6.
332 (FGRPdb_4): Replace 6 with 7.
333 (FGRPde_3): Replace 7 with 8.
334 (FGRPdf_4): Replace 8 with 9.
335 (fgrps): Add an entry for Bad_Opcode.
337 2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
339 * arc-opc.c (arc_flag_operands): Add F_DI14.
340 (arc_flag_classes): Add C_DI14.
341 * arc-nps400-tbl.h: Add new exc instructions.
343 2016-11-03 Graham Markall <graham.markall@embecosm.com>
345 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
347 * arc-nps-400-tbl.h: Add dcmac instruction.
348 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
349 (insert_nps_rbdouble_64): Added.
350 (extract_nps_rbdouble_64): Added.
351 (insert_nps_proto_size): Added.
352 (extract_nps_proto_size): Added.
354 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
356 * arc-dis.c (struct arc_operand_iterator): Remove all fields
357 relating to long instruction processing, add new limm field.
358 (OPCODE): Rename to...
359 (OPCODE_32BIT_INSN): ...this.
361 (skip_this_opcode): Handle different instruction lengths, update
363 (special_flag_p): Update parameter type.
364 (find_format_from_table): Update for more instruction lengths.
365 (find_format_long_instructions): Delete.
366 (find_format): Update for more instruction lengths.
367 (arc_insn_length): Likewise.
368 (extract_operand_value): Update for more instruction lengths.
369 (operand_iterator_next): Remove code relating to long
371 (arc_opcode_to_insn_type): New function.
372 (print_insn_arc):Update for more instructions lengths.
373 * arc-ext.c (extInstruction_t): Change argument type.
374 * arc-ext.h (extInstruction_t): Change argument type.
375 * arc-fxi.h: Change type unsigned to unsigned long long
376 extensively throughout.
377 * arc-nps400-tbl.h: Add long instructions taken from
378 arc_long_opcodes table in arc-opc.c.
379 * arc-opc.c: Update parameter types on insert/extract handlers.
380 (arc_long_opcodes): Delete.
381 (arc_num_long_opcodes): Delete.
382 (arc_opcode_len): Update for more instruction lengths.
384 2016-11-03 Graham Markall <graham.markall@embecosm.com>
386 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
388 2016-11-03 Graham Markall <graham.markall@embecosm.com>
390 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
392 (find_format_long_instructions): Likewise.
393 * arc-opc.c (arc_opcode_len): New function.
395 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
397 * arc-nps400-tbl.h: Fix some instruction masks.
399 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
401 * i386-dis.c (REG_82): Removed.
402 (X86_64_82_REG_0): Likewise.
403 (X86_64_82_REG_1): Likewise.
404 (X86_64_82_REG_2): Likewise.
405 (X86_64_82_REG_3): Likewise.
406 (X86_64_82_REG_4): Likewise.
407 (X86_64_82_REG_5): Likewise.
408 (X86_64_82_REG_6): Likewise.
409 (X86_64_82_REG_7): Likewise.
411 (dis386): Use X86_64_82 instead of REG_82.
412 (reg_table): Remove REG_82.
413 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
414 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
415 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
418 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
421 * i386-dis.c (REG_82): New.
422 (X86_64_82_REG_0): Likewise.
423 (X86_64_82_REG_1): Likewise.
424 (X86_64_82_REG_2): Likewise.
425 (X86_64_82_REG_3): Likewise.
426 (X86_64_82_REG_4): Likewise.
427 (X86_64_82_REG_5): Likewise.
428 (X86_64_82_REG_6): Likewise.
429 (X86_64_82_REG_7): Likewise.
430 (dis386): Use REG_82.
431 (reg_table): Add REG_82.
432 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
433 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
434 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
436 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
438 * i386-dis.c (REG_82): Renamed to ...
441 (reg_table): Likewise.
443 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
445 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
446 * i386-dis-evex.h (evex_table): Updated.
447 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
448 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
449 (cpu_flags): Add CpuAVX512_4VNNIW.
450 * i386-opc.h (enum): (AVX512_4VNNIW): New.
451 (i386_cpu_flags): Add cpuavx512_4vnniw.
452 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
453 * i386-init.h: Regenerate.
456 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
458 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
459 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
460 * i386-dis-evex.h (evex_table): Updated.
461 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
462 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
463 (cpu_flags): Add CpuAVX512_4FMAPS.
464 (opcode_modifiers): Add ImplicitQuadGroup modifier.
465 * i386-opc.h (AVX512_4FMAP): New.
466 (i386_cpu_flags): Add cpuavx512_4fmaps.
467 (ImplicitQuadGroup): New.
468 (i386_opcode_modifier): Add implicitquadgroup.
469 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
470 * i386-init.h: Regenerate.
473 2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
474 Andrew Waterman <andrew@sifive.com>
476 Add support for RISC-V architecture.
477 * configure.ac: Add entry for bfd_riscv_arch.
478 * configure: Regenerate.
479 * disassemble.c (disassembler): Add support for riscv.
480 (disassembler_usage): Likewise.
481 * riscv-dis.c: New file.
482 * riscv-opc.c: New file.
484 2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
486 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
487 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
488 (rm_table): Update the RM_0FAE_REG_7 entry.
489 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
490 (cpu_flags): Remove CpuPCOMMIT.
491 * i386-opc.h (CpuPCOMMIT): Removed.
492 (i386_cpu_flags): Remove cpupcommit.
493 * i386-opc.tbl: Remove pcommit.
494 * i386-init.h: Regenerated.
495 * i386-tbl.h: Likewise.
497 2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
500 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
501 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
502 32-bit mode. Don't check vex.register_specifier in 32-bit
504 (OP_VEX): Check for invalid mask registers.
506 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
509 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
512 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
515 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
517 2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
519 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
520 local variable to `index_regno'.
522 2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
524 * arc-tbl.h: Removed any "inv.+" instructions from the table.
526 2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
528 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
531 2016-10-11 Jiong Wang <jiong.wang@arm.com>
534 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
536 2016-10-07 Jiong Wang <jiong.wang@arm.com>
539 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
542 2016-10-07 Alan Modra <amodra@gmail.com>
544 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
546 2016-10-06 Alan Modra <amodra@gmail.com>
548 * aarch64-opc.c: Spell fall through comments consistently.
549 * i386-dis.c: Likewise.
550 * aarch64-dis.c: Add missing fall through comments.
551 * aarch64-opc.c: Likewise.
552 * arc-dis.c: Likewise.
553 * arm-dis.c: Likewise.
554 * i386-dis.c: Likewise.
555 * m68k-dis.c: Likewise.
556 * mep-asm.c: Likewise.
557 * ns32k-dis.c: Likewise.
558 * sh-dis.c: Likewise.
559 * tic4x-dis.c: Likewise.
560 * tic6x-dis.c: Likewise.
561 * vax-dis.c: Likewise.
563 2016-10-06 Alan Modra <amodra@gmail.com>
565 * arc-ext.c (create_map): Add missing break.
566 * msp430-decode.opc (encode_as): Likewise.
567 * msp430-decode.c: Regenerate.
569 2016-10-06 Alan Modra <amodra@gmail.com>
571 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
572 * crx-dis.c (print_insn_crx): Likewise.
574 2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
577 * i386-dis.c (putop): Don't assign alt twice.
579 2016-09-29 Jiong Wang <jiong.wang@arm.com>
582 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
584 2016-09-29 Alan Modra <amodra@gmail.com>
586 * ppc-opc.c (L): Make compulsory.
587 (LOPT): New, optional form of L.
588 (HTM_R): Define as LOPT.
590 (L32OPT): New, optional for 32-bit L.
591 (L2OPT): New, 2-bit L for dcbf.
594 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
595 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
597 <tlbiel, tlbie>: Use LOPT.
598 <wclr, wclrall>: Use L2.
600 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
602 * Makefile.in: Regenerate.
603 * configure: Likewise.
605 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
607 * arc-ext-tbl.h (EXTINSN2OPF): Define.
608 (EXTINSN2OP): Use EXTINSN2OPF.
609 (bspeekm, bspop, modapp): New extension instructions.
610 * arc-opc.c (F_DNZ_ND): Define.
615 * arc-tbl.h (dbnz): New instruction.
616 (prealloc): Allow it for ARC EM.
619 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
621 * aarch64-opc.c (print_immediate_offset_address): Print spaces
622 after commas in addresses.
623 (aarch64_print_operand): Likewise.
625 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
627 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
628 rather than "should be" or "expected to be" in error messages.
630 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
632 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
633 (print_mnemonic_name): ...here.
634 (print_comment): New function.
635 (print_aarch64_insn): Call it.
636 * aarch64-opc.c (aarch64_conds): Add SVE names.
637 (aarch64_print_operand): Print alternative condition names in
640 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
642 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
643 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
644 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
645 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
646 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
647 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
648 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
649 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
650 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
651 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
652 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
653 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
654 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
655 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
656 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
657 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
658 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
659 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
660 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
661 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
662 (OP_SVE_XWU, OP_SVE_XXU): New macros.
663 (aarch64_feature_sve): New variable.
665 (_SVE_INSN): Likewise.
666 (aarch64_opcode_table): Add SVE instructions.
667 * aarch64-opc.h (extract_fields): Declare.
668 * aarch64-opc-2.c: Regenerate.
669 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
670 * aarch64-asm-2.c: Regenerate.
671 * aarch64-dis.c (extract_fields): Make global.
672 (do_misc_decoding): Handle the new SVE aarch64_ops.
673 * aarch64-dis-2.c: Regenerate.
675 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
677 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
678 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
680 * aarch64-opc.c (fields): Add corresponding entries.
681 * aarch64-asm.c (aarch64_get_variant): New function.
682 (aarch64_encode_variant_using_iclass): Likewise.
683 (aarch64_opcode_encode): Call it.
684 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
685 (aarch64_opcode_decode): Call it.
687 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
689 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
690 and FP register operands.
691 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
692 (FLD_SVE_Vn): New aarch64_field_kinds.
693 * aarch64-opc.c (fields): Add corresponding entries.
694 (aarch64_print_operand): Handle the new SVE core and FP register
696 * aarch64-opc-2.c: Regenerate.
697 * aarch64-asm-2.c: Likewise.
698 * aarch64-dis-2.c: Likewise.
700 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
702 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
704 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
705 * aarch64-opc.c (fields): Add corresponding entry.
706 (operand_general_constraint_met_p): Handle the new SVE FP immediate
708 (aarch64_print_operand): Likewise.
709 * aarch64-opc-2.c: Regenerate.
710 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
711 (ins_sve_float_zero_one): New inserters.
712 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
713 (aarch64_ins_sve_float_half_two): Likewise.
714 (aarch64_ins_sve_float_zero_one): Likewise.
715 * aarch64-asm-2.c: Regenerate.
716 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
717 (ext_sve_float_zero_one): New extractors.
718 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
719 (aarch64_ext_sve_float_half_two): Likewise.
720 (aarch64_ext_sve_float_zero_one): Likewise.
721 * aarch64-dis-2.c: Regenerate.
723 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
725 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
726 integer immediate operands.
727 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
728 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
729 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
730 * aarch64-opc.c (fields): Add corresponding entries.
731 (operand_general_constraint_met_p): Handle the new SVE integer
733 (aarch64_print_operand): Likewise.
734 (aarch64_sve_dupm_mov_immediate_p): New function.
735 * aarch64-opc-2.c: Regenerate.
736 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
737 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
738 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
739 (aarch64_ins_limm): ...here.
740 (aarch64_ins_inv_limm): New function.
741 (aarch64_ins_sve_aimm): Likewise.
742 (aarch64_ins_sve_asimm): Likewise.
743 (aarch64_ins_sve_limm_mov): Likewise.
744 (aarch64_ins_sve_shlimm): Likewise.
745 (aarch64_ins_sve_shrimm): Likewise.
746 * aarch64-asm-2.c: Regenerate.
747 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
748 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
749 * aarch64-dis.c (decode_limm): New function, split out from...
750 (aarch64_ext_limm): ...here.
751 (aarch64_ext_inv_limm): New function.
752 (decode_sve_aimm): Likewise.
753 (aarch64_ext_sve_aimm): Likewise.
754 (aarch64_ext_sve_asimm): Likewise.
755 (aarch64_ext_sve_limm_mov): Likewise.
756 (aarch64_top_bit): Likewise.
757 (aarch64_ext_sve_shlimm): Likewise.
758 (aarch64_ext_sve_shrimm): Likewise.
759 * aarch64-dis-2.c: Regenerate.
761 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
763 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
765 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
766 the AARCH64_MOD_MUL_VL entry.
767 (value_aligned_p): Cope with non-power-of-two alignments.
768 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
769 (print_immediate_offset_address): Likewise.
770 (aarch64_print_operand): Likewise.
771 * aarch64-opc-2.c: Regenerate.
772 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
773 (ins_sve_addr_ri_s9xvl): New inserters.
774 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
775 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
776 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
777 * aarch64-asm-2.c: Regenerate.
778 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
779 (ext_sve_addr_ri_s9xvl): New extractors.
780 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
781 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
782 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
783 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
784 * aarch64-dis-2.c: Regenerate.
786 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
788 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
790 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
791 (FLD_SVE_xs_22): New aarch64_field_kinds.
792 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
793 (get_operand_specific_data): New function.
794 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
795 FLD_SVE_xs_14 and FLD_SVE_xs_22.
796 (operand_general_constraint_met_p): Handle the new SVE address
798 (sve_reg): New array.
799 (get_addr_sve_reg_name): New function.
800 (aarch64_print_operand): Handle the new SVE address operands.
801 * aarch64-opc-2.c: Regenerate.
802 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
803 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
804 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
805 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
806 (aarch64_ins_sve_addr_rr_lsl): Likewise.
807 (aarch64_ins_sve_addr_rz_xtw): Likewise.
808 (aarch64_ins_sve_addr_zi_u5): Likewise.
809 (aarch64_ins_sve_addr_zz): Likewise.
810 (aarch64_ins_sve_addr_zz_lsl): Likewise.
811 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
812 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
813 * aarch64-asm-2.c: Regenerate.
814 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
815 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
816 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
817 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
818 (aarch64_ext_sve_addr_ri_u6): Likewise.
819 (aarch64_ext_sve_addr_rr_lsl): Likewise.
820 (aarch64_ext_sve_addr_rz_xtw): Likewise.
821 (aarch64_ext_sve_addr_zi_u5): Likewise.
822 (aarch64_ext_sve_addr_zz): Likewise.
823 (aarch64_ext_sve_addr_zz_lsl): Likewise.
824 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
825 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
826 * aarch64-dis-2.c: Regenerate.
828 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
830 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
831 AARCH64_OPND_SVE_PATTERN_SCALED.
832 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
833 * aarch64-opc.c (fields): Add a corresponding entry.
834 (set_multiplier_out_of_range_error): New function.
835 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
836 (operand_general_constraint_met_p): Handle
837 AARCH64_OPND_SVE_PATTERN_SCALED.
838 (print_register_offset_address): Use PRIi64 to print the
840 (aarch64_print_operand): Likewise. Handle
841 AARCH64_OPND_SVE_PATTERN_SCALED.
842 * aarch64-opc-2.c: Regenerate.
843 * aarch64-asm.h (ins_sve_scale): New inserter.
844 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
845 * aarch64-asm-2.c: Regenerate.
846 * aarch64-dis.h (ext_sve_scale): New inserter.
847 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
848 * aarch64-dis-2.c: Regenerate.
850 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
852 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
853 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
854 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
855 (FLD_SVE_prfop): Likewise.
856 * aarch64-opc.c: Include libiberty.h.
857 (aarch64_sve_pattern_array): New variable.
858 (aarch64_sve_prfop_array): Likewise.
859 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
860 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
861 AARCH64_OPND_SVE_PRFOP.
862 * aarch64-asm-2.c: Regenerate.
863 * aarch64-dis-2.c: Likewise.
864 * aarch64-opc-2.c: Likewise.
866 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
868 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
869 AARCH64_OPND_QLF_P_[ZM].
870 (aarch64_print_operand): Print /z and /m where appropriate.
872 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
874 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
875 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
876 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
877 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
878 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
879 * aarch64-opc.c (fields): Add corresponding entries here.
880 (operand_general_constraint_met_p): Check that SVE register lists
881 have the correct length. Check the ranges of SVE index registers.
882 Check for cases where p8-p15 are used in 3-bit predicate fields.
883 (aarch64_print_operand): Handle the new SVE operands.
884 * aarch64-opc-2.c: Regenerate.
885 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
886 * aarch64-asm.c (aarch64_ins_sve_index): New function.
887 (aarch64_ins_sve_reglist): Likewise.
888 * aarch64-asm-2.c: Regenerate.
889 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
890 * aarch64-dis.c (aarch64_ext_sve_index): New function.
891 (aarch64_ext_sve_reglist): Likewise.
892 * aarch64-dis-2.c: Regenerate.
894 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
896 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
897 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
898 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
899 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
902 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
904 * aarch64-opc.c (get_offset_int_reg_name): New function.
905 (print_immediate_offset_address): Likewise.
906 (print_register_offset_address): Take the base and offset
907 registers as parameters.
908 (aarch64_print_operand): Update caller accordingly. Use
909 print_immediate_offset_address.
911 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
913 * aarch64-opc.c (BANK): New macro.
914 (R32, R64): Take a register number as argument
917 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
919 * aarch64-opc.c (print_register_list): Add a prefix parameter.
920 (aarch64_print_operand): Update accordingly.
922 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
924 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
926 * aarch64-asm.h (ins_fpimm): New inserter.
927 * aarch64-asm.c (aarch64_ins_fpimm): New function.
928 * aarch64-asm-2.c: Regenerate.
929 * aarch64-dis.h (ext_fpimm): New extractor.
930 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
931 (aarch64_ext_fpimm): New function.
932 * aarch64-dis-2.c: Regenerate.
934 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
936 * aarch64-asm.c: Include libiberty.h.
937 (insert_fields): New function.
938 (aarch64_ins_imm): Use it.
939 * aarch64-dis.c (extract_fields): New function.
940 (aarch64_ext_imm): Use it.
942 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
944 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
945 with an esize parameter.
946 (operand_general_constraint_met_p): Update accordingly.
947 Fix misindented code.
948 * aarch64-asm.c (aarch64_ins_limm): Update call to
949 aarch64_logical_immediate_p.
951 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
953 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
955 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
957 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
959 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
961 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
963 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
965 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
966 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
967 xor3>: Delete mnemonics.
968 <cp_abort>: Rename mnemonic from ...
969 <cpabort>: ...to this.
970 <setb>: Change to a X form instruction.
971 <sync>: Change to 1 operand form.
972 <copy>: Delete mnemonic.
973 <copy_first>: Rename mnemonic from ...
975 <paste, paste.>: Delete mnemonics.
976 <paste_last>: Rename mnemonic from ...
977 <paste.>: ...to this.
979 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
981 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
983 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
985 * s390-mkopc.c (main): Support alternate arch strings.
987 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
989 * s390-opc.txt: Fix kmctr instruction type.
991 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
993 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
994 * i386-init.h: Regenerated.
996 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
998 * opcodes/arc-dis.c (print_insn_arc): Changed.
1000 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
1002 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1005 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
1007 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
1008 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1009 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1011 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
1013 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1014 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1015 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1016 PREFIX_MOD_3_0FAE_REG_4.
1017 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1018 PREFIX_MOD_3_0FAE_REG_4.
1019 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1020 (cpu_flags): Add CpuPTWRITE.
1021 * i386-opc.h (CpuPTWRITE): New.
1022 (i386_cpu_flags): Add cpuptwrite.
1023 * i386-opc.tbl: Add ptwrite instruction.
1024 * i386-init.h: Regenerated.
1025 * i386-tbl.h: Likewise.
1027 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
1029 * arc-dis.h: Wrap around in extern "C".
1031 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1033 * aarch64-tbl.h (V8_2_INSN): New macro.
1034 (aarch64_opcode_table): Use it.
1036 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1038 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1039 CORE_INSN, __FP_INSN and SIMD_INSN.
1041 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1043 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1044 (aarch64_opcode_table): Update uses accordingly.
1046 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
1047 Kwok Cheung Yeung <kcy@codesourcery.com>
1050 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1051 'e_cmplwi' to 'e_cmpli' instead.
1052 (OPVUPRT, OPVUPRT_MASK): Define.
1053 (powerpc_opcodes): Add E200Z4 insns.
1054 (vle_opcodes): Add context save/restore insns.
1056 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
1058 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1059 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1062 2016-07-27 Graham Markall <graham.markall@embecosm.com>
1064 * arc-nps400-tbl.h: Change block comments to GNU format.
1065 * arc-dis.c: Add new globals addrtypenames,
1066 addrtypenames_max, and addtypeunknown.
1067 (get_addrtype): New function.
1068 (print_insn_arc): Print colons and address types when
1070 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1071 define insert and extract functions for all address types.
1072 (arc_operands): Add operands for colon and all address
1074 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1075 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1076 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1077 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1078 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1079 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1081 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
1083 * configure: Regenerated.
1085 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1087 * arc-dis.c (skipclass): New structure.
1088 (decodelist): New variable.
1089 (is_compatible_p): New function.
1090 (new_element): Likewise.
1091 (skip_class_p): Likewise.
1092 (find_format_from_table): Use skip_class_p function.
1093 (find_format): Decode first the extension instructions.
1094 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1096 (parse_option): New function.
1097 (parse_disassembler_options): Likewise.
1098 (print_arc_disassembler_options): Likewise.
1099 (print_insn_arc): Use parse_disassembler_options function. Proper
1100 select ARCv2 cpu variant.
1101 * disassemble.c (disassembler_usage): Add ARC disassembler
1104 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1106 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1107 annotation from the "nal" entry and reorder it beyond "bltzal".
1109 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1111 * sparc-opc.c (ldtxa): New macro.
1112 (sparc_opcodes): Use the macro defined above to add entries for
1113 the LDTXA instructions.
1114 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1117 2016-07-07 James Bowman <james.bowman@ftdichip.com>
1119 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1122 2016-07-01 Jan Beulich <jbeulich@suse.com>
1124 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1125 (movzb): Adjust to cover all permitted suffixes.
1127 * i386-tbl.h: Re-generate.
1129 2016-07-01 Jan Beulich <jbeulich@suse.com>
1131 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1132 (lgdt): Remove Tbyte from non-64-bit variant.
1133 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1134 xsaves64, xsavec64): Remove Disp16.
1135 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1136 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1138 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1139 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1140 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1142 * i386-tbl.h: Re-generate.
1144 2016-07-01 Jan Beulich <jbeulich@suse.com>
1146 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1147 * i386-tbl.h: Re-generate.
1149 2016-06-30 Yao Qi <yao.qi@linaro.org>
1151 * arm-dis.c (print_insn): Fix typo in comment.
1153 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1155 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1156 range of ldst_elemlist operands.
1157 (print_register_list): Use PRIi64 to print the index.
1158 (aarch64_print_operand): Likewise.
1160 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1162 * mcore-opc.h: Remove sentinal.
1163 * mcore-dis.c (print_insn_mcore): Adjust.
1165 2016-06-23 Graham Markall <graham.markall@embecosm.com>
1167 * arc-opc.c: Correct description of availability of NPS400
1170 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1172 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1173 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1174 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1175 xor3>: New mnemonics.
1176 <setb>: Change to a VX form instruction.
1177 (insert_sh6): Add support for rldixor.
1178 (extract_sh6): Likewise.
1180 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1182 * arc-ext.h: Wrap in extern C.
1184 2016-06-21 Graham Markall <graham.markall@embecosm.com>
1186 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1187 Use same method for determining instruction length on ARC700 and
1189 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1190 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1191 with the NPS400 subclass.
1192 * arc-opc.c: Likewise.
1194 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1196 * sparc-opc.c (rdasr): New macro.
1202 (sparc_opcodes): Use the macros above to fix and expand the
1203 definition of read/write instructions from/to
1204 asr/privileged/hyperprivileged instructions.
1205 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1206 %hva_mask_nz. Prefer softint_set and softint_clear over
1207 set_softint and clear_softint.
1208 (print_insn_sparc): Support %ver in Rd.
1210 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1212 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1213 architecture according to the hardware capabilities they require.
1215 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1217 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1218 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1219 bfd_mach_sparc_v9{c,d,e,v,m}.
1220 * sparc-opc.c (MASK_V9C): Define.
1221 (MASK_V9D): Likewise.
1222 (MASK_V9E): Likewise.
1223 (MASK_V9V): Likewise.
1224 (MASK_V9M): Likewise.
1225 (v6): Add MASK_V9{C,D,E,V,M}.
1226 (v6notlet): Likewise.
1230 (v9andleon): Likewise.
1238 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1240 2016-06-15 Nick Clifton <nickc@redhat.com>
1242 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1243 constants to match expected behaviour.
1244 (nds32_parse_opcode): Likewise. Also for whitespace.
1246 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1248 * arc-opc.c (extract_rhv1): Extract value from insn.
1250 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1252 * arc-nps400-tbl.h: Add ldbit instruction.
1253 * arc-opc.c: Add flag classes required for ldbit.
1255 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1257 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1258 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1259 support the above instructions.
1261 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1263 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1264 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1265 csma, cbba, zncv, and hofs.
1266 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1267 support the above instructions.
1269 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1271 * arc-nps400-tbl.h: Add andab and orab instructions.
1273 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1275 * arc-nps400-tbl.h: Add addl-like instructions.
1277 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1279 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1281 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1283 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1286 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1288 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1290 (init_disasm): Handle new command line option "insnlength".
1291 (print_s390_disassembler_options): Mention new option in help
1293 (print_insn_s390): Use the encoded insn length when dumping
1294 unknown instructions.
1296 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1298 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1299 to the address and set as symbol address for LDS/ STS immediate operands.
1301 2016-06-07 Alan Modra <amodra@gmail.com>
1303 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1304 cpu for "vle" to e500.
1305 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1306 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1307 (PPCNONE): Delete, substitute throughout.
1308 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1309 except for major opcode 4 and 31.
1310 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1312 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1314 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1315 ARM_EXT_RAS in relevant entries.
1317 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1320 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1323 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1326 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1327 (indir_v_mode): New.
1328 Add comments for '&'.
1329 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1330 (putop): Handle '&'.
1331 (intel_operand_size): Handle indir_v_mode.
1332 (OP_E_register): Likewise.
1333 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1334 64-bit indirect call/jmp for AMD64.
1335 * i386-tbl.h: Regenerated
1337 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1339 * arc-dis.c (struct arc_operand_iterator): New structure.
1340 (find_format_from_table): All the old content from find_format,
1341 with some minor adjustments, and parameter renaming.
1342 (find_format_long_instructions): New function.
1343 (find_format): Rewritten.
1344 (arc_insn_length): Add LSB parameter.
1345 (extract_operand_value): New function.
1346 (operand_iterator_next): New function.
1347 (print_insn_arc): Use new functions to find opcode, and iterator
1349 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1350 (extract_nps_3bit_dst_short): New function.
1351 (insert_nps_3bit_src2_short): New function.
1352 (extract_nps_3bit_src2_short): New function.
1353 (insert_nps_bitop1_size): New function.
1354 (extract_nps_bitop1_size): New function.
1355 (insert_nps_bitop2_size): New function.
1356 (extract_nps_bitop2_size): New function.
1357 (insert_nps_bitop_mod4_msb): New function.
1358 (extract_nps_bitop_mod4_msb): New function.
1359 (insert_nps_bitop_mod4_lsb): New function.
1360 (extract_nps_bitop_mod4_lsb): New function.
1361 (insert_nps_bitop_dst_pos3_pos4): New function.
1362 (extract_nps_bitop_dst_pos3_pos4): New function.
1363 (insert_nps_bitop_ins_ext): New function.
1364 (extract_nps_bitop_ins_ext): New function.
1365 (arc_operands): Add new operands.
1366 (arc_long_opcodes): New global array.
1367 (arc_num_long_opcodes): New global.
1368 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1370 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1372 * nds32-asm.h: Add extern "C".
1373 * sh-opc.h: Likewise.
1375 2016-06-01 Graham Markall <graham.markall@embecosm.com>
1377 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1378 0,b,limm to the rflt instruction.
1380 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1382 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1385 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1388 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1389 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1390 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1391 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1392 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1393 * i386-init.h: Regenerated.
1395 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1398 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1399 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1400 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1401 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1402 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1403 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1404 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1405 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1406 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1407 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1408 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1409 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1410 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1411 CpuRegMask for AVX512.
1412 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1414 (set_bitfield_from_cpu_flag_init): New function.
1415 (set_bitfield): Remove const on f. Call
1416 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1417 * i386-opc.h (CpuRegMMX): New.
1418 (CpuRegXMM): Likewise.
1419 (CpuRegYMM): Likewise.
1420 (CpuRegZMM): Likewise.
1421 (CpuRegMask): Likewise.
1422 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1424 * i386-init.h: Regenerated.
1425 * i386-tbl.h: Likewise.
1427 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1430 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1431 (opcode_modifiers): Add AMD64 and Intel64.
1432 (main): Properly verify CpuMax.
1433 * i386-opc.h (CpuAMD64): Removed.
1434 (CpuIntel64): Likewise.
1435 (CpuMax): Set to CpuNo64.
1436 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1438 (Intel64): Likewise.
1439 (i386_opcode_modifier): Add amd64 and intel64.
1440 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1442 * i386-init.h: Regenerated.
1443 * i386-tbl.h: Likewise.
1445 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1448 * i386-gen.c (main): Fail if CpuMax is incorrect.
1449 * i386-opc.h (CpuMax): Set to CpuIntel64.
1450 * i386-tbl.h: Regenerated.
1452 2016-05-27 Nick Clifton <nickc@redhat.com>
1455 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1456 (msp430dis_opcode_unsigned): New function.
1457 (msp430dis_opcode_signed): New function.
1458 (msp430_singleoperand): Use the new opcode reading functions.
1459 Only disassenmble bytes if they were successfully read.
1460 (msp430_doubleoperand): Likewise.
1461 (msp430_branchinstr): Likewise.
1462 (msp430x_callx_instr): Likewise.
1463 (print_insn_msp430): Check that it is safe to read bytes before
1464 attempting disassembly. Use the new opcode reading functions.
1466 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1468 * ppc-opc.c (CY): New define. Document it.
1469 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1471 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1473 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1474 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1475 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1476 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1478 * i386-init.h: Regenerated.
1480 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1483 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1484 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1485 * i386-init.h: Regenerated.
1487 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1489 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1490 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1491 * i386-init.h: Regenerated.
1493 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1495 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1497 (print_insn_arc): Set insn_type information.
1498 * arc-opc.c (C_CC): Add F_CLASS_COND.
1499 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1500 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1501 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1502 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1503 (brne, brne_s, jeq_s, jne_s): Likewise.
1505 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1507 * arc-tbl.h (neg): New instruction variant.
1509 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1511 * arc-dis.c (find_format, find_format, get_auxreg)
1512 (print_insn_arc): Changed.
1513 * arc-ext.h (INSERT_XOP): Likewise.
1515 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1517 * tic54x-dis.c (sprint_mmr): Adjust.
1518 * tic54x-opc.c: Likewise.
1520 2016-05-19 Alan Modra <amodra@gmail.com>
1522 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1524 2016-05-19 Alan Modra <amodra@gmail.com>
1526 * ppc-opc.c: Formatting.
1527 (NSISIGNOPT): Define.
1528 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1530 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1532 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1533 replacing references to `micromips_ase' throughout.
1534 (_print_insn_mips): Don't use file-level microMIPS annotation to
1535 determine the disassembly mode with the symbol table.
1537 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1539 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1541 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1543 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1545 * mips-opc.c (D34): New macro.
1546 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1548 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1550 * i386-dis.c (prefix_table): Add RDPID instruction.
1551 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1552 (cpu_flags): Add RDPID bitfield.
1553 * i386-opc.h (enum): Add RDPID element.
1554 (i386_cpu_flags): Add RDPID field.
1555 * i386-opc.tbl: Add RDPID instruction.
1556 * i386-init.h: Regenerate.
1557 * i386-tbl.h: Regenerate.
1559 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1561 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1562 branch type of a symbol.
1563 (print_insn): Likewise.
1565 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1567 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1568 Mainline Security Extensions instructions.
1569 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1570 Extensions instructions.
1571 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1573 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1576 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1578 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1580 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1582 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1583 (arcExtMap_genOpcode): Likewise.
1584 * arc-opc.c (arg_32bit_rc): Define new variable.
1585 (arg_32bit_u6): Likewise.
1586 (arg_32bit_limm): Likewise.
1588 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1590 * aarch64-gen.c (VERIFIER): Define.
1591 * aarch64-opc.c (VERIFIER): Define.
1592 (verify_ldpsw): Use static linkage.
1593 * aarch64-opc.h (verify_ldpsw): Remove.
1594 * aarch64-tbl.h: Use VERIFIER for verifiers.
1596 2016-04-28 Nick Clifton <nickc@redhat.com>
1599 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1600 * aarch64-opc.c (verify_ldpsw): New function.
1601 * aarch64-opc.h (verify_ldpsw): New prototype.
1602 * aarch64-tbl.h: Add initialiser for verifier field.
1603 (LDPSW): Set verifier to verify_ldpsw.
1605 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1609 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1610 smaller than address size.
1612 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1614 * alpha-dis.c: Regenerate.
1615 * crx-dis.c: Likewise.
1616 * disassemble.c: Likewise.
1617 * epiphany-opc.c: Likewise.
1618 * fr30-opc.c: Likewise.
1619 * frv-opc.c: Likewise.
1620 * ip2k-opc.c: Likewise.
1621 * iq2000-opc.c: Likewise.
1622 * lm32-opc.c: Likewise.
1623 * lm32-opinst.c: Likewise.
1624 * m32c-opc.c: Likewise.
1625 * m32r-opc.c: Likewise.
1626 * m32r-opinst.c: Likewise.
1627 * mep-opc.c: Likewise.
1628 * mt-opc.c: Likewise.
1629 * or1k-opc.c: Likewise.
1630 * or1k-opinst.c: Likewise.
1631 * tic80-opc.c: Likewise.
1632 * xc16x-opc.c: Likewise.
1633 * xstormy16-opc.c: Likewise.
1635 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1637 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1638 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1639 calcsd, and calcxd instructions.
1640 * arc-opc.c (insert_nps_bitop_size): Delete.
1641 (extract_nps_bitop_size): Delete.
1642 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1643 (extract_nps_qcmp_m3): Define.
1644 (extract_nps_qcmp_m2): Define.
1645 (extract_nps_qcmp_m1): Define.
1646 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1647 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1648 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1649 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1650 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1653 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1655 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1657 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1659 * Makefile.in: Regenerated with automake 1.11.6.
1660 * aclocal.m4: Likewise.
1662 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1664 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1666 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1667 (extract_nps_cmem_uimm16): New function.
1668 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1670 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1672 * arc-dis.c (arc_insn_length): New function.
1673 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1674 (find_format): Change insnLen parameter to unsigned.
1676 2016-04-13 Nick Clifton <nickc@redhat.com>
1679 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1680 the LD.B and LD.BU instructions.
1682 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1684 * arc-dis.c (find_format): Check for extension flags.
1685 (print_flags): New function.
1686 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1688 * arc-ext.c (arcExtMap_coreRegName): Use
1689 LAST_EXTENSION_CORE_REGISTER.
1690 (arcExtMap_coreReadWrite): Likewise.
1691 (dump_ARC_extmap): Update printing.
1692 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1693 (arc_aux_regs): Add cpu field.
1694 * arc-regs.h: Add cpu field, lower case name aux registers.
1696 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1698 * arc-tbl.h: Add rtsc, sleep with no arguments.
1700 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1702 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1704 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1705 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1706 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1707 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1708 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1709 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1710 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1711 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1712 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1713 (arc_opcode arc_opcodes): Null terminate the array.
1714 (arc_num_opcodes): Remove.
1715 * arc-ext.h (INSERT_XOP): Define.
1716 (extInstruction_t): Likewise.
1717 (arcExtMap_instName): Delete.
1718 (arcExtMap_insn): New function.
1719 (arcExtMap_genOpcode): Likewise.
1720 * arc-ext.c (ExtInstruction): Remove.
1721 (create_map): Zero initialize instruction fields.
1722 (arcExtMap_instName): Remove.
1723 (arcExtMap_insn): New function.
1724 (dump_ARC_extmap): More info while debuging.
1725 (arcExtMap_genOpcode): New function.
1726 * arc-dis.c (find_format): New function.
1727 (print_insn_arc): Use find_format.
1728 (arc_get_disassembler): Enable dump_ARC_extmap only when
1731 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1733 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1734 instruction bits out.
1736 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1738 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1739 * arc-opc.c (arc_flag_operands): Add new flags.
1740 (arc_flag_classes): Add new classes.
1742 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1744 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1746 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1748 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1749 encode1, rflt, crc16, and crc32 instructions.
1750 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1751 (arc_flag_classes): Add C_NPS_R.
1752 (insert_nps_bitop_size_2b): New function.
1753 (extract_nps_bitop_size_2b): Likewise.
1754 (insert_nps_bitop_uimm8): Likewise.
1755 (extract_nps_bitop_uimm8): Likewise.
1756 (arc_operands): Add new operand entries.
1758 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1760 * arc-regs.h: Add a new subclass field. Add double assist
1761 accumulator register values.
1762 * arc-tbl.h: Use DPA subclass to mark the double assist
1763 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1764 * arc-opc.c (RSP): Define instead of SP.
1765 (arc_aux_regs): Add the subclass field.
1767 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1769 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1771 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1773 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1776 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1778 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1779 issues. No functional changes.
1781 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1783 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1784 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1785 (RTT): Remove duplicate.
1786 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1787 (PCT_CONFIG*): Remove.
1788 (D1L, D1H, D2H, D2L): Define.
1790 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1792 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1794 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1796 * arc-tbl.h (invld07): Remove.
1797 * arc-ext-tbl.h: New file.
1798 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1799 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1801 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1803 Fix -Wstack-usage warnings.
1804 * aarch64-dis.c (print_operands): Substitute size.
1805 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1807 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1809 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1810 to get a proper diagnostic when an invalid ASR register is used.
1812 2016-03-22 Nick Clifton <nickc@redhat.com>
1814 * configure: Regenerate.
1816 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1818 * arc-nps400-tbl.h: New file.
1819 * arc-opc.c: Add top level comment.
1820 (insert_nps_3bit_dst): New function.
1821 (extract_nps_3bit_dst): New function.
1822 (insert_nps_3bit_src2): New function.
1823 (extract_nps_3bit_src2): New function.
1824 (insert_nps_bitop_size): New function.
1825 (extract_nps_bitop_size): New function.
1826 (arc_flag_operands): Add nps400 entries.
1827 (arc_flag_classes): Add nps400 entries.
1828 (arc_operands): Add nps400 entries.
1829 (arc_opcodes): Add nps400 include.
1831 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1833 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1834 the new class enum values.
1836 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1838 * arc-dis.c (print_insn_arc): Handle nps400.
1840 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1842 * arc-opc.c (BASE): Delete.
1844 2016-03-18 Nick Clifton <nickc@redhat.com>
1847 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1848 of MOV insn that aliases an ORR insn.
1850 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1852 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1854 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1856 * mcore-opc.h: Add const qualifiers.
1857 * microblaze-opc.h (struct op_code_struct): Likewise.
1858 * sh-opc.h: Likewise.
1859 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1860 (tic4x_print_op): Likewise.
1862 2016-03-02 Alan Modra <amodra@gmail.com>
1864 * or1k-desc.h: Regenerate.
1865 * fr30-ibld.c: Regenerate.
1866 * rl78-decode.c: Regenerate.
1868 2016-03-01 Nick Clifton <nickc@redhat.com>
1871 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1873 2016-02-24 Renlin Li <renlin.li@arm.com>
1875 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1876 (print_insn_coprocessor): Support fp16 instructions.
1878 2016-02-24 Renlin Li <renlin.li@arm.com>
1880 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1881 vminnm, vrint(mpna).
1883 2016-02-24 Renlin Li <renlin.li@arm.com>
1885 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1886 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1888 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1890 * i386-dis.c (print_insn): Parenthesize expression to prevent
1891 truncated addresses.
1894 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1895 Janek van Oirschot <jvanoirs@synopsys.com>
1897 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1900 2016-02-04 Nick Clifton <nickc@redhat.com>
1903 * msp430-dis.c (print_insn_msp430): Add a special case for
1904 decoding an RRC instruction with the ZC bit set in the extension
1907 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1909 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1910 * epiphany-ibld.c: Regenerate.
1911 * fr30-ibld.c: Regenerate.
1912 * frv-ibld.c: Regenerate.
1913 * ip2k-ibld.c: Regenerate.
1914 * iq2000-ibld.c: Regenerate.
1915 * lm32-ibld.c: Regenerate.
1916 * m32c-ibld.c: Regenerate.
1917 * m32r-ibld.c: Regenerate.
1918 * mep-ibld.c: Regenerate.
1919 * mt-ibld.c: Regenerate.
1920 * or1k-ibld.c: Regenerate.
1921 * xc16x-ibld.c: Regenerate.
1922 * xstormy16-ibld.c: Regenerate.
1924 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1926 * epiphany-dis.c: Regenerated from latest cpu files.
1928 2016-02-01 Michael McConville <mmcco@mykolab.com>
1930 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1933 2016-01-25 Renlin Li <renlin.li@arm.com>
1935 * arm-dis.c (mapping_symbol_for_insn): New function.
1936 (find_ifthen_state): Call mapping_symbol_for_insn().
1938 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1940 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1941 of MSR UAO immediate operand.
1943 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1945 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1946 instruction support.
1948 2016-01-17 Alan Modra <amodra@gmail.com>
1950 * configure: Regenerate.
1952 2016-01-14 Nick Clifton <nickc@redhat.com>
1954 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1955 instructions that can support stack pointer operations.
1956 * rl78-decode.c: Regenerate.
1957 * rl78-dis.c: Fix display of stack pointer in MOVW based
1960 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1962 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1963 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1964 erxtatus_el1 and erxaddr_el1.
1966 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1968 * arm-dis.c (arm_opcodes): Add "esb".
1969 (thumb_opcodes): Likewise.
1971 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1973 * ppc-opc.c <xscmpnedp>: Delete.
1974 <xvcmpnedp>: Likewise.
1975 <xvcmpnedp.>: Likewise.
1976 <xvcmpnesp>: Likewise.
1977 <xvcmpnesp.>: Likewise.
1979 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1982 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1985 2016-01-01 Alan Modra <amodra@gmail.com>
1987 Update year range in copyright notice of all files.
1989 For older changes see ChangeLog-2015
1991 Copyright (C) 2016 Free Software Foundation, Inc.
1993 Copying and distribution of this file, with or without modification,
1994 are permitted in any medium without royalty provided the copyright
1995 notice and this notice are preserved.
2001 version-control: never