1 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
3 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
4 MDMX-like instructions.
5 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
6 printing "Q" operands for INSN_5400 instructions.
8 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
10 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
12 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
15 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
17 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
19 * mips16-opc.c (mips16_opcodes): Likewise.
20 * micromips-opc.c (micromips_opcodes): Likewise.
21 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
22 (print_insn_mips16): Handle "+i".
23 (print_insn_micromips): Likewise. Conditionally preserve the
24 ISA bit for "a" but not for "+i".
26 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
28 * micromips-opc.c (WR_mhi): Rename to..
30 (micromips_opcodes): Update "movep" entry accordingly. Replace
32 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
33 (micromips_to_32_reg_h_map1): ...this.
34 (micromips_to_32_reg_i_map): Rename to...
35 (micromips_to_32_reg_h_map2): ...this.
36 (print_micromips_insn): Remove "mi" case. Print both registers
39 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
41 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
42 * micromips-opc.c (micromips_opcodes): Likewise.
43 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
44 and "+T" handling. Check for a "0" suffix when deciding whether to
45 use coprocessor 0 names. In that case, also check for ",H" selectors.
47 2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
49 * s390-opc.c (J12_12, J24_24): New macros.
50 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
51 (MASK_MII_UPI): Rename to MASK_MII_UPP.
52 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
54 2013-07-04 Alan Modra <amodra@gmail.com>
56 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
58 2013-06-26 Nick Clifton <nickc@redhat.com>
60 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
61 field when checking for type 2 nop.
62 * rx-decode.c: Regenerate.
64 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
66 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
69 2013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
71 * mips-dis.c (is_mips16_plt_tail): New function.
72 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
74 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
76 2013-06-21 DJ Delorie <dj@redhat.com>
78 * msp430-decode.opc: New.
79 * msp430-decode.c: New/generated.
80 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
81 (MAINTAINER_CLEANFILES): Likewise.
82 Add rule to build msp430-decode.c frommsp430decode.opc
83 using the opc2c program.
84 * Makefile.in: Regenerate.
85 * configure.in: Add msp430-decode.lo to msp430 architecture files.
86 * configure: Regenerate.
88 2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
90 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
91 (SYMTAB_AVAILABLE): Removed.
92 (#include "elf/aarch64.h): Ditto.
94 2013-06-17 Catherine Moore <clm@codesourcery.com>
95 Maciej W. Rozycki <macro@codesourcery.com>
96 Chao-Ying Fu <fu@mips.com>
98 * micromips-opc.c (EVA): Define.
100 (micromips_opcodes): Add EVA opcodes.
101 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
102 (print_insn_args): Handle EVA offsets.
103 (print_insn_micromips): Likewise.
104 * mips-opc.c (EVA): Define.
106 (mips_builtin_opcodes): Add EVA opcodes.
108 2013-06-17 Alan Modra <amodra@gmail.com>
110 * Makefile.am (mips-opc.lo): Add rules to create automatic
111 dependency files. Pass archdefs.
112 (micromips-opc.lo, mips16-opc.lo): Likewise.
113 * Makefile.in: Regenerate.
115 2013-06-14 DJ Delorie <dj@redhat.com>
117 * rx-decode.opc (rx_decode_opcode): Bit operations on
118 registers are 32-bit operations, not 8-bit operations.
119 * rx-decode.c: Regenerate.
121 2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
123 * micromips-opc.c (IVIRT): New define.
124 (IVIRT64): New define.
125 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
126 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
128 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
129 dmtgc0 to print cp0 names.
131 2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
133 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
136 2013-06-08 Catherine Moore <clm@codesourcery.com>
137 Richard Sandiford <rdsandiford@googlemail.com>
139 * micromips-opc.c (D32, D33, MC): Update definitions.
140 (micromips_opcodes): Initialize ase field.
141 * mips-dis.c (mips_arch_choice): Add ase field.
142 (mips_arch_choices): Initialize ase field.
143 (set_default_mips_dis_options): Declare and setup mips_ase.
144 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
145 MT32, MC): Update definitions.
146 (mips_builtin_opcodes): Initialize ase field.
148 2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
150 * s390-opc.txt (flogr): Require a register pair destination.
152 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
154 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
157 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
159 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
161 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
163 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
164 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
165 XLS_MASK, PPCVSX2): New defines.
166 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
167 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
168 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
169 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
170 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
171 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
172 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
173 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
174 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
175 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
176 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
177 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
178 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
179 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
180 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
181 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
182 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
183 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
184 <lxvx, stxvx>: New extended mnemonics.
186 2013-05-17 Alan Modra <amodra@gmail.com>
188 * ia64-raw.tbl: Replace non-ASCII char.
189 * ia64-waw.tbl: Likewise.
190 * ia64-asmtab.c: Regenerate.
192 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
194 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
195 * i386-init.h: Regenerated.
197 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
199 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
200 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
201 check from [0, 255] to [-128, 255].
203 2013-05-09 Andrew Pinski <apinski@cavium.com>
205 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
206 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
207 (parse_mips_dis_option): Handle the virt option.
208 (print_insn_args): Handle "+J".
209 (print_mips_disassembler_options): Print out message about virt64.
210 * mips-opc.c (IVIRT): New define.
211 (IVIRT64): New define.
212 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
213 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
214 Move rfe to the bottom as it conflicts with tlbgp.
216 2013-05-09 Alan Modra <amodra@gmail.com>
218 * ppc-opc.c (extract_vlesi): Properly sign extend.
219 (extract_vlensi): Likewise. Comment reason for setting invalid.
221 2013-05-02 Nick Clifton <nickc@redhat.com>
223 * msp430-dis.c: Add support for MSP430X instructions.
225 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
227 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
230 2013-04-17 Wei-chen Wang <cole945@gmail.com>
233 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
235 (hash_insns_list): Likewise.
237 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
239 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
242 2013-04-08 Jan Beulich <jbeulich@suse.com>
244 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
245 * i386-tbl.h: Re-generate.
247 2013-04-06 David S. Miller <davem@davemloft.net>
249 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
250 of an opcode, prefer the one with F_PREFERRED set.
251 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
252 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
253 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
254 mark existing mnenomics as aliases. Add "cc" suffix to edge
255 instructions generating condition codes, mark existing mnenomics
256 as aliases. Add "fp" prefix to VIS compare instructions, mark
257 existing mnenomics as aliases.
259 2013-04-03 Nick Clifton <nickc@redhat.com>
261 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
262 destination address by subtracting the operand from the current
264 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
265 a positive value in the insn.
266 (extract_u16_loop): Do not negate the returned value.
267 (D16_LOOP): Add V850_INVERSE_PCREL flag.
269 (ceilf.sw): Remove duplicate entry.
270 (cvtf.hs): New entry.
276 (maddf.s): Restrict to E3V5 architectures.
278 (nmaddf.s): Likewise.
279 (nmsubf.s): Likewise.
281 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
283 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
285 (print_insn): Pass sizeflag to get_sib.
287 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
290 * tic6x-dis.c: Add support for displaying 16-bit insns.
292 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
295 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
296 individual msb and lsb halves in src1 & src2 fields. Discard the
297 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
298 follow what Ti SDK does in that case as any value in the src1
299 field yields the same output with SDK disassembler.
301 2013-03-12 Michael Eager <eager@eagercon.com>
303 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
305 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
307 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
309 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
311 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
313 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
315 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
317 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
319 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
320 (thumb32_opcodes): Likewise.
321 (print_insn_thumb32): Handle 'S' control char.
323 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
325 * lm32-desc.c: Regenerate.
327 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
329 * i386-reg.tbl (riz): Add RegRex64.
330 * i386-tbl.h: Regenerated.
332 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
334 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
335 (aarch64_feature_crc): New static.
337 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
338 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
339 * aarch64-asm-2.c: Re-generate.
340 * aarch64-dis-2.c: Ditto.
341 * aarch64-opc-2.c: Ditto.
343 2013-02-27 Alan Modra <amodra@gmail.com>
345 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
346 * rl78-decode.c: Regenerate.
348 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
350 * rl78-decode.opc: Fix encoding of DIVWU insn.
351 * rl78-decode.c: Regenerate.
353 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
356 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
358 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
359 (cpu_flags): Add CpuSMAP.
361 * i386-opc.h (CpuSMAP): New.
362 (i386_cpu_flags): Add cpusmap.
364 * i386-opc.tbl: Add clac and stac.
366 * i386-init.h: Regenerated.
367 * i386-tbl.h: Likewise.
369 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
371 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
372 which also makes the disassembler output be in little
373 endian like it should be.
375 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
377 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
379 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
381 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
383 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
384 section disassembled.
386 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
388 * arm-dis.c: Update strht pattern.
390 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
392 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
393 single-float. Disable ll, lld, sc and scd for EE. Disable the
394 trunc.w.s macro for EE.
396 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
397 Andrew Jenner <andrew@codesourcery.com>
399 Based on patches from Altera Corporation.
401 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
403 * Makefile.in: Regenerated.
404 * configure.in: Add case for bfd_nios2_arch.
405 * configure: Regenerated.
406 * disassemble.c (ARCH_nios2): Define.
407 (disassembler): Add case for bfd_arch_nios2.
408 * nios2-dis.c: New file.
409 * nios2-opc.c: New file.
411 2013-02-04 Alan Modra <amodra@gmail.com>
413 * po/POTFILES.in: Regenerate.
414 * rl78-decode.c: Regenerate.
415 * rx-decode.c: Regenerate.
417 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
419 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
420 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
421 * aarch64-asm.c (convert_xtl_to_shll): New function.
422 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
423 calling convert_xtl_to_shll.
424 * aarch64-dis.c (convert_shll_to_xtl): New function.
425 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
426 calling convert_shll_to_xtl.
427 * aarch64-gen.c: Update copyright year.
428 * aarch64-asm-2.c: Re-generate.
429 * aarch64-dis-2.c: Re-generate.
430 * aarch64-opc-2.c: Re-generate.
432 2013-01-24 Nick Clifton <nickc@redhat.com>
434 * v850-dis.c: Add support for e3v5 architecture.
435 * v850-opc.c: Likewise.
437 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
439 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
440 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
441 * aarch64-opc.c (operand_general_constraint_met_p): For
442 AARCH64_MOD_LSL, move the range check on the shift amount before the
443 alignment check; change to call set_sft_amount_out_of_range_error
444 instead of set_imm_out_of_range_error.
445 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
446 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
447 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
450 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
452 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
454 * i386-init.h: Regenerated.
455 * i386-tbl.h: Likewise.
457 2013-01-15 Nick Clifton <nickc@redhat.com>
459 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
461 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
463 2013-01-14 Will Newton <will.newton@imgtec.com>
465 * metag-dis.c (REG_WIDTH): Increase to 64.
467 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
469 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
470 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
471 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
473 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
474 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
475 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
476 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
478 2013-01-10 Will Newton <will.newton@imgtec.com>
480 * Makefile.am: Add Meta.
481 * configure.in: Add Meta.
482 * disassemble.c: Add Meta support.
483 * metag-dis.c: New file.
484 * Makefile.in: Regenerate.
485 * configure: Regenerate.
487 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
489 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
490 (match_opcode): Rename to cr16_match_opcode.
492 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
494 * mips-dis.c: Add names for CP0 registers of r5900.
495 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
496 instructions sq and lq.
497 Add support for MIPS r5900 CPU.
498 Add support for 128 bit MMI (Multimedia Instructions).
499 Add support for EE instructions (Emotion Engine).
500 Disable unsupported floating point instructions (64 bit and
501 undefined compare operations).
502 Enable instructions of MIPS ISA IV which are supported by r5900.
503 Disable 64 bit co processor instructions.
504 Disable 64 bit multiplication and division instructions.
505 Disable instructions for co-processor 2 and 3, because these are
506 not supported (preparation for later VU0 support (Vector Unit)).
507 Disable cvt.w.s because this behaves like trunc.w.s and the
508 correct execution can't be ensured on r5900.
509 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
510 will confuse less developers and compilers.
512 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
514 * aarch64-opc.c (aarch64_print_operand): Change to print
515 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
517 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
518 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
521 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
523 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
524 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
526 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
528 * i386-gen.c (process_copyright): Update copyright year to 2013.
530 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
532 * cr16-dis.c (match_opcode,make_instruction): Remove static
534 (dwordU,wordU): Moved typedefs to opcode/cr16.h
535 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
537 For older changes see ChangeLog-2012
539 Copyright (C) 2013 Free Software Foundation, Inc.
541 Copying and distribution of this file, with or without modification,
542 are permitted in any medium without royalty provided the copyright
543 notice and this notice are preserved.
549 version-control: never