1 2013-07-04 Alan Modra <amodra@gmail.com>
3 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
5 2013-06-26 Nick Clifton <nickc@redhat.com>
7 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
8 field when checking for type 2 nop.
9 * rx-decode.c: Regenerate.
11 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
13 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
16 2013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
18 * mips-dis.c (is_mips16_plt_tail): New function.
19 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
21 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
23 2013-06-21 DJ Delorie <dj@redhat.com>
25 * msp430-decode.opc: New.
26 * msp430-decode.c: New/generated.
27 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
28 (MAINTAINER_CLEANFILES): Likewise.
29 Add rule to build msp430-decode.c frommsp430decode.opc
30 using the opc2c program.
31 * Makefile.in: Regenerate.
32 * configure.in: Add msp430-decode.lo to msp430 architecture files.
33 * configure: Regenerate.
35 2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
37 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
38 (SYMTAB_AVAILABLE): Removed.
39 (#include "elf/aarch64.h): Ditto.
41 2013-06-17 Catherine Moore <clm@codesourcery.com>
42 Maciej W. Rozycki <macro@codesourcery.com>
43 Chao-Ying Fu <fu@mips.com>
45 * micromips-opc.c (EVA): Define.
47 (micromips_opcodes): Add EVA opcodes.
48 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
49 (print_insn_args): Handle EVA offsets.
50 (print_insn_micromips): Likewise.
51 * mips-opc.c (EVA): Define.
53 (mips_builtin_opcodes): Add EVA opcodes.
55 2013-06-17 Alan Modra <amodra@gmail.com>
57 * Makefile.am (mips-opc.lo): Add rules to create automatic
58 dependency files. Pass archdefs.
59 (micromips-opc.lo, mips16-opc.lo): Likewise.
60 * Makefile.in: Regenerate.
62 2013-06-14 DJ Delorie <dj@redhat.com>
64 * rx-decode.opc (rx_decode_opcode): Bit operations on
65 registers are 32-bit operations, not 8-bit operations.
66 * rx-decode.c: Regenerate.
68 2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
70 * micromips-opc.c (IVIRT): New define.
71 (IVIRT64): New define.
72 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
73 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
75 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
76 dmtgc0 to print cp0 names.
78 2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
80 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
83 2013-06-08 Catherine Moore <clm@codesourcery.com>
84 Richard Sandiford <rdsandiford@googlemail.com>
86 * micromips-opc.c (D32, D33, MC): Update definitions.
87 (micromips_opcodes): Initialize ase field.
88 * mips-dis.c (mips_arch_choice): Add ase field.
89 (mips_arch_choices): Initialize ase field.
90 (set_default_mips_dis_options): Declare and setup mips_ase.
91 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
92 MT32, MC): Update definitions.
93 (mips_builtin_opcodes): Initialize ase field.
95 2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
97 * s390-opc.txt (flogr): Require a register pair destination.
99 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
101 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
104 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
106 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
108 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
110 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
111 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
112 XLS_MASK, PPCVSX2): New defines.
113 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
114 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
115 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
116 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
117 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
118 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
119 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
120 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
121 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
122 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
123 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
124 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
125 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
126 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
127 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
128 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
129 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
130 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
131 <lxvx, stxvx>: New extended mnemonics.
133 2013-05-17 Alan Modra <amodra@gmail.com>
135 * ia64-raw.tbl: Replace non-ASCII char.
136 * ia64-waw.tbl: Likewise.
137 * ia64-asmtab.c: Regenerate.
139 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
141 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
142 * i386-init.h: Regenerated.
144 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
146 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
147 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
148 check from [0, 255] to [-128, 255].
150 2013-05-09 Andrew Pinski <apinski@cavium.com>
152 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
153 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
154 (parse_mips_dis_option): Handle the virt option.
155 (print_insn_args): Handle "+J".
156 (print_mips_disassembler_options): Print out message about virt64.
157 * mips-opc.c (IVIRT): New define.
158 (IVIRT64): New define.
159 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
160 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
161 Move rfe to the bottom as it conflicts with tlbgp.
163 2013-05-09 Alan Modra <amodra@gmail.com>
165 * ppc-opc.c (extract_vlesi): Properly sign extend.
166 (extract_vlensi): Likewise. Comment reason for setting invalid.
168 2013-05-02 Nick Clifton <nickc@redhat.com>
170 * msp430-dis.c: Add support for MSP430X instructions.
172 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
174 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
177 2013-04-17 Wei-chen Wang <cole945@gmail.com>
180 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
182 (hash_insns_list): Likewise.
184 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
186 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
189 2013-04-08 Jan Beulich <jbeulich@suse.com>
191 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
192 * i386-tbl.h: Re-generate.
194 2013-04-06 David S. Miller <davem@davemloft.net>
196 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
197 of an opcode, prefer the one with F_PREFERRED set.
198 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
199 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
200 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
201 mark existing mnenomics as aliases. Add "cc" suffix to edge
202 instructions generating condition codes, mark existing mnenomics
203 as aliases. Add "fp" prefix to VIS compare instructions, mark
204 existing mnenomics as aliases.
206 2013-04-03 Nick Clifton <nickc@redhat.com>
208 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
209 destination address by subtracting the operand from the current
211 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
212 a positive value in the insn.
213 (extract_u16_loop): Do not negate the returned value.
214 (D16_LOOP): Add V850_INVERSE_PCREL flag.
216 (ceilf.sw): Remove duplicate entry.
217 (cvtf.hs): New entry.
223 (maddf.s): Restrict to E3V5 architectures.
225 (nmaddf.s): Likewise.
226 (nmsubf.s): Likewise.
228 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
230 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
232 (print_insn): Pass sizeflag to get_sib.
234 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
237 * tic6x-dis.c: Add support for displaying 16-bit insns.
239 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
242 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
243 individual msb and lsb halves in src1 & src2 fields. Discard the
244 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
245 follow what Ti SDK does in that case as any value in the src1
246 field yields the same output with SDK disassembler.
248 2013-03-12 Michael Eager <eager@eagercon.com>
250 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
252 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
254 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
256 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
258 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
260 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
262 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
264 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
266 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
267 (thumb32_opcodes): Likewise.
268 (print_insn_thumb32): Handle 'S' control char.
270 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
272 * lm32-desc.c: Regenerate.
274 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
276 * i386-reg.tbl (riz): Add RegRex64.
277 * i386-tbl.h: Regenerated.
279 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
281 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
282 (aarch64_feature_crc): New static.
284 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
285 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
286 * aarch64-asm-2.c: Re-generate.
287 * aarch64-dis-2.c: Ditto.
288 * aarch64-opc-2.c: Ditto.
290 2013-02-27 Alan Modra <amodra@gmail.com>
292 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
293 * rl78-decode.c: Regenerate.
295 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
297 * rl78-decode.opc: Fix encoding of DIVWU insn.
298 * rl78-decode.c: Regenerate.
300 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
303 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
305 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
306 (cpu_flags): Add CpuSMAP.
308 * i386-opc.h (CpuSMAP): New.
309 (i386_cpu_flags): Add cpusmap.
311 * i386-opc.tbl: Add clac and stac.
313 * i386-init.h: Regenerated.
314 * i386-tbl.h: Likewise.
316 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
318 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
319 which also makes the disassembler output be in little
320 endian like it should be.
322 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
324 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
326 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
328 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
330 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
331 section disassembled.
333 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
335 * arm-dis.c: Update strht pattern.
337 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
339 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
340 single-float. Disable ll, lld, sc and scd for EE. Disable the
341 trunc.w.s macro for EE.
343 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
344 Andrew Jenner <andrew@codesourcery.com>
346 Based on patches from Altera Corporation.
348 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
350 * Makefile.in: Regenerated.
351 * configure.in: Add case for bfd_nios2_arch.
352 * configure: Regenerated.
353 * disassemble.c (ARCH_nios2): Define.
354 (disassembler): Add case for bfd_arch_nios2.
355 * nios2-dis.c: New file.
356 * nios2-opc.c: New file.
358 2013-02-04 Alan Modra <amodra@gmail.com>
360 * po/POTFILES.in: Regenerate.
361 * rl78-decode.c: Regenerate.
362 * rx-decode.c: Regenerate.
364 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
366 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
367 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
368 * aarch64-asm.c (convert_xtl_to_shll): New function.
369 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
370 calling convert_xtl_to_shll.
371 * aarch64-dis.c (convert_shll_to_xtl): New function.
372 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
373 calling convert_shll_to_xtl.
374 * aarch64-gen.c: Update copyright year.
375 * aarch64-asm-2.c: Re-generate.
376 * aarch64-dis-2.c: Re-generate.
377 * aarch64-opc-2.c: Re-generate.
379 2013-01-24 Nick Clifton <nickc@redhat.com>
381 * v850-dis.c: Add support for e3v5 architecture.
382 * v850-opc.c: Likewise.
384 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
386 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
387 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
388 * aarch64-opc.c (operand_general_constraint_met_p): For
389 AARCH64_MOD_LSL, move the range check on the shift amount before the
390 alignment check; change to call set_sft_amount_out_of_range_error
391 instead of set_imm_out_of_range_error.
392 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
393 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
394 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
397 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
399 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
401 * i386-init.h: Regenerated.
402 * i386-tbl.h: Likewise.
404 2013-01-15 Nick Clifton <nickc@redhat.com>
406 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
408 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
410 2013-01-14 Will Newton <will.newton@imgtec.com>
412 * metag-dis.c (REG_WIDTH): Increase to 64.
414 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
416 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
417 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
418 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
420 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
421 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
422 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
423 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
425 2013-01-10 Will Newton <will.newton@imgtec.com>
427 * Makefile.am: Add Meta.
428 * configure.in: Add Meta.
429 * disassemble.c: Add Meta support.
430 * metag-dis.c: New file.
431 * Makefile.in: Regenerate.
432 * configure: Regenerate.
434 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
436 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
437 (match_opcode): Rename to cr16_match_opcode.
439 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
441 * mips-dis.c: Add names for CP0 registers of r5900.
442 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
443 instructions sq and lq.
444 Add support for MIPS r5900 CPU.
445 Add support for 128 bit MMI (Multimedia Instructions).
446 Add support for EE instructions (Emotion Engine).
447 Disable unsupported floating point instructions (64 bit and
448 undefined compare operations).
449 Enable instructions of MIPS ISA IV which are supported by r5900.
450 Disable 64 bit co processor instructions.
451 Disable 64 bit multiplication and division instructions.
452 Disable instructions for co-processor 2 and 3, because these are
453 not supported (preparation for later VU0 support (Vector Unit)).
454 Disable cvt.w.s because this behaves like trunc.w.s and the
455 correct execution can't be ensured on r5900.
456 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
457 will confuse less developers and compilers.
459 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
461 * aarch64-opc.c (aarch64_print_operand): Change to print
462 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
464 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
465 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
468 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
470 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
471 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
473 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
475 * i386-gen.c (process_copyright): Update copyright year to 2013.
477 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
479 * cr16-dis.c (match_opcode,make_instruction): Remove static
481 (dwordU,wordU): Moved typedefs to opcode/cr16.h
482 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
484 For older changes see ChangeLog-2012
486 Copyright (C) 2013 Free Software Foundation, Inc.
488 Copying and distribution of this file, with or without modification,
489 are permitted in any medium without royalty provided the copyright
490 notice and this notice are preserved.
496 version-control: never