1 2006-11-30 Jan Beulich <jbeulich@novell.com>
3 * i386-dis.c (zAX): New.
8 (putop): New suffix character 'G'.
9 (dis386): Use it for in, out, ins, and outs.
10 (intel_operand_size): Handle z_mode.
11 (OP_REG): Delete unreachable case indir_dx_reg.
12 (OP_IMREG): Fix Intel syntax output for case indir_dx_reg. Handle
14 (OP_ESreg): Fix Intel syntax operand size handling.
17 2006-11-30 Jan Beulich <jbeulich@novell.com>
19 * i386-dis.c (dis386): Use 'R' and 'O' for cbw/cwd unconditionally.
20 (putop): For 'O' suffix, print 'q' in Intel mode, and mark data prefix
21 used. For 'R' and 'W' suffix, simplify and fix Intel mode.
23 2006-11-29 Paul Brook <paul@codesourcery.com>
25 * arm-dis.c (coprocessor_opcodes): Fix bitfields for fconstd/fconstd.
27 2006-11-22 Daniel Jacobowitz <dan@codesourcery.com>
29 * arm-dis.c (last_is_thumb): Delete.
30 (enum map_type, last_type): New.
31 (print_insn_data): New.
32 (get_sym_code_type): Take MAP_TYPE argument. Check the type of
33 the right symbol. Handle $d.
34 (print_insn): Check for mapping symbols even without a normal
35 symbol. Adjust searching. If $d is found see how much data
36 to print. Handle data.
38 2006-11-16 Nathan Sidwell <nathan@codesourcery.com>
40 * m68k-opc.c (m68k_opcodes): Place trap instructions before set
41 conditionals. Add tpf coldfire instruction as alias for trapf.
43 2006-11-09 H.J. Lu <hongjiu.lu@intel.com>
45 * i386-dis.c (print_insn): Check PREFIX_REPNZ before
46 PREFIX_DATA when prefix user table is used.
48 2006-11-09 H.J. Lu <hongjiu.lu@intel.com>
50 * i386-dis.c (twobyte_uses_SSE_prefix): Renamed to ...
51 (twobyte_uses_DATA_prefix): This.
52 (twobyte_uses_REPNZ_prefix): New.
53 (twobyte_uses_REPZ_prefix): Likewise.
54 (threebyte_0x38_uses_DATA_prefix): Likewise.
55 (threebyte_0x38_uses_REPNZ_prefix): Likewise.
56 (threebyte_0x38_uses_REPZ_prefix): Likewise.
57 (threebyte_0x3a_uses_DATA_prefix): Likewise.
58 (threebyte_0x3a_uses_REPNZ_prefix): Likewise.
59 (threebyte_0x3a_uses_REPZ_prefix): Likewise.
60 (print_insn): Updated checking usages of DATA/REPNZ/REPZ
63 2006-11-06 Troy Rollo <troy@corvu.com.au>
65 * ppc-opc.c: Restore COM to mfcr wrongly removed 2003-07-04.
67 2006-11-01 Mei Ligang <ligang@sunnorth.com.cn>
69 * score-opc.h (score_opcodes): Delete modifier '0x'.
71 2006-10-30 Paul Brook <paul@codesourcery.com>
73 * arm-dis.c (last_is_thumb, last_mapping_sym, last_mapping_addr): New.
74 (get_sym_code_type): New function.
75 (print_insn): Search for mapping symbols.
77 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
79 * score-dis.c (print_insn): Correct the error code to print
80 correct PCE instruction disassembly.
82 2006-10-26 Ben Elliston <bje@au.ibm.com>
83 Anton Blanchard <anton@samba.org>
84 Peter Bergner <bergner@vnet.ibm.com>
86 * ppc-opc.c (A_L, DCM, DGM, TE, RMC, R, SP, S, SH16, XRT_L, EH,
87 AFRALFRC_MASK, Z, ZRC, Z_MASK, XLRT_MASK, XEH_MASK): Define.
89 (powerpc_opcodes): Extend "lwarx", "ldarx", "dcbf", "fres", "fres.",
90 "frsqrtes", "frsqrtes." "fre", "fre.", "frsqrte" and "frsqrte.".
91 Add "doze", "nap", "sleep", "rvwinkle", "dcbfl", "prtyw", "prtyd",
92 "mfcfar", "cmpb", "lfdpx", "stfdpx", "mtcfar", "mffgpr", "mftgpr",
93 "lwzcix", "lhzcix", "lbzcix", "ldcix", "lfiwax", "stwcix", "sthcix",
94 "stbcix", "stdcix", "lfdp", "dadd", "dadd.", "dqua", "dqua.", "dmul",
95 "dmul.", "drrnd", "drrnd.", "dscli", "dscli.", "dquai", "dquai.",
96 "dscri", "dscri.", "drintx", "drintx.", "dcmpo", "dtstex", "dtstdc",
97 "dtstdg", "dtstsf", "drintn", "drintn.", "dctdp", "dctdp.", "dctfix",
98 "dctfix.", "ddedpd", "ddedpd.", "dxex", "dxex.", "dsub", "dsub.",
99 "ddiv", "ddiv.", "dcmpu", "drsp", "drsp.", "dcffix", "dcffix.",
100 "denbcd", "denbcd.", "diex", "diex.", "stfdp", "daddq", "daddq.",
101 "dquaq", "dquaq.", "fcpsgn", "fcpsgn.", "dmulq", "dmulq.",
102 "drrndq", "drrndq.", "dscliq", "dscliq.", "dquaiq", "dquaiq.",
103 "dscriq", "dscriq.", "drintxq", "drintxq.", "dcmpoq", "dtstexq",
104 "dtstdcq", "dtstdgq", "dtstsfq", "drintnq", "drintnq.",
105 "dctqpq", "dctqpq.", "dctfixq", "dctfixq.", "ddedpdq", "ddedpdq.",
106 "dxexq", "dxexq.", "dsubq", "dsubq.", "ddivq", "ddivq.", "dcmpuq",
107 "drdpq", "drdpq.", "dcffixq", "dcffixq.", "denbcdq", "denbcdq.",
108 "diexq" and "diexq." opcodes.
110 2006-10-26 Daniel Jacobowitz <dan@codesourcery.com>
112 * h8300-dis.c (bfd_h8_disassemble): Add missing consts.
114 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
115 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
116 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
117 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
118 Alan Modra <amodra@bigpond.net.au>
120 * spu-dis.c: New file.
121 * spu-opc.c: New file.
122 * configure.in: Add SPU support.
123 * disassemble.c: Likewise.
124 * Makefile.am: Likewise. Run "make dep-am".
125 * Makefile.in: Regenerate.
126 * configure: Regenerate.
127 * po/POTFILES.in: Regenerate.
129 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
131 * ppc-opc.c (CELL): New define.
132 (powerpc_opcodes): Enable hrfid for Cell. Add ldbrx and stdbrx,
133 cell specific instructions. Add {st,l}x{r,l}{,l} cell specific
135 * ppc-dis.c (powerpc_dialect): Handle cell.
137 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
139 * i386-dis.c (dis386): Add support for the change in POPCNT opcode in
140 amdfam10 architecture.
142 (print_insn): Disallow REP prefix for POPCNT.
144 2006-10-20 Andrew Stubbs <andrew.stubbs@st.com>
146 * sh-dis.c (print_insn_sh): Remove 0x from output to prevent GDB
149 2006-10-18 Dave Brolley <brolley@redhat.com>
151 * configure.in (BFD_MACHINES): Add cgen-bitset.lo for bfd_sh_arch.
152 * configure: Regenerated.
154 2006-09-29 Alan Modra <amodra@bigpond.net.au>
156 * po/POTFILES.in: Regenerate.
158 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
159 Joseph Myers <joseph@codesourcery.com>
160 Ian Lance Taylor <ian@wasabisystems.com>
161 Ben Elliston <bje@wasabisystems.com>
163 * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
164 only be used with the default multiply-add operation, so if N is
165 set, don't bother printing X. Add new iwmmxt instructions.
166 (IWMMXT_INSN_COUNT): Update.
167 (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
169 (print_insn_coprocessor): Check for iWMMXt2. Handle format
172 2006-09-24 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
175 * i386-dis.c (prefix_user_table): Fix the second operand of
176 maskmovdqu instruction to allow only %xmm register instead of
177 both %xmm register and memory.
179 2006-09-23 H.J. Lu <hongjiu.lu@intel.com>
182 * i386-dis.c (OP_OFF64): Get 32bit offset if there is an
185 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
187 * score-dis.c: New file.
188 * score-opc.h: New file.
189 * Makefile.am: Add Score files.
190 * Makefile.in: Regenerate.
191 * configure.in: Add support for Score target.
192 * configure: Regenerate.
193 * disassemble.c: Add support for Score target.
195 2006-09-16 Nick Clifton <nickc@redhat.com>
196 Pedro Alves <pedro_alves@portugalmail.pt>
198 * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ
199 macros defined in bfd.h.
200 * cris-dis.c: Likewise.
201 * h8300-dis.c: Likewise.
202 * i386-dis.c: Likewise.
203 * ia64-gen.c: Likewise.
204 * mips-dis: Likewise.
206 2006-09-04 Paul Brook <paul@codesourcery.com>
208 * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
210 2006-08-23 H.J. Lu <hongjiu.lu@intel.com>
212 * i386-dis.c (three_byte_table): Expand to 256 elements.
214 2006-08-04 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
217 * i386-dis.c (MXC,EMC): Define.
218 (OP_MXC): New function to handle cvt* (convert instructions) between
219 %xmm and %mm register correctly.
221 (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
222 instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
225 2006-07-29 Richard Sandiford <richard@codesourcery.com>
227 * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
230 2006-07-19 Paul Brook <paul@codesourcery.com>
232 * armd-dis.c (arm_opcodes): Fix rbit opcode.
234 2006-07-18 H.J. Lu <hongjiu.lu@intel.com>
236 * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
237 "sldt", "str" and "smsw".
239 2006-07-15 H.J. Lu <hongjiu.lu@intel.com>
242 * i386-dis.c (GRP11_C6): NEW.
243 (GRP11_C7): Likewise.
250 (GRPPADLCK1): Likewise.
251 (GRPPADLCK2): Likewise.
252 (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
254 (grps): Add entries for GRP11_C6 and GRP11_C7.
256 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
257 Michael Meissner <michael.meissner@amd.com>
259 * i386-dis.c (dis386): Add support for 4 operand instructions. Add
260 support for amdfam10 SSE4a/ABM instructions. Modify all
261 initializer macros to have additional arguments. Disallow REP
262 prefix for non-string instructions.
265 2006-07-05 Julian Brown <julian@codesourcery.com>
267 * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
269 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
271 * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
272 (twobyte_has_modrm): Set 1 for 0x1f.
274 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
276 * i386-dis.c (NOP_Fixup): Removed.
278 (NOP_Fixup2): Likewise.
279 (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
281 2006-06-12 Julian Brown <julian@codesourcery.com>
283 * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
286 2006-06-10 H.J. Lu <hongjiu.lu@intel.com>
288 * i386.c (GRP10): Renamed to ...
290 (GRP11): Renamed to ...
292 (GRP12): Renamed to ...
294 (GRP13): Renamed to ...
296 (GRP14): Renamed to ...
298 (dis386_twobyte): Updated.
301 2006-06-09 Nick Clifton <nickc@redhat.com>
303 * po/fi.po: Updated Finnish translation.
305 2006-06-07 Joseph S. Myers <joseph@codesourcery.com>
307 * po/Make-in (pdf, ps): New dummy targets.
309 2006-06-06 Paul Brook <paul@codesourcery.com>
311 * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
313 (neon_opcodes): Add conditional execution specifiers.
314 (thumb_opcodes): Ditto.
315 (thumb32_opcodes): Ditto.
316 (arm_conditional): Change 0xe to "al" and add "" to end.
317 (ifthen_state, ifthen_next_state, ifthen_address): New.
318 (IFTHEN_COND): Define.
319 (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
320 (print_insn_arm): Change %c to use new values of arm_conditional.
321 (print_insn_thumb16): Print thumb conditions. Add %I.
322 (print_insn_thumb32): Print thumb conditions.
323 (find_ifthen_state): New function.
324 (print_insn): Track IT block state.
326 2006-06-06 Ben Elliston <bje@au.ibm.com>
327 Anton Blanchard <anton@samba.org>
328 Peter Bergner <bergner@vnet.ibm.com>
330 * ppc-dis.c (powerpc_dialect): Handle power6 option.
331 (print_ppc_disassembler_options): Mention power6.
333 2006-06-06 Thiemo Seufer <ths@mips.com>
334 Chao-ying Fu <fu@mips.com>
336 * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
337 * mips-opc.c: Add DSP64 instructions.
339 2006-06-06 Alan Modra <amodra@bigpond.net.au>
341 * m68hc11-dis.c (print_insn): Warning fix.
343 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
345 * po/Make-in (top_builddir): Define.
347 2006-06-05 Alan Modra <amodra@bigpond.net.au>
349 * Makefile.am: Run "make dep-am".
350 * Makefile.in: Regenerate.
351 * config.in: Regenerate.
353 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
355 * Makefile.am (INCLUDES): Use @INCINTL@.
356 * acinclude.m4: Include new gettext macros.
357 * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
358 Remove local code for po/Makefile.
359 * Makefile.in, aclocal.m4, configure: Regenerated.
361 2006-05-30 Nick Clifton <nickc@redhat.com>
363 * po/es.po: Updated Spanish translation.
365 2006-05-25 Richard Sandiford <richard@codesourcery.com>
367 * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
368 and fmovem entries. Put register list entries before immediate
369 mask entries. Use "l" rather than "L" in the fmovem entries.
370 * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
372 (m68k_scan_mask): New function, split out from...
373 (print_insn_m68k): ...here. If no architecture has been set,
374 first try printing an m680x0 instruction, then try a Coldfire one.
376 2006-05-24 Nick Clifton <nickc@redhat.com>
378 * po/ga.po: Updated Irish translation.
380 2006-05-22 Nick Clifton <nickc@redhat.com>
382 * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
384 2006-05-22 Nick Clifton <nickc@redhat.com>
386 * po/nl.po: Updated translation.
388 2006-05-18 Alan Modra <amodra@bigpond.net.au>
390 * avr-dis.c: Formatting fix.
392 2006-05-14 Thiemo Seufer <ths@mips.com>
394 * mips16-opc.c (I1, I32, I64): New shortcut defines.
395 (mips16_opcodes): Change membership of instructions to their
398 2006-05-09 H.J. Lu <hongjiu.lu@intel.com>
400 * i386-dis.c (grps): Update sgdt/sidt for 64bit.
402 2006-05-05 Julian Brown <julian@codesourcery.com>
404 * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
407 2006-05-05 Thiemo Seufer <ths@mips.com>
408 David Ung <davidu@mips.com>
410 * mips-opc.c: Add macro for cache instruction.
412 2006-05-04 Thiemo Seufer <ths@mips.com>
413 Nigel Stephens <nigel@mips.com>
414 David Ung <davidu@mips.com>
416 * mips-dis.c (mips_arch_choices): Add smartmips instruction
417 decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
418 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
420 * mips-opc.c: fix random typos in comments.
421 (INSN_SMARTMIPS): New defines.
422 (mips_builtin_opcodes): Add paired single support for MIPS32R2.
423 Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
424 flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
425 FP_S and FP_D flags to denote single and double register
426 accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
427 Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
428 for MIPS32R2. Add SmartMIPS instructions. Add two-argument
429 variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
431 * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
433 2006-05-03 Thiemo Seufer <ths@mips.com>
435 * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
437 2006-05-02 Thiemo Seufer <ths@mips.com>
438 Nigel Stephens <nigel@mips.com>
439 David Ung <davidu@mips.com>
441 * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
442 (print_mips16_insn_arg): Force mips16 to odd addresses.
444 2006-04-30 Thiemo Seufer <ths@mips.com>
445 David Ung <davidu@mips.com>
447 * mips-opc.c (mips_builtin_opcodes): Add udi instructions
449 * mips-dis.c (print_insn_args): Adds udi argument handling.
451 2006-04-28 James E Wilson <wilson@specifix.com>
453 * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
456 2006-04-28 Thiemo Seufer <ths@mips.com>
457 David Ung <davidu@mips.com>
458 Nigel Stephens <nigel@mips.com>
460 * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
463 2006-04-28 Thiemo Seufer <ths@mips.com>
464 Nigel Stephens <nigel@mips.com>
465 David Ung <davidu@mips.com>
467 * mips-dis.c (print_insn_args): Add mips_opcode argument.
468 (print_insn_mips): Adjust print_insn_args call.
470 2006-04-28 Thiemo Seufer <ths@mips.com>
471 Nigel Stephens <nigel@mips.com>
473 * mips-dis.c (print_insn_args): Print $fcc only for FP
474 instructions, use $cc elsewise.
476 2006-04-28 Thiemo Seufer <ths@mips.com>
477 Nigel Stephens <nigel@mips.com>
479 * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
480 Map MIPS16 registers to O32 names.
481 (print_mips16_insn_arg): Use mips16_reg_names.
483 2006-04-26 Julian Brown <julian@codesourcery.com>
485 * arm-dis.c (print_insn_neon): Disassemble floating-point constant
488 2006-04-26 Nathan Sidwell <nathan@codesourcery.com>
489 Julian Brown <julian@codesourcery.com>
491 * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
492 %<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?].
493 Add unified load/store instruction names.
494 (neon_opcode_table): New.
495 (arm_opcodes): Expand meaning of %<bitfield>['`?].
496 (arm_decode_bitfield): New.
497 (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
498 Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
499 (print_insn_neon): New.
500 (print_insn_arm): Adjust print_insn_coprocessor call. Call
501 print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
502 (print_insn_thumb32): Likewise.
504 2006-04-19 Alan Modra <amodra@bigpond.net.au>
506 * Makefile.am: Run "make dep-am".
507 * Makefile.in: Regenerate.
509 2006-04-19 Alan Modra <amodra@bigpond.net.au>
511 * avr-dis.c (avr_operand): Warning fix.
513 * configure: Regenerate.
515 2006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
517 * po/POTFILES.in: Regenerated.
519 2006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de>
522 * avr-dis.c (avr_operand): Arrange for a comment to appear before
523 the symolic form of an address, so that the output of objdump -d
526 2006-04-10 DJ Delorie <dj@redhat.com>
528 * m32c-asm.c: Regenerate.
530 2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
532 * Makefile.am: Add install-html target.
533 * Makefile.in: Regenerate.
535 2006-04-06 Nick Clifton <nickc@redhat.com>
537 * po/vi/po: Updated Vietnamese translation.
539 2006-03-31 Paul Koning <ni1d@arrl.net>
541 * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
543 2006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
545 * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
546 logic to identify halfword shifts.
548 2006-03-16 Paul Brook <paul@codesourcery.com>
550 * arm-dis.c (arm_opcodes): Rename swi to svc.
551 (thumb_opcodes): Ditto.
553 2006-03-13 DJ Delorie <dj@redhat.com>
555 * m32c-asm.c: Regenerate.
556 * m32c-desc.c: Likewise.
557 * m32c-desc.h: Likewise.
558 * m32c-dis.c: Likewise.
559 * m32c-ibld.c: Likewise.
560 * m32c-opc.c: Likewise.
561 * m32c-opc.h: Likewise.
563 2006-03-10 DJ Delorie <dj@redhat.com>
565 * m32c-desc.c: Regenerate with mul.l, mulu.l.
566 * m32c-opc.c: Likewise.
567 * m32c-opc.h: Likewise.
570 2006-03-09 Nick Clifton <nickc@redhat.com>
572 * po/sv.po: Updated Swedish translation.
574 2006-03-07 H.J. Lu <hongjiu.lu@intel.com>
577 * i386-dis.c (REP_Fixup): New function.
578 (AL): Remove duplicate.
583 (indirDXr): Likewise.
586 (dis386): Updated entries of ins, outs, movs, lods and stos.
588 2006-03-05 Nick Clifton <nickc@redhat.com>
590 * cgen-ibld.in (insert_normal): Cope with attempts to insert a
591 signed 32-bit value into an unsigned 32-bit field when the host is
593 * fr30-ibld.c: Regenerate.
594 * frv-ibld.c: Regenerate.
595 * ip2k-ibld.c: Regenerate.
596 * iq2000-asm.c: Regenerate.
597 * iq2000-ibld.c: Regenerate.
598 * m32c-ibld.c: Regenerate.
599 * m32r-ibld.c: Regenerate.
600 * openrisc-ibld.c: Regenerate.
601 * xc16x-ibld.c: Regenerate.
602 * xstormy16-ibld.c: Regenerate.
604 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
606 * xc16x-asm.c: Regenerate.
607 * xc16x-dis.c: Regenerate.
609 2006-02-27 Carlos O'Donell <carlos@codesourcery.com>
611 * po/Make-in: Add html target.
613 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
615 * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
616 Intel Merom New Instructions.
617 (THREE_BYTE_0): Likewise.
618 (THREE_BYTE_1): Likewise.
619 (three_byte_table): Likewise.
620 (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
621 THREE_BYTE_1 for entry 0x3a.
622 (twobyte_has_modrm): Updated.
623 (twobyte_uses_SSE_prefix): Likewise.
624 (print_insn): Handle 3-byte opcodes used by Intel Merom New
627 2006-02-24 David S. Miller <davem@sunset.davemloft.net>
629 * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
630 (v9_hpriv_reg_names): New table.
631 (print_insn_sparc): Allow values up to 16 for '?' and '!'.
632 New cases '$' and '%' for read/write hyperprivileged register.
633 * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
634 window handling and rdhpr/wrhpr instructions.
636 2006-02-24 DJ Delorie <dj@redhat.com>
638 * m32c-desc.c: Regenerate with linker relaxation attributes.
639 * m32c-desc.h: Likewise.
640 * m32c-dis.c: Likewise.
641 * m32c-opc.c: Likewise.
643 2006-02-24 Paul Brook <paul@codesourcery.com>
645 * arm-dis.c (arm_opcodes): Add V7 instructions.
646 (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
647 (print_arm_address): New function.
648 (print_insn_arm): Use it. Add 'P' and 'U' cases.
649 (psr_name): New function.
650 (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
652 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
654 * ia64-opc-i.c (bXc): New.
656 (OpX2TaTbYaXcC): Likewise.
659 (ia64_opcodes_i): Add instructions for tf.
661 * ia64-opc.h (IMMU5b): New.
663 * ia64-asmtab.c: Regenerated.
665 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
667 * ia64-gen.c: Update copyright years.
668 * ia64-opc-b.c: Likewise.
670 2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
672 * ia64-gen.c (lookup_regindex): Handle ".vm".
673 (print_dependency_table): Handle '\"'.
675 * ia64-ic.tbl: Updated from SDM 2.2.
676 * ia64-raw.tbl: Likewise.
677 * ia64-waw.tbl: Likewise.
678 * ia64-asmtab.c: Regenerated.
680 * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
682 2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
683 Anil Paranjape <anilp1@kpitcummins.com>
684 Shilin Shakti <shilins@kpitcummins.com>
686 * xc16x-desc.h: New file
687 * xc16x-desc.c: New file
688 * xc16x-opc.h: New file
689 * xc16x-opc.c: New file
690 * xc16x-ibld.c: New file
691 * xc16x-asm.c: New file
692 * xc16x-dis.c: New file
693 * Makefile.am: Entries for xc16x
694 * Makefile.in: Regenerate
695 * cofigure.in: Add xc16x target information.
696 * configure: Regenerate.
697 * disassemble.c: Add xc16x target information.
699 2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
701 * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
704 2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
706 * i386-dis.c ('Z'): Add a new macro.
707 (dis386_twobyte): Use "movZ" for control register moves.
709 2006-02-10 Nick Clifton <nickc@redhat.com>
711 * iq2000-asm.c: Regenerate.
713 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
715 * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
717 2006-01-26 David Ung <davidu@mips.com>
719 * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
720 ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
721 floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
722 nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
723 rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
725 2006-01-18 Arnold Metselaar <arnoldm@sourceware.org>
727 * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
728 ld_d_r, pref_xd_cb): Use signed char to hold data to be
730 * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
731 buffer overflows when disassembling instructions like
733 * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
734 operand, if the offset is negative.
736 2006-01-17 Arnold Metselaar <arnoldm@sourceware.org>
738 * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
739 unsigned char to hold data to be disassembled.
741 2006-01-17 Andreas Schwab <schwab@suse.de>
744 * disassemble.c (disassemble_init_for_target): Set
745 disassembler_needs_relocs for bfd_arch_arm.
747 2006-01-16 Paul Brook <paul@codesourcery.com>
749 * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
750 f?add?, and f?sub? instructions.
752 2006-01-16 Nick Clifton <nickc@redhat.com>
754 * po/zh_CN.po: New Chinese (simplified) translation.
755 * configure.in (ALL_LINGUAS): Add "zh_CH".
756 * configure: Regenerate.
758 2006-01-05 Paul Brook <paul@codesourcery.com>
760 * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
762 2006-01-06 DJ Delorie <dj@redhat.com>
764 * m32c-desc.c: Regenerate.
765 * m32c-opc.c: Regenerate.
766 * m32c-opc.h: Regenerate.
768 2006-01-03 DJ Delorie <dj@redhat.com>
770 * cgen-ibld.in (extract_normal): Avoid memory range errors.
771 * m32c-ibld.c: Regenerated.
773 For older changes see ChangeLog-2005
779 version-control: never